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to be specified with write and rdwr mports
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roadblock in assigning clocked ports
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all feature tests. Deleted CondRead because it tested a problem we don't have any more
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Decided to not have Conditionally in low firrtl - instead, Print and
Stop have enables
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emitting ports (and the assignments to them)
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Lower Types pass. #53
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support for -b <backend> flag without any other specified passes in stanza, updated parser tests to work with stanza implementation.
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Updated Scala FIRRTL with Testing and Infer-Types Pass
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sense for some applications, also fixed up printing to better match stanza implementation
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printing to match stanza implementation
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for unknown width. Also added test to check this
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Change of FIRRTL semantics!
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Fix init accessor
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Assignments to a register are no longer affected by enclosing when
statements:
when p :
reg r : UInt,clk,reset
r := a
will lower to:
reg r : UInt,clk,reset
r := a
instead of:
reg r : UInt,clk,reset
when p : r := a
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StandardVerilogCompiler
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particular directory structure.
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catching of initialization of accessors. Missing use case of accessing an accessor. Still need to update tests to pass
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enable with muxing the index with poison bits
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conditional assignment
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now be small examples, categorized by either passes, errors, or features.
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Updated tests to match. #29.
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extract, not >>
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