Added new const propagation test

1 files changed, 11 insertions, 0 deletions

diff --git a/test/passes/const-prop/bits.fir b/test/passes/const-prop/bits.fir
new file mode 100644
index 00000000..16d678b3
--- /dev/null
+++ b/test/passes/const-prop/bits.fir
@@ -0,0 +1,11 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p cT 2>&1 | tee %s.out | FileCheck %s
+
+;CHECK: Constant Propagation
+;CHECK: node x = UInt("h7")
+;CHECK: Finished Constant Propagation
+
+circuit top :
+   module top :
+      output out : UInt
+      node x = bits(UInt(127),2,0)
+      out := x