diff options
| author | azidar | 2015-12-09 18:31:45 -0800 |
|---|---|---|
| committer | azidar | 2016-01-16 14:28:17 -0800 |
| commit | be78d49aa01c097978f69a3b022acb2047fdf438 (patch) | |
| tree | 76dc4b32b5e6861938404ebb4d124ca5b87d13a5 /test | |
| parent | c427b31a1ef8361b643d5f7435aeb42472dfe626 (diff) | |
New memory works with verilog. Slowly changing tests and fixing bugs.
Decided to not have Conditionally in low firrtl - instead, Print and
Stop have enables
Diffstat (limited to 'test')
99 files changed, 1137 insertions, 1114 deletions
diff --git a/test/custom/when-coverage/gcd.fir b/test/custom/when-coverage/gcd.fir index 4c1409d1..b07c313b 100644 --- a/test/custom/when-coverage/gcd.fir +++ b/test/custom/when-coverage/gcd.fir @@ -7,7 +7,7 @@ circuit top : input x : UInt input y : UInt output q : UInt - q := subw(x, y) + q <= subw(x, y) module gcd : input a : UInt<16> input b : UInt<16> @@ -18,23 +18,23 @@ circuit top : output v : UInt<1> reg x : UInt,clk,reset reg y : UInt,clk,reset - onreset x := UInt(0) - onreset y := UInt(42) + onreset x <= UInt(0) + onreset y <= UInt(42) when gt(x, y) : inst s of subtracter - s.x := x - s.y := y - x := s.q + s.x <= x + s.y <= y + x <= s.q else : inst s2 of subtracter - s2.x := x - s2.y := y - y := s2.q + s2.x <= x + s2.y <= y + y <= s2.q when e : - x := a - y := b - v := eqv(v, UInt(0)) - z := x + x <= a + y <= b + v <= eqv(v, UInt(0)) + z <= x module top : input a : UInt<16> input b : UInt<16> @@ -42,11 +42,11 @@ circuit top : input reset : UInt<1> output z : UInt inst i of gcd - i.a := a - i.b := b - i.e := UInt(1) - i.clk := clk - i.reset := reset - z := i.z + i.a <= a + i.b <= b + i.e <= UInt(1) + i.clk <= clk + i.reset <= reset + z <= i.z ;CHECK: Done! diff --git a/test/errors/gender/BulkWrong.fir b/test/errors/gender/BulkWrong.fir index 830e8156..1becd104 100644 --- a/test/errors/gender/BulkWrong.fir +++ b/test/errors/gender/BulkWrong.fir @@ -9,18 +9,18 @@ circuit BTB : input in : {x : UInt<1>, flip y : {flip z : UInt<1>}} output out : {x : UInt<1>, flip y : {flip z : UInt<1>}} - in <> out - out.y <> in.y - out.y.z <> in.y.z + in <- out + out.y <- in.y + out.y.z <- in.y.z wire w : {x : UInt<1>, flip y : {flip z : UInt<1>}} - w <> in - in.y <> w.y - in.y.z <> w.y.z + w <- in + in.y <- w.y + in.y.z <- w.y.z - w.x := addw(in.x,in.y.z) + w.x <= addw(in.x,in.y.z) - out <> in - in.y <> out.y - in.y.z <> out.y.z + out <- in + in.y <- out.y + in.y.z <- out.y.z diff --git a/test/errors/gender/InstancePorts.fir b/test/errors/gender/InstancePorts.fir index 55d5fd46..3f5ae8c7 100644 --- a/test/errors/gender/InstancePorts.fir +++ b/test/errors/gender/InstancePorts.fir @@ -6,12 +6,12 @@ circuit BTB : module Queue : input in : UInt<1> output out : UInt<1> - out := in + out <= in module BTB : input time : UInt<1> output out : UInt<1> inst queue of Queue - queue.in := time - out := queue.in + queue.in <= time + out <= queue.in diff --git a/test/errors/gender/ReadOutput.fir b/test/errors/gender/ReadOutput.fir index 14ac75c1..fd3607d0 100644 --- a/test/errors/gender/ReadOutput.fir +++ b/test/errors/gender/ReadOutput.fir @@ -6,7 +6,7 @@ circuit BTB : output out : {x : UInt<1>, flip y : UInt<1>} wire w : {x : UInt<1>, flip y : UInt<1>} - w.x := UInt(1) - w.y := UInt(1) - out.x := UInt(1) - w <> out + w.x <= UInt(1) + w.y <= UInt(1) + out.x <= UInt(1) + w <- out diff --git a/test/errors/gender/bad_bulk_connect.fir b/test/errors/gender/bad_bulk_connect.fir index f0891b9e..984d8da0 100644 --- a/test/errors/gender/bad_bulk_connect.fir +++ b/test/errors/gender/bad_bulk_connect.fir @@ -8,321 +8,321 @@ circuit ClientTileLinkIOWrapper_49 : input in : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}} output out : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}} - in.grant.bits.g_type := UInt<1>("h00") - in.grant.bits.is_builtin_type := UInt<1>("h00") - in.grant.bits.manager_xact_id := UInt<1>("h00") - in.grant.bits.client_xact_id := UInt<1>("h00") - in.grant.bits.data := UInt<1>("h00") - in.grant.bits.addr_beat := UInt<1>("h00") - in.grant.valid := UInt<1>("h00") - in.acquire.ready := UInt<1>("h00") - out.release.bits.voluntary := UInt<1>("h00") - out.release.bits.r_type := UInt<1>("h00") - out.release.bits.data := UInt<1>("h00") - out.release.bits.addr_beat := UInt<1>("h00") - out.release.bits.client_xact_id := UInt<1>("h00") - out.release.bits.addr_block := UInt<1>("h00") - out.release.valid := UInt<1>("h00") - out.probe.ready := UInt<1>("h00") - out.grant.ready := UInt<1>("h00") - out.acquire.bits.union := UInt<1>("h00") - out.acquire.bits.a_type := UInt<1>("h00") - out.acquire.bits.is_builtin_type := UInt<1>("h00") - out.acquire.bits.data := UInt<1>("h00") - out.acquire.bits.addr_beat := UInt<1>("h00") - out.acquire.bits.client_xact_id := UInt<1>("h00") - out.acquire.bits.addr_block := UInt<1>("h00") - out.acquire.valid := UInt<1>("h00") + in.grant.bits.g_type <= UInt<1>("h00") + in.grant.bits.is_builtin_type <= UInt<1>("h00") + in.grant.bits.manager_xact_id <= UInt<1>("h00") + in.grant.bits.client_xact_id <= UInt<1>("h00") + in.grant.bits.data <= UInt<1>("h00") + in.grant.bits.addr_beat <= UInt<1>("h00") + in.grant.valid <= UInt<1>("h00") + in.acquire.ready <= UInt<1>("h00") + out.release.bits.voluntary <= UInt<1>("h00") + out.release.bits.r_type <= UInt<1>("h00") + out.release.bits.data <= UInt<1>("h00") + out.release.bits.addr_beat <= UInt<1>("h00") + out.release.bits.client_xact_id <= UInt<1>("h00") + out.release.bits.addr_block <= UInt<1>("h00") + out.release.valid <= UInt<1>("h00") + out.probe.ready <= UInt<1>("h00") + out.grant.ready <= UInt<1>("h00") + out.acquire.bits.union <= UInt<1>("h00") + out.acquire.bits.a_type <= UInt<1>("h00") + out.acquire.bits.is_builtin_type <= UInt<1>("h00") + out.acquire.bits.data <= UInt<1>("h00") + out.acquire.bits.addr_beat <= UInt<1>("h00") + out.acquire.bits.client_xact_id <= UInt<1>("h00") + out.acquire.bits.addr_block <= UInt<1>("h00") + out.acquire.valid <= UInt<1>("h00") wire T_173394 : UInt<2>[2] - T_173394[0] := UInt<2>("h01") - T_173394[1] := UInt<2>("h02") + T_173394[0] <= UInt<2>("h01") + T_173394[1] <= UInt<2>("h02") wire T_173397 : UInt<2>[2] - T_173397[0] := UInt<2>("h01") - T_173397[1] := UInt<2>("h02") + T_173397[0] <= UInt<2>("h01") + T_173397[1] <= UInt<2>("h02") wire T_173399 : UInt<2>[1] - T_173399[0] := UInt<2>("h02") + T_173399[0] <= UInt<2>("h02") wire T_173439 : UInt<2>[2] - T_173439[0] := UInt<2>("h01") - T_173439[1] := UInt<2>("h02") + T_173439[0] <= UInt<2>("h01") + T_173439[1] <= UInt<2>("h02") wire T_173442 : UInt<2>[2] - T_173442[0] := UInt<2>("h01") - T_173442[1] := UInt<2>("h02") + T_173442[0] <= UInt<2>("h01") + T_173442[1] <= UInt<2>("h02") wire T_173444 : UInt<2>[1] - T_173444[0] := UInt<2>("h02") + T_173444[0] <= UInt<2>("h02") wire T_173483 : UInt<2>[2] - T_173483[0] := UInt<2>("h01") - T_173483[1] := UInt<2>("h02") + T_173483[0] <= UInt<2>("h01") + T_173483[1] <= UInt<2>("h02") wire T_173486 : UInt<2>[2] - T_173486[0] := UInt<2>("h01") - T_173486[1] := UInt<2>("h02") + T_173486[0] <= UInt<2>("h01") + T_173486[1] <= UInt<2>("h02") wire T_173488 : UInt<2>[1] - T_173488[0] := UInt<2>("h02") + T_173488[0] <= UInt<2>("h02") wire T_173537 : UInt<2>[2] - T_173537[0] := UInt<2>("h01") - T_173537[1] := UInt<2>("h02") + T_173537[0] <= UInt<2>("h01") + T_173537[1] <= UInt<2>("h02") wire T_173540 : UInt<2>[2] - T_173540[0] := UInt<2>("h01") - T_173540[1] := UInt<2>("h02") + T_173540[0] <= UInt<2>("h01") + T_173540[1] <= UInt<2>("h02") wire T_173542 : UInt<2>[1] - T_173542[0] := UInt<2>("h02") + T_173542[0] <= UInt<2>("h02") wire T_173588 : UInt<2>[2] - T_173588[0] := UInt<2>("h01") - T_173588[1] := UInt<2>("h02") + T_173588[0] <= UInt<2>("h01") + T_173588[1] <= UInt<2>("h02") wire T_173591 : UInt<2>[2] - T_173591[0] := UInt<2>("h01") - T_173591[1] := UInt<2>("h02") + T_173591[0] <= UInt<2>("h01") + T_173591[1] <= UInt<2>("h02") wire T_173593 : UInt<2>[1] - T_173593[0] := UInt<2>("h02") + T_173593[0] <= UInt<2>("h02") wire T_173639 : UInt<2>[2] - T_173639[0] := UInt<2>("h01") - T_173639[1] := UInt<2>("h02") + T_173639[0] <= UInt<2>("h01") + T_173639[1] <= UInt<2>("h02") wire T_173642 : UInt<2>[2] - T_173642[0] := UInt<2>("h01") - T_173642[1] := UInt<2>("h02") + T_173642[0] <= UInt<2>("h01") + T_173642[1] <= UInt<2>("h02") wire T_173644 : UInt<2>[1] - T_173644[0] := UInt<2>("h02") + T_173644[0] <= UInt<2>("h02") wire T_173692 : UInt<2>[2] - T_173692[0] := UInt<2>("h01") - T_173692[1] := UInt<2>("h02") + T_173692[0] <= UInt<2>("h01") + T_173692[1] <= UInt<2>("h02") wire T_173695 : UInt<2>[2] - T_173695[0] := UInt<2>("h01") - T_173695[1] := UInt<2>("h02") + T_173695[0] <= UInt<2>("h01") + T_173695[1] <= UInt<2>("h02") wire T_173697 : UInt<2>[1] - T_173697[0] := UInt<2>("h02") + T_173697[0] <= UInt<2>("h02") wire T_173742 : UInt<2>[2] - T_173742[0] := UInt<2>("h01") - T_173742[1] := UInt<2>("h02") + T_173742[0] <= UInt<2>("h01") + T_173742[1] <= UInt<2>("h02") wire T_173745 : UInt<2>[2] - T_173745[0] := UInt<2>("h01") - T_173745[1] := UInt<2>("h02") + T_173745[0] <= UInt<2>("h01") + T_173745[1] <= UInt<2>("h02") wire T_173747 : UInt<2>[1] - T_173747[0] := UInt<2>("h02") + T_173747[0] <= UInt<2>("h02") wire T_173795 : UInt<2>[2] - T_173795[0] := UInt<2>("h01") - T_173795[1] := UInt<2>("h02") + T_173795[0] <= UInt<2>("h01") + T_173795[1] <= UInt<2>("h02") wire T_173798 : UInt<2>[2] - T_173798[0] := UInt<2>("h01") - T_173798[1] := UInt<2>("h02") + T_173798[0] <= UInt<2>("h01") + T_173798[1] <= UInt<2>("h02") wire T_173800 : UInt<2>[1] - T_173800[0] := UInt<2>("h02") + T_173800[0] <= UInt<2>("h02") wire T_173845 : UInt<2>[2] - T_173845[0] := UInt<2>("h01") - T_173845[1] := UInt<2>("h02") + T_173845[0] <= UInt<2>("h01") + T_173845[1] <= UInt<2>("h02") wire T_173848 : UInt<2>[2] - T_173848[0] := UInt<2>("h01") - T_173848[1] := UInt<2>("h02") + T_173848[0] <= UInt<2>("h01") + T_173848[1] <= UInt<2>("h02") wire T_173850 : UInt<2>[1] - T_173850[0] := UInt<2>("h02") + T_173850[0] <= UInt<2>("h02") wire T_173895 : UInt<2>[2] - T_173895[0] := UInt<2>("h01") - T_173895[1] := UInt<2>("h02") + T_173895[0] <= UInt<2>("h01") + T_173895[1] <= UInt<2>("h02") wire T_173898 : UInt<2>[2] - T_173898[0] := UInt<2>("h01") - T_173898[1] := UInt<2>("h02") + T_173898[0] <= UInt<2>("h01") + T_173898[1] <= UInt<2>("h02") wire T_173900 : UInt<2>[1] - T_173900[0] := UInt<2>("h02") + T_173900[0] <= UInt<2>("h02") wire T_173939 : UInt<2>[2] - T_173939[0] := UInt<2>("h01") - T_173939[1] := UInt<2>("h02") + T_173939[0] <= UInt<2>("h01") + T_173939[1] <= UInt<2>("h02") wire T_173942 : UInt<2>[2] - T_173942[0] := UInt<2>("h01") - T_173942[1] := UInt<2>("h02") + T_173942[0] <= UInt<2>("h01") + T_173942[1] <= UInt<2>("h02") wire T_173944 : UInt<2>[1] - T_173944[0] := UInt<2>("h02") + T_173944[0] <= UInt<2>("h02") wire T_173993 : UInt<2>[2] - T_173993[0] := UInt<2>("h01") - T_173993[1] := UInt<2>("h02") + T_173993[0] <= UInt<2>("h01") + T_173993[1] <= UInt<2>("h02") wire T_173996 : UInt<2>[2] - T_173996[0] := UInt<2>("h01") - T_173996[1] := UInt<2>("h02") + T_173996[0] <= UInt<2>("h01") + T_173996[1] <= UInt<2>("h02") wire T_173998 : UInt<2>[1] - T_173998[0] := UInt<2>("h02") + T_173998[0] <= UInt<2>("h02") wire T_174044 : UInt<2>[2] - T_174044[0] := UInt<2>("h01") - T_174044[1] := UInt<2>("h02") + T_174044[0] <= UInt<2>("h01") + T_174044[1] <= UInt<2>("h02") wire T_174047 : UInt<2>[2] - T_174047[0] := UInt<2>("h01") - T_174047[1] := UInt<2>("h02") + T_174047[0] <= UInt<2>("h01") + T_174047[1] <= UInt<2>("h02") wire T_174049 : UInt<2>[1] - T_174049[0] := UInt<2>("h02") + T_174049[0] <= UInt<2>("h02") wire T_174095 : UInt<2>[2] - T_174095[0] := UInt<2>("h01") - T_174095[1] := UInt<2>("h02") + T_174095[0] <= UInt<2>("h01") + T_174095[1] <= UInt<2>("h02") wire T_174098 : UInt<2>[2] - T_174098[0] := UInt<2>("h01") - T_174098[1] := UInt<2>("h02") + T_174098[0] <= UInt<2>("h01") + T_174098[1] <= UInt<2>("h02") wire T_174100 : UInt<2>[1] - T_174100[0] := UInt<2>("h02") + T_174100[0] <= UInt<2>("h02") wire T_174148 : UInt<2>[2] - T_174148[0] := UInt<2>("h01") - T_174148[1] := UInt<2>("h02") + T_174148[0] <= UInt<2>("h01") + T_174148[1] <= UInt<2>("h02") wire T_174151 : UInt<2>[2] - T_174151[0] := UInt<2>("h01") - T_174151[1] := UInt<2>("h02") + T_174151[0] <= UInt<2>("h01") + T_174151[1] <= UInt<2>("h02") wire T_174153 : UInt<2>[1] - T_174153[0] := UInt<2>("h02") + T_174153[0] <= UInt<2>("h02") wire T_174198 : UInt<2>[2] - T_174198[0] := UInt<2>("h01") - T_174198[1] := UInt<2>("h02") + T_174198[0] <= UInt<2>("h01") + T_174198[1] <= UInt<2>("h02") wire T_174201 : UInt<2>[2] - T_174201[0] := UInt<2>("h01") - T_174201[1] := UInt<2>("h02") + T_174201[0] <= UInt<2>("h01") + T_174201[1] <= UInt<2>("h02") wire T_174203 : UInt<2>[1] - T_174203[0] := UInt<2>("h02") + T_174203[0] <= UInt<2>("h02") wire T_174251 : UInt<2>[2] - T_174251[0] := UInt<2>("h01") - T_174251[1] := UInt<2>("h02") + T_174251[0] <= UInt<2>("h01") + T_174251[1] <= UInt<2>("h02") wire T_174254 : UInt<2>[2] - T_174254[0] := UInt<2>("h01") - T_174254[1] := UInt<2>("h02") + T_174254[0] <= UInt<2>("h01") + T_174254[1] <= UInt<2>("h02") wire T_174256 : UInt<2>[1] - T_174256[0] := UInt<2>("h02") + T_174256[0] <= UInt<2>("h02") wire T_174301 : UInt<2>[2] - T_174301[0] := UInt<2>("h01") - T_174301[1] := UInt<2>("h02") + T_174301[0] <= UInt<2>("h01") + T_174301[1] <= UInt<2>("h02") wire T_174304 : UInt<2>[2] - T_174304[0] := UInt<2>("h01") - T_174304[1] := UInt<2>("h02") + T_174304[0] <= UInt<2>("h01") + T_174304[1] <= UInt<2>("h02") wire T_174306 : UInt<2>[1] - T_174306[0] := UInt<2>("h02") + T_174306[0] <= UInt<2>("h02") wire T_174351 : UInt<2>[2] - T_174351[0] := UInt<2>("h01") - T_174351[1] := UInt<2>("h02") + T_174351[0] <= UInt<2>("h01") + T_174351[1] <= UInt<2>("h02") wire T_174354 : UInt<2>[2] - T_174354[0] := UInt<2>("h01") - T_174354[1] := UInt<2>("h02") + T_174354[0] <= UInt<2>("h01") + T_174354[1] <= UInt<2>("h02") wire T_174356 : UInt<2>[1] - T_174356[0] := UInt<2>("h02") + T_174356[0] <= UInt<2>("h02") wire T_174395 : UInt<2>[2] - T_174395[0] := UInt<2>("h01") - T_174395[1] := UInt<2>("h02") + T_174395[0] <= UInt<2>("h01") + T_174395[1] <= UInt<2>("h02") wire T_174398 : UInt<2>[2] - T_174398[0] := UInt<2>("h01") - T_174398[1] := UInt<2>("h02") + T_174398[0] <= UInt<2>("h01") + T_174398[1] <= UInt<2>("h02") wire T_174400 : UInt<2>[1] - T_174400[0] := UInt<2>("h02") + T_174400[0] <= UInt<2>("h02") wire T_174449 : UInt<2>[2] - T_174449[0] := UInt<2>("h01") - T_174449[1] := UInt<2>("h02") + T_174449[0] <= UInt<2>("h01") + T_174449[1] <= UInt<2>("h02") wire T_174452 : UInt<2>[2] - T_174452[0] := UInt<2>("h01") - T_174452[1] := UInt<2>("h02") + T_174452[0] <= UInt<2>("h01") + T_174452[1] <= UInt<2>("h02") wire T_174454 : UInt<2>[1] - T_174454[0] := UInt<2>("h02") + T_174454[0] <= UInt<2>("h02") wire T_174500 : UInt<2>[2] - T_174500[0] := UInt<2>("h01") - T_174500[1] := UInt<2>("h02") + T_174500[0] <= UInt<2>("h01") + T_174500[1] <= UInt<2>("h02") wire T_174503 : UInt<2>[2] - T_174503[0] := UInt<2>("h01") - T_174503[1] := UInt<2>("h02") + T_174503[0] <= UInt<2>("h01") + T_174503[1] <= UInt<2>("h02") wire T_174505 : UInt<2>[1] - T_174505[0] := UInt<2>("h02") + T_174505[0] <= UInt<2>("h02") wire T_174551 : UInt<2>[2] - T_174551[0] := UInt<2>("h01") - T_174551[1] := UInt<2>("h02") + T_174551[0] <= UInt<2>("h01") + T_174551[1] <= UInt<2>("h02") wire T_174554 : UInt<2>[2] - T_174554[0] := UInt<2>("h01") - T_174554[1] := UInt<2>("h02") + T_174554[0] <= UInt<2>("h01") + T_174554[1] <= UInt<2>("h02") wire T_174556 : UInt<2>[1] - T_174556[0] := UInt<2>("h02") + T_174556[0] <= UInt<2>("h02") wire T_174604 : UInt<2>[2] - T_174604[0] := UInt<2>("h01") - T_174604[1] := UInt<2>("h02") + T_174604[0] <= UInt<2>("h01") + T_174604[1] <= UInt<2>("h02") wire T_174607 : UInt<2>[2] - T_174607[0] := UInt<2>("h01") - T_174607[1] := UInt<2>("h02") + T_174607[0] <= UInt<2>("h01") + T_174607[1] <= UInt<2>("h02") wire T_174609 : UInt<2>[1] - T_174609[0] := UInt<2>("h02") + T_174609[0] <= UInt<2>("h02") wire T_174654 : UInt<2>[2] - T_174654[0] := UInt<2>("h01") - T_174654[1] := UInt<2>("h02") + T_174654[0] <= UInt<2>("h01") + T_174654[1] <= UInt<2>("h02") wire T_174657 : UInt<2>[2] - T_174657[0] := UInt<2>("h01") - T_174657[1] := UInt<2>("h02") + T_174657[0] <= UInt<2>("h01") + T_174657[1] <= UInt<2>("h02") wire T_174659 : UInt<2>[1] - T_174659[0] := UInt<2>("h02") + T_174659[0] <= UInt<2>("h02") wire T_174707 : UInt<2>[2] - T_174707[0] := UInt<2>("h01") - T_174707[1] := UInt<2>("h02") + T_174707[0] <= UInt<2>("h01") + T_174707[1] <= UInt<2>("h02") wire T_174710 : UInt<2>[2] - T_174710[0] := UInt<2>("h01") - T_174710[1] := UInt<2>("h02") + T_174710[0] <= UInt<2>("h01") + T_174710[1] <= UInt<2>("h02") wire T_174712 : UInt<2>[1] - T_174712[0] := UInt<2>("h02") + T_174712[0] <= UInt<2>("h02") wire T_174757 : UInt<2>[2] - T_174757[0] := UInt<2>("h01") - T_174757[1] := UInt<2>("h02") + T_174757[0] <= UInt<2>("h01") + T_174757[1] <= UInt<2>("h02") wire T_174760 : UInt<2>[2] - T_174760[0] := UInt<2>("h01") - T_174760[1] := UInt<2>("h02") + T_174760[0] <= UInt<2>("h01") + T_174760[1] <= UInt<2>("h02") wire T_174762 : UInt<2>[1] - T_174762[0] := UInt<2>("h02") + T_174762[0] <= UInt<2>("h02") wire T_174807 : UInt<2>[2] - T_174807[0] := UInt<2>("h01") - T_174807[1] := UInt<2>("h02") + T_174807[0] <= UInt<2>("h01") + T_174807[1] <= UInt<2>("h02") wire T_174810 : UInt<2>[2] - T_174810[0] := UInt<2>("h01") - T_174810[1] := UInt<2>("h02") + T_174810[0] <= UInt<2>("h01") + T_174810[1] <= UInt<2>("h02") wire T_174812 : UInt<2>[1] - T_174812[0] := UInt<2>("h02") + T_174812[0] <= UInt<2>("h02") wire T_174856 : UInt<2>[2] - T_174856[0] := UInt<2>("h01") - T_174856[1] := UInt<2>("h02") + T_174856[0] <= UInt<2>("h01") + T_174856[1] <= UInt<2>("h02") wire T_174859 : UInt<2>[2] - T_174859[0] := UInt<2>("h01") - T_174859[1] := UInt<2>("h02") + T_174859[0] <= UInt<2>("h01") + T_174859[1] <= UInt<2>("h02") wire T_174861 : UInt<2>[1] - T_174861[0] := UInt<2>("h02") + T_174861[0] <= UInt<2>("h02") wire T_174902 : UInt<2>[2] - T_174902[0] := UInt<2>("h01") - T_174902[1] := UInt<2>("h02") + T_174902[0] <= UInt<2>("h01") + T_174902[1] <= UInt<2>("h02") wire T_174905 : UInt<2>[2] - T_174905[0] := UInt<2>("h01") - T_174905[1] := UInt<2>("h02") + T_174905[0] <= UInt<2>("h01") + T_174905[1] <= UInt<2>("h02") wire T_174907 : UInt<2>[1] - T_174907[0] := UInt<2>("h02") + T_174907[0] <= UInt<2>("h02") wire T_174951 : UInt<2>[2] - T_174951[0] := UInt<2>("h01") - T_174951[1] := UInt<2>("h02") + T_174951[0] <= UInt<2>("h01") + T_174951[1] <= UInt<2>("h02") wire T_174954 : UInt<2>[2] - T_174954[0] := UInt<2>("h01") - T_174954[1] := UInt<2>("h02") + T_174954[0] <= UInt<2>("h01") + T_174954[1] <= UInt<2>("h02") wire T_174956 : UInt<2>[1] - T_174956[0] := UInt<2>("h02") + T_174956[0] <= UInt<2>("h02") wire T_174997 : UInt<2>[2] - T_174997[0] := UInt<2>("h01") - T_174997[1] := UInt<2>("h02") + T_174997[0] <= UInt<2>("h01") + T_174997[1] <= UInt<2>("h02") wire T_175000 : UInt<2>[2] - T_175000[0] := UInt<2>("h01") - T_175000[1] := UInt<2>("h02") + T_175000[0] <= UInt<2>("h01") + T_175000[1] <= UInt<2>("h02") wire T_175002 : UInt<2>[1] - T_175002[0] := UInt<2>("h02") + T_175002[0] <= UInt<2>("h02") wire T_175043 : UInt<2>[2] - T_175043[0] := UInt<2>("h01") - T_175043[1] := UInt<2>("h02") + T_175043[0] <= UInt<2>("h01") + T_175043[1] <= UInt<2>("h02") wire T_175046 : UInt<2>[2] - T_175046[0] := UInt<2>("h01") - T_175046[1] := UInt<2>("h02") + T_175046[0] <= UInt<2>("h01") + T_175046[1] <= UInt<2>("h02") wire T_175048 : UInt<2>[1] - T_175048[0] := UInt<2>("h02") + T_175048[0] <= UInt<2>("h02") wire T_175096 : UInt<2>[2] - T_175096[0] := UInt<2>("h01") - T_175096[1] := UInt<2>("h02") + T_175096[0] <= UInt<2>("h01") + T_175096[1] <= UInt<2>("h02") wire T_175099 : UInt<2>[2] - T_175099[0] := UInt<2>("h01") - T_175099[1] := UInt<2>("h02") + T_175099[0] <= UInt<2>("h01") + T_175099[1] <= UInt<2>("h02") wire T_175101 : UInt<2>[1] - T_175101[0] := UInt<2>("h02") + T_175101[0] <= UInt<2>("h02") wire T_175146 : UInt<2>[2] - T_175146[0] := UInt<2>("h01") - T_175146[1] := UInt<2>("h02") + T_175146[0] <= UInt<2>("h01") + T_175146[1] <= UInt<2>("h02") wire T_175149 : UInt<2>[2] - T_175149[0] := UInt<2>("h01") - T_175149[1] := UInt<2>("h02") + T_175149[0] <= UInt<2>("h01") + T_175149[1] <= UInt<2>("h02") wire T_175151 : UInt<2>[1] - T_175151[0] := UInt<2>("h02") - out.acquire <> in.acquire - out.grant <> in.grant - out.probe.ready := UInt<1>("h01") - out.release.valid := UInt<1>("h00") + T_175151[0] <= UInt<2>("h02") + out.acquire <- in.acquire + out.grant <- in.grant + out.probe.ready <= UInt<1>("h01") + out.release.valid <= UInt<1>("h00") diff --git a/test/errors/high-form/InvalidLOC.fir b/test/errors/high-form/InvalidLOC.fir index a0a3cea9..8329cc02 100644 --- a/test/errors/high-form/InvalidLOC.fir +++ b/test/errors/high-form/InvalidLOC.fir @@ -6,7 +6,7 @@ circuit Top : module Top : wire x : UInt - add(x,x) := UInt(1) - UInt(1) := UInt(1) - SInt(1) := UInt(1) + add(x,x) <= UInt(1) + UInt(1) <= UInt(1) + SInt(1) <= UInt(1) diff --git a/test/errors/high-form/InvalidSubexp.fir b/test/errors/high-form/InvalidSubexp.fir index 07f529d2..23c155e2 100644 --- a/test/errors/high-form/InvalidSubexp.fir +++ b/test/errors/high-form/InvalidSubexp.fir @@ -5,5 +5,5 @@ circuit Top : module Top : wire x : UInt<4> - add(x,x)[10] := UInt(1) - add(x,x).x := UInt(1) + add(x,x)[10] <= UInt(1) + add(x,x).x <= UInt(1) diff --git a/test/errors/high-form/NegUInt.fir b/test/errors/high-form/NegUInt.fir index 35f25013..8249f791 100644 --- a/test/errors/high-form/NegUInt.fir +++ b/test/errors/high-form/NegUInt.fir @@ -4,4 +4,4 @@ circuit Top : module Top : wire x : UInt<4> - x := UInt(-2) + x <= UInt(-2) diff --git a/test/errors/high-form/RemoveChar.fir b/test/errors/high-form/RemoveChar.fir index 74c4a092..9341468c 100644 --- a/test/errors/high-form/RemoveChar.fir +++ b/test/errors/high-form/RemoveChar.fir @@ -4,9 +4,9 @@ circuit Top : module Top : wire x_1 : UInt<1> - x_1 := UInt(1) + x_1 <= UInt(1) wire x : UInt<1> - x := addw(addw(UInt(1),UInt(1)),UInt(1)) + x <= addw(addw(UInt(1),UInt(1)),UInt(1)) diff --git a/test/errors/high-form/RemoveScope.fir b/test/errors/high-form/RemoveScope.fir index 16498fd8..63dfb4de 100644 --- a/test/errors/high-form/RemoveScope.fir +++ b/test/errors/high-form/RemoveScope.fir @@ -8,11 +8,11 @@ circuit Top : node p = UInt(1) when p : wire x : UInt<1> - x := UInt(1) + x <= UInt(1) node y = add(x,UInt(1)) else : wire x : UInt<1> - x := UInt(1) + x <= UInt(1) node z = add(x,UInt(1)) - x := UInt(1) + x <= UInt(1) node w = add(x,UInt(1)) diff --git a/test/errors/high-form/SpecialChars.fir b/test/errors/high-form/SpecialChars.fir index 99df9143..85911c06 100644 --- a/test/errors/high-form/SpecialChars.fir +++ b/test/errors/high-form/SpecialChars.fir @@ -4,32 +4,32 @@ circuit Top : module Top : wire x : UInt<1> - x := UInt(1) + x <= UInt(1) wire x~y : UInt<2> - x~y := UInt(1) + x~y <= UInt(1) wire x!y : UInt<2> - x!y := UInt(1) + x!y <= UInt(1) wire x@y : UInt<2> - x@y := UInt(1) + x@y <= UInt(1) wire x#y : UInt<2> - x#y := UInt(1) + x#y <= UInt(1) wire x%y : UInt<2> - x%y := UInt(1) + x%y <= UInt(1) wire x^y : UInt<2> - x^y := UInt(1) + x^y <= UInt(1) wire x*y : UInt<2> - x*y := UInt(1) + x*y <= UInt(1) wire x-y : UInt<2> - x-y := UInt(1) + x-y <= UInt(1) wire x_y : UInt<2> - x_y := UInt(1) + x_y <= UInt(1) wire x+y : UInt<2> - x+y := UInt(1) + x+y <= UInt(1) wire x=y : UInt<2> - x=y := UInt(1) + x=y <= UInt(1) wire x?y : UInt<2> - x?y := UInt(1) + x?y <= UInt(1) wire x/y : UInt<2> - x/y := UInt(1) + x/y <= UInt(1) diff --git a/test/errors/init/Output.fir b/test/errors/init/Output.fir index f28d1e0b..0b7a7f80 100644 --- a/test/errors/init/Output.fir +++ b/test/errors/init/Output.fir @@ -7,4 +7,4 @@ circuit Top : wire y : UInt<1> when UInt(0) : - y := UInt(1) + y <= UInt(1) diff --git a/test/errors/type/BulkConnect.fir b/test/errors/type/BulkConnect.fir index 4e02402c..26f5c156 100644 --- a/test/errors/type/BulkConnect.fir +++ b/test/errors/type/BulkConnect.fir @@ -7,26 +7,26 @@ circuit Top : module Top : wire a : { w : UInt<42>} wire b : { w : SInt<42>} - a <> b + a <- b wire c : { w : UInt<10>} wire d : { flip w : UInt<12> } - c <> d + c <- d wire e : { w : UInt<10>} wire f : { x : UInt<12> } - e <> f + e <- f wire g : { w : { y : UInt<10> }} wire h : { w : { x : UInt<12> }} - g <> h + g <- h wire i : { w : { flip y : UInt<10> }} wire j : { w : { y : UInt<12> }} - i <> j + i <- j wire k : { w : { y : SInt<10> }} wire l : { w : { y : UInt<12> }} - k <> l + k <- l diff --git a/test/errors/width/NegWidth.fir b/test/errors/width/NegWidth.fir index 5d5bbf43..e02884a8 100644 --- a/test/errors/width/NegWidth.fir +++ b/test/errors/width/NegWidth.fir @@ -6,4 +6,4 @@ circuit Top : output y : UInt wire x : UInt<2> - y := shr(x,4) + y <= shr(x,4) diff --git a/test/errors/width/SmallWidth.fir b/test/errors/width/SmallWidth.fir index 0ee60ec0..0885ba52 100644 --- a/test/errors/width/SmallWidth.fir +++ b/test/errors/width/SmallWidth.fir @@ -5,7 +5,7 @@ circuit Top : module Top : output z : UInt - z := add(UInt<4>("h121"),UInt<3>("h13333")) + z <= add(UInt<4>("h121"),UInt<3>("h13333")) diff --git a/test/features/BigInt.fir b/test/features/BigInt.fir index 225f1d8b..a8dadcfc 100644 --- a/test/features/BigInt.fir +++ b/test/features/BigInt.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.v -X verilog -p cT 2>&1 | tee %s.out | FileCheck %s circuit Top : module Top : node x = UInt("h2") diff --git a/test/features/BulkConnect.fir b/test/features/BulkConnect.fir index f08d6dc7..a57ce199 100644 --- a/test/features/BulkConnect.fir +++ b/test/features/BulkConnect.fir @@ -1,39 +1,39 @@ ; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: Lower To Ground +;CHECK: Expand Connects circuit Top : module Top : wire a : { w : UInt<42>} - a.w := UInt(1) + a.w <= UInt(1) wire b : { w : UInt<42>, x : UInt<20>} - b.w := UInt(1) - b.x := UInt(1) - a <> b - ; CHECK: a$w := b$w - ; CHECK-NOT: a$x := b$x - ; CHECK-NOT: a$y := b$y - ; CHECK-NOT: b$y := a$y - ; CHECK-NOT: a$z := b$z + b.w <= UInt(1) + b.x <= UInt(1) + a <- b + ; CHECK: a.w <= b.w + ; CHECK-NOT: a.x <= b.x + ; CHECK-NOT: a.y <= b.y + ; CHECK-NOT: b.y <= a.y + ; CHECK-NOT: a.z <= b.z wire c : { x : { y : UInt<1>, z : UInt<1>}}[4] - c[0].x.z := UInt(1) - c[1].x.z := UInt(1) - c[2].x.y := UInt(1) - c[2].x.z := UInt(1) - c[3].x.y := UInt(1) - c[3].x.z := UInt(1) + c[0].x.z <= UInt(1) + c[1].x.z <= UInt(1) + c[2].x.y <= UInt(1) + c[2].x.z <= UInt(1) + c[3].x.y <= UInt(1) + c[3].x.z <= UInt(1) wire d : { x : { y : UInt<1>}}[2] - d[0].x.y := UInt(1) - d[1].x.y := UInt(1) - c <> d - ; CHECK: c$0$x$y := d$0$x$y - ; CHECK: c$1$x$y := d$1$x$y - ; CHECK-NOT: c$2$x$y := d$2$x$y - ; CHECK-NOT: c$3$x$y := d$3$x$y - ; CHECK-NOT: c$0$x$z := d$0$x$z - ; CHECK-NOT: c$1$x$z := d$1$x$z - ; CHECK-NOT: c$2$x$z := d$2$x$z - ; CHECK-NOT: c$3$x$z := d$3$x$z + d[0].x.y <= UInt(1) + d[1].x.y <= UInt(1) + c <- d + ; CHECK: c[0].x.y <= d[0].x.y + ; CHECK: c[1].x.y <= d[1].x.y + ; CHECK-NOT: c[2].x.y <= d[2].x.y + ; CHECK-NOT: c[3].x.y <= d[3].x.y + ; CHECK-NOT: c[0].x.z <= d[0].x.z + ; CHECK-NOT: c[1].x.z <= d[1].x.z + ; CHECK-NOT: c[2].x.z <= d[2].x.z + ; CHECK-NOT: c[3].x.z <= d[3].x.z -;CHECK: Finished Lower To Ground +;CHECK: Finished Expand Connects ;CHECK: Done! diff --git a/test/features/CondRead.fir b/test/features/CondRead.fir index a9ae27ca..5dd1d321 100644 --- a/test/features/CondRead.fir +++ b/test/features/CondRead.fir @@ -12,7 +12,7 @@ circuit CondRead : poison xxx : UInt<6> wire data : UInt<20> read accessor readport = mem[mux(pred,index,xxx)] - out := readport + out <= readport ; CHECK: read accessor readport = mem[mux(pred,index,index_0)] diff --git a/test/features/ExModule.fir b/test/features/ExModule.fir index 146d11b9..b31c77c9 100644 --- a/test/features/ExModule.fir +++ b/test/features/ExModule.fir @@ -3,9 +3,9 @@ circuit Top : module Top : output z : UInt<4> inst i of BlackBox - i.x := UInt(1) - i.y := UInt(2) - z := i.z + i.x <= UInt(1) + i.y <= UInt(2) + z <= i.z extmodule BlackBox : input x : UInt<4> input y : UInt<4> diff --git a/test/features/InitAccessor.fir b/test/features/InitAccessor.fir index 0bf861f2..356b5a68 100644 --- a/test/features/InitAccessor.fir +++ b/test/features/InitAccessor.fir @@ -5,10 +5,10 @@ circuit Top : module Top : input in : UInt<1> wire b : UInt<1>[3] - b.0 := UInt(1) - b.1 := UInt(1) - b.2 := UInt(1) + b.0 <= UInt(1) + b.1 <= UInt(1) + b.2 <= UInt(1) node c = UInt(1) infer accessor a = b[c] when in : - a := UInt(1) + a <= UInt(1) diff --git a/test/features/InitializeVec.fir b/test/features/InitializeVec.fir index 0aa28835..ef6400a0 100644 --- a/test/features/InitializeVec.fir +++ b/test/features/InitializeVec.fir @@ -6,17 +6,17 @@ circuit Tst : input in : {valid : UInt<1>, flip ready : UInt<1>, bits : UInt<8>} output outs : {valid : UInt<1>, flip ready : UInt<1>, bits : UInt<8>}[4] - in.ready := UInt<1>(1) - outs[0].valid := UInt<1>(0) - outs[0].bits := UInt<1>(0) - outs[1].valid := UInt<1>(0) - outs[1].bits := UInt<1>(0) - outs[2].valid := UInt<1>(0) - outs[2].bits := UInt<1>(0) - outs[3].valid := UInt<1>(0) - outs[3].bits := UInt<1>(0) - in.ready := UInt<1>(1) + in.ready <= UInt<1>(1) + outs[0].valid <= UInt<1>(0) + outs[0].bits <= UInt<1>(0) + outs[1].valid <= UInt<1>(0) + outs[1].bits <= UInt<1>(0) + outs[2].valid <= UInt<1>(0) + outs[2].bits <= UInt<1>(0) + outs[3].valid <= UInt<1>(0) + outs[3].bits <= UInt<1>(0) + in.ready <= UInt<1>(1) infer accessor out = outs[in.bits] when out.ready : - out.bits := UInt<7>(99) - out.valid := UInt<1>(1) + out.bits <= UInt<7>(99) + out.valid <= UInt<1>(1) diff --git a/test/features/Link.fir b/test/features/Link.fir index 040ac2c5..57fb8605 100644 --- a/test/features/Link.fir +++ b/test/features/Link.fir @@ -1,5 +1,5 @@ ; RUN: firrtl -i %s -m %S/Queue.fir -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: Lower To Ground +;CHECK: Done! circuit Top : module Top : input clk : Clock @@ -7,8 +7,8 @@ circuit Top : output out : UInt<10> inst q of Queue - q.clk := clk - q.reset := reset - q.in := UInt(1) - out := q.out + q.clk <= clk + q.reset <= reset + q.in <= UInt(1) + out <= q.out diff --git a/test/features/Long.fir b/test/features/Long.fir index b191ac55..7ac5ad6c 100644 --- a/test/features/Long.fir +++ b/test/features/Long.fir @@ -3,4 +3,4 @@ circuit Top : module Top : wire a : UInt - a := UInt("h4261441663") + a <= UInt("h4261441663") diff --git a/test/features/Poison.fir b/test/features/Poison.fir index d8aa4411..2b47411f 100644 --- a/test/features/Poison.fir +++ b/test/features/Poison.fir @@ -5,14 +5,36 @@ circuit Poison : input clk : Clock input reset : UInt<1> input index : UInt<7> + input wmask : {x:UInt<1>, y:UInt<1>} input p : UInt<1> output out : {x : UInt<10>, y : UInt<10>} - poison q : {x : UInt<10>, y : UInt<10>} - smem m : {x : UInt<10>, y : UInt<10>}[128],clk - infer accessor r = m[index] + mem m : + data-type => {x : UInt<10>, y : UInt<10>} + depth => 128 + read-latency => 1 + write-latency => 2 + reader => r + writer => w + read-writer => rw + m.r.addr <= index + m.r.en <= UInt(1) + m.r.clk <= clk + m.w.addr <= index + m.w.en <= UInt(1) + m.w.mask <= wmask + m.w.clk <= clk + m.w.data <= q + + m.rw.clk <= clk + m.rw.raddr <= index + m.rw.ren <= UInt(1) + m.rw.waddr <= index + m.rw.wen <= UInt(1) + m.rw.wmask <= wmask + m.rw.wdata <= q when p : - out := r + out <= m.r.data else : - out := q + out <= q diff --git a/test/features/Printf.fir b/test/features/Printf.fir index 2f8dc985..4e8682ff 100644 --- a/test/features/Printf.fir +++ b/test/features/Printf.fir @@ -1,20 +1,21 @@ ; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: Lower To Ground +;CHECK: Expand Whens circuit Top : module Top : input x : {y : UInt<1>} input p : UInt<1> input clk : Clock - printf(clk,"Hello World!\n") - printf(clk,"Hello World! %x\n", x.y) + input en : UInt<1> + printf(clk,en,"Hello World!\n") + printf(clk,en,"Hello World! %x\n", x.y) when p : - printf(clk,"In consequence\n") + printf(clk,en,"In consequence\n") else : - printf(clk,"In alternate\n") + printf(clk,en,"In alternate\n") -;CHECK: printf(clk, "Hello World!\n") -;CHECK: printf(clk, "Hello World! %x\n", x$y) -;CHECK: when p : printf(clk, "In consequence\n") -;CHECK: when not(p) : printf(clk, "In alternate\n") +;CHECK: printf(clk, en, "Hello World!\n") +;CHECK: printf(clk, en, "Hello World! %x\n", x.y) +;CHECK: printf(clk, and(p, en), "In consequence\n") +;CHECK: printf(clk, and(eqv(p, UInt("h0")), en), "In alternate\n") ;CHECK: Done! diff --git a/test/features/Queue.fir b/test/features/Queue.fir index 07132d94..9b19caf4 100644 --- a/test/features/Queue.fir +++ b/test/features/Queue.fir @@ -7,6 +7,6 @@ circuit Queue : input clk : Clock input reset : UInt<1> - reg r : UInt<10>,clk,reset - r := in - out := r + reg r : UInt<10>,clk,reset,in + r <= in + out <= r diff --git a/test/features/SeqMem.fir b/test/features/SeqMem.fir index 9690f2d1..354bd8de 100644 --- a/test/features/SeqMem.fir +++ b/test/features/SeqMem.fir @@ -4,21 +4,21 @@ circuit Top : module Top : input clk : Clock wire i : UInt<5> - i := UInt(1) + i <= UInt(1) wire i0 : UInt<5> wire j : UInt<128> - i0 := UInt(10) + i0 <= UInt(10) cmem m-com : UInt<128>[32], clk infer accessor r-com = m-com[i] infer accessor w-com = m-com[i] - j := r-com - w-com := j + j <= r-com + w-com <= j smem m-seq : UInt<128>[32], clk infer accessor r-seq = m-seq[i] infer accessor w-seq = m-seq[i] - j := r-seq - w-seq := j + j <= r-seq + w-seq <= j diff --git a/test/features/TwoClocks.fir b/test/features/TwoClocks.fir index 9665c153..f68a2769 100644 --- a/test/features/TwoClocks.fir +++ b/test/features/TwoClocks.fir @@ -8,14 +8,14 @@ circuit Top : reg src : UInt<10>, clk1, reset1 reg sink : UInt<10>, clk2, reset2 - onreset src := UInt(0) - src := addw(src,UInt(1)) + onreset src <= UInt(0) + src <= addw(src,UInt(1)) reg sync_A : UInt<10>, clk2, reset2 - sync_A := src + sync_A <= src reg sync_B : UInt<10>, clk2, reset2 - sync_B := sync_A + sync_B <= sync_A - sink := sync_B + sink <= sync_B ;CHECK: Done! diff --git a/test/passes/const-prop/bits.fir b/test/passes/const-prop/bits.fir index 16d678b3..78c450a9 100644 --- a/test/passes/const-prop/bits.fir +++ b/test/passes/const-prop/bits.fir @@ -8,4 +8,4 @@ circuit top : module top : output out : UInt node x = bits(UInt(127),2,0) - out := x + out <= x diff --git a/test/passes/const-prop/rsh.fir b/test/passes/const-prop/rsh.fir index 8c13e410..4159899f 100644 --- a/test/passes/const-prop/rsh.fir +++ b/test/passes/const-prop/rsh.fir @@ -1,14 +1,14 @@ ; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s ;CHECK: Constant Propagation -;CHECK: x := UInt("h1f") -;CHECK: y := SInt("h20") +;CHECK: x <= UInt("h1f") +;CHECK: y <= SInt("h20") ;CHECK: Finished Constant Propagation circuit top : module top : output x : UInt output y : SInt - x := shr(UInt(127),2) - y := shr(SInt(-128),2) + x <= shr(UInt(127),2) + y <= shr(SInt(-128),2) diff --git a/test/passes/expand-accessors/accessor-mem.fir b/test/passes/expand-accessors/accessor-mem.fir index 6f8b63e3..6f64f57d 100644 --- a/test/passes/expand-accessors/accessor-mem.fir +++ b/test/passes/expand-accessors/accessor-mem.fir @@ -6,19 +6,19 @@ circuit top : input clk : Clock cmem m : UInt<32>[2][2][2], clk wire i : UInt<4> - i := UInt(1) + i <= UInt(1) infer accessor a = m[i] ;CHECK: read accessor a = m[i] infer accessor b = a[i] ;CHECK: indexer b = (a[0] a[1])[i] : UInt<32>[2] infer accessor c = b[i] ;CHECK: indexer c = (b[0] b[1])[i] : UInt<32> wire j : UInt<32> - j := c + j <= c infer accessor x = m[i] ;CHECK: write accessor x = m[i] infer accessor y = x[i] ;CHECK: indexer (x[0] x[1])[i] = y : UInt<32>[2] - y[0] := UInt(1) - y[1] := UInt(1) + y[0] <= UInt(1) + y[1] <= UInt(1) infer accessor z = y[i] ;CHECK: indexer (y[0] y[1])[i] = z : UInt<32> - z := j + z <= j ; CHECK: Finished Expand Accessors ; CHECK: Done! diff --git a/test/passes/expand-accessors/accessor-vec.fir b/test/passes/expand-accessors/accessor-vec.fir index 96a5c74c..1d1bbec9 100644 --- a/test/passes/expand-accessors/accessor-vec.fir +++ b/test/passes/expand-accessors/accessor-vec.fir @@ -4,44 +4,44 @@ circuit top : module top : wire m : UInt<32>[2][2][2] - m[0][0][0] := UInt(1) - m[1][0][0] := UInt(1) - m[0][1][0] := UInt(1) - m[1][1][0] := UInt(1) - m[0][0][1] := UInt(1) - m[1][0][1] := UInt(1) - m[0][1][1] := UInt(1) - m[1][1][1] := UInt(1) + m[0][0][0] <= UInt(1) + m[1][0][0] <= UInt(1) + m[0][1][0] <= UInt(1) + m[1][1][0] <= UInt(1) + m[0][0][1] <= UInt(1) + m[1][0][1] <= UInt(1) + m[0][1][1] <= UInt(1) + m[1][1][1] <= UInt(1) wire i : UInt - i := UInt(1) + i <= UInt(1) infer accessor a = m[i] ;CHECK: indexer a = (m[0] m[1])[i] : UInt<32>[2][2] infer accessor b = a[i] ;CHECK: indexer b = (a[0] a[1])[i] : UInt<32>[2] infer accessor c = b[i] ;CHECK: indexer c = (b[0] b[1])[i] : UInt<32> wire j : UInt - j := c + j <= c infer accessor x = m[i] ;CHECK: indexer (m[0] m[1])[i] = x : UInt<32>[2][2] - x[0][0] := UInt(1) - x[1][0] := UInt(1) - x[0][1] := UInt(1) - x[1][1] := UInt(1) + x[0][0] <= UInt(1) + x[1][0] <= UInt(1) + x[0][1] <= UInt(1) + x[1][1] <= UInt(1) infer accessor y = x[i] ;CHECK: indexer (x[0] x[1])[i] = y : UInt<32>[2] infer accessor z = y[i] ;CHECK: indexer (y[0] y[1])[i] = z : UInt<32> - y[0] := UInt(1) - y[1] := UInt(1) - z := j + y[0] <= UInt(1) + y[1] <= UInt(1) + z <= j wire p : {n : UInt<32>[2]} - p.n[0] := UInt(1) - p.n[1] := UInt(1) + p.n[0] <= UInt(1) + p.n[1] <= UInt(1) infer accessor q = p.n[i] ;CHECK: indexer (p.n[0] p.n[1])[i] = q : UInt<32> - q := j + q <= j wire r : {m : UInt<32>}[2] - r[0].m := UInt(1) - r[1].m := UInt(1) + r[0].m <= UInt(1) + r[1].m <= UInt(1) infer accessor s = r[i] ;CHECK: indexer s = (r[0] r[1])[i] : { m : UInt<32>} - j := s.m + j <= s.m ; CHECK: Finished Expand Accessors ; CHECK: Done! diff --git a/test/passes/expand-accessors/simple.fir b/test/passes/expand-accessors/simple.fir index 7f5a4eb8..7e8a4dcd 100644 --- a/test/passes/expand-accessors/simple.fir +++ b/test/passes/expand-accessors/simple.fir @@ -6,10 +6,10 @@ circuit top : output o : UInt wire m : UInt<32>[2] wire i : UInt - m[0] := UInt("h1") - m[1] := UInt("h1") - i := UInt("h1") + m[0] <= UInt("h1") + m[1] <= UInt("h1") + i <= UInt("h1") infer accessor a = m[i] ;CHECK: indexer a = (m$0 m$1)[i] : UInt<32> - o := a + o <= a diff --git a/test/passes/expand-accessors/simple2.fir b/test/passes/expand-accessors/simple2.fir index 54f8a507..550d34b8 100644 --- a/test/passes/expand-accessors/simple2.fir +++ b/test/passes/expand-accessors/simple2.fir @@ -7,11 +7,11 @@ circuit top : output o2 : UInt wire m : UInt<32>[2] wire i : UInt - m[0] := UInt("h1") - m[1] := UInt("h1") - i := UInt("h1") + m[0] <= UInt("h1") + m[1] <= UInt("h1") + i <= UInt("h1") infer accessor a = m[i] ;CHECK: indexer a = (m$0 m$1)[i] : UInt<32> - o1 := a - o2 := a + o1 <= a + o2 <= a diff --git a/test/passes/expand-whens/bundle-init.fir b/test/passes/expand-whens/bundle-init.fir index 892b419a..f34dbe1a 100644 --- a/test/passes/expand-whens/bundle-init.fir +++ b/test/passes/expand-whens/bundle-init.fir @@ -8,20 +8,20 @@ circuit top : wire a : UInt wire b : UInt wire w : { x : UInt, y : UInt} - a := UInt(1) - b := UInt(2) + a <= UInt(1) + b <= UInt(2) - w.x := b - w.y := a - r.x := a - r.y := b - onreset r := w + w.x <= b + w.y <= a + r.x <= a + r.y <= b + onreset r <= w -; CHECK: r$x := mux(reset, w$x, a) -; CHECK: r$y := mux(reset, w$y, b) -; CHECK: a := UInt("h1") -; CHECK: b := UInt("h2") -; CHECK: w$x := b -; CHECK: w$y := a +; CHECK: r$x <= mux(reset, w$x, a) +; CHECK: r$y <= mux(reset, w$y, b) +; CHECK: a <= UInt("h1") +; CHECK: b <= UInt("h2") +; CHECK: w$x <= b +; CHECK: w$y <= a ; CHECK: Finished Expand Whens diff --git a/test/passes/expand-whens/nested-whens.fir b/test/passes/expand-whens/nested-whens.fir index f5f33af6..0a45dac1 100644 --- a/test/passes/expand-whens/nested-whens.fir +++ b/test/passes/expand-whens/nested-whens.fir @@ -13,22 +13,22 @@ circuit top : wire y : UInt wire z : UInt wire w : UInt - p := UInt(1) - q := UInt(1) - a := UInt(1) - b := UInt(1) - x := UInt(1) - y := UInt(1) - z := UInt(1) - w := UInt(1) + p <= UInt(1) + q <= UInt(1) + a <= UInt(1) + b <= UInt(1) + x <= UInt(1) + y <= UInt(1) + z <= UInt(1) + w <= UInt(1) - onreset r := w + onreset r <= w when p : - onreset r := x - r := a + onreset r <= x + r <= a when q : - onreset r := y - r := b - r := z -; CHECK: r := mux(reset, mux(q, y, mux(p, x, w)), z) + onreset r <= y + r <= b + r <= z +; CHECK: r <= mux(reset, mux(q, y, mux(p, x, w)), z) ; CHECK: Finished Expand Whens diff --git a/test/passes/expand-whens/one-when.fir b/test/passes/expand-whens/one-when.fir index 35fb18be..53616b0e 100644 --- a/test/passes/expand-whens/one-when.fir +++ b/test/passes/expand-whens/one-when.fir @@ -9,28 +9,28 @@ circuit top : wire i : UInt<1> wire p : UInt<1> wire j : UInt<1> - j := UInt(1) + j <= UInt(1) reg r : UInt<1>, clk, reset - p := j + p <= j when p : - onreset r := i + onreset r <= i infer accessor a = m[i] - i := a + i <= a infer accessor b = m[i] - b := i + b <= i else : infer accessor c = m[i] - i := c + i <= c infer accessor d = m[i] - d := i + d <= i infer accessor e = m[i] when p : - p := i + p <= i when e : - p := p - onreset r := p - r := p + p <= p + onreset r <= p + r <= p ; CHECK: Finished Expand Whens diff --git a/test/passes/expand-whens/partial-init.fir b/test/passes/expand-whens/partial-init.fir index 3b5a9f0f..f2b9c2e1 100644 --- a/test/passes/expand-whens/partial-init.fir +++ b/test/passes/expand-whens/partial-init.fir @@ -6,16 +6,16 @@ circuit top : input clk : Clock input reset : UInt<1> reg r : UInt<1>[10],clk,reset - r[0] := UInt(1) - r[1] := UInt(1) - r[2] := UInt(1) - r[3] := UInt(1) - r[4] := UInt(1) - r[5] := UInt(1) - r[6] := UInt(1) - r[7] := UInt(1) - r[8] := UInt(1) - r[9] := UInt(1) - onreset r[3] := UInt(0) + r[0] <= UInt(1) + r[1] <= UInt(1) + r[2] <= UInt(1) + r[3] <= UInt(1) + r[4] <= UInt(1) + r[5] <= UInt(1) + r[6] <= UInt(1) + r[7] <= UInt(1) + r[8] <= UInt(1) + r[9] <= UInt(1) + onreset r[3] <= UInt(0) ; CHECK: Finished Expand Whens diff --git a/test/passes/expand-whens/reg-and-when.fir b/test/passes/expand-whens/reg-and-when.fir index ac678b6d..97b96735 100644 --- a/test/passes/expand-whens/reg-and-when.fir +++ b/test/passes/expand-whens/reg-and-when.fir @@ -12,35 +12,35 @@ circuit Top : input set_divisor : {valid : UInt<1>, bits : UInt<32>} output divisor : UInt<32> - out_fast.ready := UInt<1>("h00") - out_slow.bits := UInt<1>("h00") - out_slow.valid := UInt<1>("h00") - in_fast.bits := UInt<1>("h00") - in_fast.valid := UInt<1>("h00") - in_slow.ready := UInt<1>("h00") - clk_slow := UInt<1>("h00") - divisor := UInt<1>("h00") + out_fast.ready <= UInt<1>("h00") + out_slow.bits <= UInt<1>("h00") + out_slow.valid <= UInt<1>("h00") + in_fast.bits <= UInt<1>("h00") + in_fast.valid <= UInt<1>("h00") + in_slow.ready <= UInt<1>("h00") + clk_slow <= UInt<1>("h00") + divisor <= UInt<1>("h00") inst fromhost_q of Queue_50 - fromhost_q.reset := UInt<1>("h00") - fromhost_q.enq.bits := UInt<1>("h00") - fromhost_q.enq.valid := UInt<1>("h00") - fromhost_q.deq.ready := UInt<1>("h00") - fromhost_q.clock := clock - fromhost_q.reset := reset + fromhost_q.reset <= UInt<1>("h00") + fromhost_q.enq.bits <= UInt<1>("h00") + fromhost_q.enq.valid <= UInt<1>("h00") + fromhost_q.deq.ready <= UInt<1>("h00") + fromhost_q.clock <= clock + fromhost_q.reset <= reset inst tohost_q of Queue_51 - tohost_q.reset := UInt<1>("h00") - tohost_q.enq.bits := UInt<1>("h00") - tohost_q.enq.valid := UInt<1>("h00") - tohost_q.deq.ready := UInt<1>("h00") - tohost_q.clock := clock - tohost_q.reset := reset + tohost_q.reset <= UInt<1>("h00") + tohost_q.enq.bits <= UInt<1>("h00") + tohost_q.enq.valid <= UInt<1>("h00") + tohost_q.deq.ready <= UInt<1>("h00") + tohost_q.clock <= clock + tohost_q.reset <= reset reg out_slow_bits : UInt<17>, clock, reset - out_slow_bits := tohost_q.deq.bits + out_slow_bits <= tohost_q.deq.bits when fromhost_q.deq.valid : - out_slow_bits := fromhost_q.deq.bits + out_slow_bits <= fromhost_q.deq.bits module Queue_50 : input clock : Clock @@ -49,14 +49,14 @@ circuit Top : output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>} output count : UInt<1> - enq.ready := UInt<1>("h00") - deq.bits := UInt<1>("h00") - deq.valid := UInt<1>("h00") - count := UInt<1>("h00") + enq.ready <= UInt<1>("h00") + deq.bits <= UInt<1>("h00") + deq.valid <= UInt<1>("h00") + count <= UInt<1>("h00") cmem ram : UInt<17>[1], clock reg maybe_full : UInt<1>, clock, reset - onreset maybe_full := UInt<1>("h00") + onreset maybe_full <= UInt<1>("h00") node ptr_match = eq(UInt<1>("h00"), UInt<1>("h00")) node T_115167 = eq(maybe_full, UInt<1>("h00")) node empty = and(ptr_match, T_115167) @@ -71,34 +71,34 @@ circuit Top : node do_deq = and(T_115177, T_115179) when do_enq : infer accessor T_115181 = ram[UInt<1>("h00")] - T_115181 := enq.bits + T_115181 <= enq.bits skip when do_deq : skip node T_115184 = neq(do_enq, do_deq) when T_115184 : - maybe_full := do_enq + maybe_full <= do_enq skip node T_115186 = eq(empty, UInt<1>("h00")) node T_115188 = and(UInt<1>("h00"), enq.valid) node T_115189 = or(T_115186, T_115188) - deq.valid := T_115189 + deq.valid <= T_115189 node T_115191 = eq(full, UInt<1>("h00")) node T_115193 = and(UInt<1>("h00"), deq.ready) node T_115194 = or(T_115191, T_115193) - enq.ready := T_115194 + enq.ready <= T_115194 infer accessor T_115195 = ram[UInt<1>("h00")] wire T_115197 : UInt<17> - T_115197 := T_115195 + T_115197 <= T_115195 when maybe_flow : - T_115197 := enq.bits + T_115197 <= enq.bits skip - deq.bits := T_115197 + deq.bits <= T_115197 node ptr_diff = subw(UInt<1>("h00"), UInt<1>("h00")) node T_115199 = and(maybe_full, ptr_match) node T_115200 = T_115199 node T_115201 = cat(T_115200, ptr_diff) - count := T_115201 + count <= T_115201 module Queue_51 : input clock : Clock @@ -107,14 +107,14 @@ circuit Top : output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>} output count : UInt<1> - enq.ready := UInt<1>("h00") - deq.bits := UInt<1>("h00") - deq.valid := UInt<1>("h00") - count := UInt<1>("h00") + enq.ready <= UInt<1>("h00") + deq.bits <= UInt<1>("h00") + deq.valid <= UInt<1>("h00") + count <= UInt<1>("h00") cmem ram : UInt<17>[1], clock reg maybe_full : UInt<1>, clock, reset - onreset maybe_full := UInt<1>("h00") + onreset maybe_full <= UInt<1>("h00") node ptr_match = eq(UInt<1>("h00"), UInt<1>("h00")) node T_115235 = eq(maybe_full, UInt<1>("h00")) node empty = and(ptr_match, T_115235) @@ -129,32 +129,32 @@ circuit Top : node do_deq = and(T_115245, T_115247) when do_enq : infer accessor T_115249 = ram[UInt<1>("h00")] - T_115249 := enq.bits + T_115249 <= enq.bits skip when do_deq : skip node T_115252 = neq(do_enq, do_deq) when T_115252 : - maybe_full := do_enq + maybe_full <= do_enq skip node T_115254 = eq(empty, UInt<1>("h00")) node T_115256 = and(UInt<1>("h00"), enq.valid) node T_115257 = or(T_115254, T_115256) - deq.valid := T_115257 + deq.valid <= T_115257 node T_115259 = eq(full, UInt<1>("h00")) node T_115261 = and(UInt<1>("h00"), deq.ready) node T_115262 = or(T_115259, T_115261) - enq.ready := T_115262 + enq.ready <= T_115262 infer accessor T_115263 = ram[UInt<1>("h00")] wire T_115265 : UInt<17> - T_115265 := T_115263 + T_115265 <= T_115263 when maybe_flow : - T_115265 := enq.bits + T_115265 <= enq.bits skip - deq.bits := T_115265 + deq.bits <= T_115265 node ptr_diff = subw(UInt<1>("h00"), UInt<1>("h00")) node T_115267 = and(maybe_full, ptr_match) node T_115268 = T_115267 node T_115269 = cat(T_115268, ptr_diff) - count := T_115269 + count <= T_115269 diff --git a/test/passes/expand-whens/reg-dwc.fir b/test/passes/expand-whens/reg-dwc.fir index 349c4298..30132723 100644 --- a/test/passes/expand-whens/reg-dwc.fir +++ b/test/passes/expand-whens/reg-dwc.fir @@ -4,10 +4,10 @@ circuit top : input clk : Clock input reset : UInt<1> wire p : UInt - p := UInt(1) + p <= UInt(1) reg r : UInt,clk,reset when p : - r := UInt(2) + r <= UInt(2) ; CHECK: Expand Whens @@ -15,8 +15,8 @@ circuit top : ; CHECK: module top : ; CHECK: wire p : UInt ; CHECK: reg r : UInt -; CHECK: p := UInt("h1") -; CHECK: when p : r := UInt("h2") +; CHECK: p <= UInt("h1") +; CHECK: when p : r <= UInt("h2") ; CHECK: Finished Expand Whens diff --git a/test/passes/expand-whens/reg-dwoc.fir b/test/passes/expand-whens/reg-dwoc.fir index 60bd43a8..002f34a5 100644 --- a/test/passes/expand-whens/reg-dwoc.fir +++ b/test/passes/expand-whens/reg-dwoc.fir @@ -4,11 +4,11 @@ circuit top : input clk : Clock input reset : UInt<1> wire p : UInt - p := UInt(1) + p <= UInt(1) reg r : UInt,clk,reset when p : - onreset r := UInt(1) - r := UInt(2) + onreset r <= UInt(1) + r <= UInt(2) ; CHECK: Expand Whens @@ -16,8 +16,8 @@ circuit top : ; CHECK: module top : ; CHECK: wire p : UInt ; CHECK: reg r : UInt, clk, reset -; CHECK: p := UInt("h1") -; CHECK: when p : r := mux(reset, UInt("h1"), UInt("h2")) +; CHECK: p <= UInt("h1") +; CHECK: when p : r <= mux(reset, UInt("h1"), UInt("h2")) ; CHECK: Finished Expand Whens diff --git a/test/passes/expand-whens/reg-wdc.fir b/test/passes/expand-whens/reg-wdc.fir index c6439860..33cac75e 100644 --- a/test/passes/expand-whens/reg-wdc.fir +++ b/test/passes/expand-whens/reg-wdc.fir @@ -4,10 +4,10 @@ circuit top : input clk : Clock input reset : UInt<1> wire p : UInt - p := UInt(1) + p <= UInt(1) when p : reg r : UInt,clk,reset - r := UInt(2) + r <= UInt(2) ; CHECK: Expand Whens @@ -15,8 +15,8 @@ circuit top : ; CHECK: module top : ; CHECK: wire p : UInt ; CHECK: reg r : UInt, clk, reset -; CHECK: p := UInt("h1") -; CHECK-NOT: when p : r := UInt("h2") +; CHECK: p <= UInt("h1") +; CHECK-NOT: when p : r <= UInt("h2") ; CHECK: Finished Expand Whens diff --git a/test/passes/expand-whens/reg-wdoc.fir b/test/passes/expand-whens/reg-wdoc.fir index de0bbfd6..1d535aca 100644 --- a/test/passes/expand-whens/reg-wdoc.fir +++ b/test/passes/expand-whens/reg-wdoc.fir @@ -4,11 +4,11 @@ circuit top : input clk : Clock input reset : UInt<1> wire p : UInt - p := UInt(1) + p <= UInt(1) when p : reg r : UInt,clk,reset - onreset r := UInt(1) - r := UInt(2) + onreset r <= UInt(1) + r <= UInt(2) ; CHECK: Expand Whens @@ -16,8 +16,8 @@ circuit top : ; CHECK: module top : ; CHECK: wire p : UInt ; CHECK: reg r : UInt, clk, reset -; CHECK: p := UInt("h1") -; CHECK-NOT: when p : r := mux(reset, UInt("h1"), UInt("h2")) +; CHECK: p <= UInt("h1") +; CHECK-NOT: when p : r <= mux(reset, UInt("h1"), UInt("h2")) ; CHECK: Finished Expand Whens diff --git a/test/passes/expand-whens/scoped-reg.fir b/test/passes/expand-whens/scoped-reg.fir index 493d8c41..edce1e1e 100644 --- a/test/passes/expand-whens/scoped-reg.fir +++ b/test/passes/expand-whens/scoped-reg.fir @@ -4,11 +4,11 @@ circuit top : input clk : Clock input reset : UInt<1> wire p : UInt - p := UInt(1) + p <= UInt(1) when p : reg r : UInt, clk, reset - onreset r := UInt(1) - r := UInt(2) + onreset r <= UInt(1) + r <= UInt(2) ; CHECK: Expand Whens @@ -16,6 +16,6 @@ circuit top : ; CHECK: module top : ; CHECK: wire p : UInt ; CHECK: reg r : UInt, clk, reset -; CHECK-NOT: when p : r := mux(reset, UInt("h00000001"), UInt("h00000002")) +; CHECK-NOT: when p : r <= mux(reset, UInt("h00000001"), UInt("h00000002")) ; CHECK: Finished Expand Whens diff --git a/test/passes/expand-whens/two-when.fir b/test/passes/expand-whens/two-when.fir index 939fac09..05179cf5 100644 --- a/test/passes/expand-whens/two-when.fir +++ b/test/passes/expand-whens/two-when.fir @@ -6,34 +6,34 @@ circuit top : input clk : Clock cmem m :{ x : UInt<1>, y : UInt<1> }[2], clk wire i : UInt<1> - i := UInt(1) + i <= UInt(1) wire p : UInt<1> - p := UInt(1) + p <= UInt(1) wire q : { x : UInt<1>, y : UInt<1> } when p : wire p2 : UInt<1> - p2 := UInt(1) + p2 <= UInt(1) when p2 : infer accessor a = m[i] - q := a + q <= a infer accessor b = m[i] - b := q + b <= q else : infer accessor c = m[i] - q := c + q <= c infer accessor d = m[i] - d := q + d <= q else : wire p3 : UInt<1> - p3 := UInt(1) + p3 <= UInt(1) when p3 : infer accessor w = m[i] - q := w + q <= w infer accessor x = m[i] - x := q + x <= q else : infer accessor y = m[i] - q := y + q <= y infer accessor z = m[i] - z := q + z <= q ; CHECK: Finished Expand Whens diff --git a/test/passes/expand-whens/wacc-wdc.fir b/test/passes/expand-whens/wacc-wdc.fir index 77c5b194..25fcff17 100644 --- a/test/passes/expand-whens/wacc-wdc.fir +++ b/test/passes/expand-whens/wacc-wdc.fir @@ -4,10 +4,10 @@ circuit top : input clk : Clock wire p : UInt cmem m : UInt<4>[10], clk - p := UInt(1) + p <= UInt(1) when p : write accessor a = m[UInt(3)] - a := UInt(2) + a <= UInt(2) ; CHECK: Expand Whens @@ -16,8 +16,8 @@ circuit top : ; CHECK: wire p : UInt ; CHECK: cmem m : UInt<4>[10], clk ; CHECK: write accessor a = m[UInt("h3")] -; CHECK: p := UInt("h1") -; CHECK: when p : a := UInt("h2") +; CHECK: p <= UInt("h1") +; CHECK: when p : a <= UInt("h2") ; CHECK: Finished Expand Whens diff --git a/test/passes/infer-types/bundle.fir b/test/passes/infer-types/bundle.fir index 89f9ac22..400aecde 100644 --- a/test/passes/infer-types/bundle.fir +++ b/test/passes/infer-types/bundle.fir @@ -4,21 +4,21 @@ circuit top : module top : wire z : { x : UInt, flip y: SInt} - z.x := UInt(1) - z.y := SInt(1) + z.x <= UInt(1) + z.y <= SInt(1) node x = z.x ;CHECK: node x = z@<t:{ x : UInt, flip y : SInt}>.x@<t:UInt> node y = z.y ;CHECK: node y = z@<t:{ x : UInt, flip y : SInt}>.y@<t:SInt> wire a : UInt<3>[10] ;CHECK: wire a : UInt<3>[10]@<t:UInt>@<t:UInt<3>[10]@<t:UInt>> - a[0] := UInt(1) - a[1] := UInt(1) - a[2] := UInt(1) - a[3] := UInt(1) - a[4] := UInt(1) - a[5] := UInt(1) - a[6] := UInt(1) - a[7] := UInt(1) - a[8] := UInt(1) - a[9] := UInt(1) + a[0] <= UInt(1) + a[1] <= UInt(1) + a[2] <= UInt(1) + a[3] <= UInt(1) + a[4] <= UInt(1) + a[5] <= UInt(1) + a[6] <= UInt(1) + a[7] <= UInt(1) + a[8] <= UInt(1) + a[9] <= UInt(1) node b = a[2] ;CHECK: node b = a@<t:UInt<3>[10]@<t:UInt>>[2]@<t:UInt> read accessor c = a[UInt(3)] ;CHECK: read accessor c = a@<t:UInt<3>[10]@<t:UInt>>[UInt("h3")@<t:UInt>] ; CHECK: Finished Infer Types diff --git a/test/passes/infer-types/gcd.fir b/test/passes/infer-types/gcd.fir index 24860b91..68ec4174 100644 --- a/test/passes/infer-types/gcd.fir +++ b/test/passes/infer-types/gcd.fir @@ -6,8 +6,8 @@ circuit top : input x : UInt input y : UInt output z : UInt - z := subw(x, y) - ;CHECK: z@<t:UInt> := subw(x@<t:UInt>, y@<t:UInt>)@<t:UInt> + z <= subw(x, y) + ;CHECK: z@<t:UInt> <= subw(x@<t:UInt>, y@<t:UInt>)@<t:UInt> module gcd : input a : UInt<16> input b : UInt<16> @@ -19,27 +19,27 @@ circuit top : reg x : UInt,clk,reset reg y : UInt,clk,reset ; CHECK: reg x : UInt, clk@<t:Clock>, reset@<t:UInt>@<t:UInt> - onreset x := UInt(0) - onreset y := UInt(42) + onreset x <= UInt(0) + onreset y <= UInt(42) when gt(x, y) : ;CHECK: when gt(x@<t:UInt>, y@<t:UInt>)@<t:UInt> : inst s of subtracter ;CHECK: inst s of subtracter@<t:{flip x : UInt, flip y : UInt, z : UInt}> - s.x := x - s.y := y - x := s.z - ;CHECK: s@<t:{flip x : UInt, flip y : UInt, z : UInt}>.x@<t:UInt> := x@<t:UInt> - ;CHECK: s@<t:{flip x : UInt, flip y : UInt, z : UInt}>.y@<t:UInt> := y@<t:UInt> - ;CHECK: x@<t:UInt> := s@<t:{flip x : UInt, flip y : UInt, z : UInt}>.z@<t:UInt> + s.x <= x + s.y <= y + x <= s.z + ;CHECK: s@<t:{flip x : UInt, flip y : UInt, z : UInt}>.x@<t:UInt> <= x@<t:UInt> + ;CHECK: s@<t:{flip x : UInt, flip y : UInt, z : UInt}>.y@<t:UInt> <= y@<t:UInt> + ;CHECK: x@<t:UInt> <= s@<t:{flip x : UInt, flip y : UInt, z : UInt}>.z@<t:UInt> else : inst s2 of subtracter - s2.x := x - s2.y := y - y := s2.z + s2.x <= x + s2.y <= y + y <= s2.z when e : - x := a - y := b - z := x + x <= a + y <= b + z <= x module top : input a : UInt<16> input b : UInt<16> @@ -47,11 +47,11 @@ circuit top : input reset : UInt<1> output z : UInt inst i of gcd - i.a := a - i.b := b - i.clk := clk - i.reset := reset - i.e := UInt(1) - z := i.z + i.a <= a + i.b <= b + i.clk <= clk + i.reset <= reset + i.e <= UInt(1) + z <= i.z ; CHECK: Finished Infer Types diff --git a/test/passes/infer-types/primops.fir b/test/passes/infer-types/primops.fir index ac057c68..102a94ae 100644 --- a/test/passes/infer-types/primops.fir +++ b/test/passes/infer-types/primops.fir @@ -9,11 +9,11 @@ circuit top : wire d : SInt<8> wire e : UInt<1> - a := UInt(1) - b := UInt(1) - c := SInt(1) - d := SInt(1) - e := UInt(1) + a <= UInt(1) + b <= UInt(1) + c <= SInt(1) + d <= SInt(1) + e <= UInt(1) node vadd = add(a, c) ;CHECK: node vadd = add(a@<t:UInt>, c@<t:SInt>)@<t:SInt> node wadd = add(a, b) ;CHECK: node wadd = add(a@<t:UInt>, b@<t:UInt>)@<t:UInt> diff --git a/test/passes/infer-widths/dsh.fir b/test/passes/infer-widths/dsh.fir index 77986134..f36b8ad4 100644 --- a/test/passes/infer-widths/dsh.fir +++ b/test/passes/infer-widths/dsh.fir @@ -11,14 +11,14 @@ circuit top : wire b : SInt wire c : UInt wire d : SInt - x := UInt(1) - y := UInt(1) - z := SInt(1) + x <= UInt(1) + y <= UInt(1) + z <= SInt(1) - a := dshl(x,y) - b := dshl(z,y) - c := dshr(x,y) - d := dshr(z,y) + a <= dshl(x,y) + b <= dshl(z,y) + c <= dshr(x,y) + d <= dshr(z,y) ; CHECK: wire a : UInt<23> diff --git a/test/passes/infer-widths/gcd.fir b/test/passes/infer-widths/gcd.fir index 0002fffe..4de2a539 100644 --- a/test/passes/infer-widths/gcd.fir +++ b/test/passes/infer-widths/gcd.fir @@ -6,7 +6,7 @@ circuit top : input x : UInt input y : UInt output q : UInt - q := subw(x, y) + q <= subw(x, y) module gcd : input a : UInt<16> input b : UInt<16> @@ -16,22 +16,22 @@ circuit top : output z : UInt<16> reg x : UInt,clk,reset reg y : UInt,clk,reset - onreset x := UInt(0) - onreset y := UInt(42) + onreset x <= UInt(0) + onreset y <= UInt(42) when gt(x, y) : inst s of subtracter - s.x := x - s.y := y - x := s.q + s.x <= x + s.y <= y + x <= s.q else : inst s2 of subtracter - s2.x := x - s2.y := y - y := s2.q + s2.x <= x + s2.y <= y + y <= s2.q when e : - x := a - y := b - z := x + x <= a + y <= b + z <= x module top : input a : UInt<16> input b : UInt<16> @@ -39,11 +39,11 @@ circuit top : input reset : UInt<1> output z : UInt inst i of gcd - i.a := a - i.b := b - i.clk := clk - i.reset := reset - i.e := UInt(1) - z := i.z + i.a <= a + i.b <= b + i.clk <= clk + i.reset <= reset + i.e <= UInt(1) + z <= i.z ; CHECK: Finished Infer Widths diff --git a/test/passes/infer-widths/shr.fir b/test/passes/infer-widths/shr.fir index c0a6e358..e5a9e15a 100644 --- a/test/passes/infer-widths/shr.fir +++ b/test/passes/infer-widths/shr.fir @@ -10,24 +10,24 @@ circuit MemSerdes : input wide : {req_cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<26>, tag : UInt<7>, rw : UInt<1>}}, req_data : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, tag : UInt<7>}}} output narrow : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, flip resp : {valid : UInt<1>, bits : UInt<16>}} - wide.resp.bits.tag := UInt<1>("h00") - wide.resp.bits.data := UInt<1>("h00") - wide.resp.valid := UInt<1>("h00") - wide.req_data.ready := UInt<1>("h00") - wide.req_cmd.ready := UInt<1>("h00") - narrow.req.bits := UInt<1>("h00") - narrow.req.valid := UInt<1>("h00") + wide.resp.bits.tag <= UInt<1>("h00") + wide.resp.bits.data <= UInt<1>("h00") + wide.resp.valid <= UInt<1>("h00") + wide.req_data.ready <= UInt<1>("h00") + wide.req_cmd.ready <= UInt<1>("h00") + narrow.req.bits <= UInt<1>("h00") + narrow.req.valid <= UInt<1>("h00") node T_218961 = cat(wide.req_cmd.bits.tag, wide.req_cmd.bits.rw) node T_218962 = cat(wide.req_cmd.bits.addr, T_218961) reg out_buf : UInt, clock, reset reg in_buf : UInt, clock, reset reg state : UInt<3>, clock, reset - onreset state := UInt<3>("h00") + onreset state <= UInt<3>("h00") reg send_cnt : UInt<3>, clock, reset - onreset send_cnt := UInt<3>("h00") + onreset send_cnt <= UInt<3>("h00") reg data_send_cnt : UInt<2>, clock, reset - onreset data_send_cnt := UInt<2>("h00") + onreset data_send_cnt <= UInt<2>("h00") node T_218984 = eq(send_cnt, UInt<2>("h02")) node adone = and(narrow.req.ready, T_218984) node T_218987 = eq(send_cnt, UInt<3>("h07")) @@ -36,92 +36,92 @@ circuit MemSerdes : node T_218989 = and(narrow.req.valid, narrow.req.ready) when T_218989 : node T_218991 = addw(send_cnt, UInt<1>("h01")) - send_cnt := T_218991 + send_cnt <= T_218991 node T_218992 = shr(out_buf, 16) - out_buf := T_218992 + out_buf <= T_218992 node T_218993 = and(wide.req_cmd.valid, wide.req_cmd.ready) when T_218993 : node T_218994 = cat(wide.req_cmd.bits.tag, wide.req_cmd.bits.rw) node T_218995 = cat(wide.req_cmd.bits.addr, T_218994) - out_buf := T_218995 + out_buf <= T_218995 node T_218996 = and(wide.req_data.valid, wide.req_data.ready) - when T_218996 : out_buf := wide.req_data.bits.data + when T_218996 : out_buf <= wide.req_data.bits.data node T_218997 = eq(state, UInt<3>("h00")) - wide.req_cmd.ready := T_218997 + wide.req_cmd.ready <= T_218997 node T_218998 = eq(state, UInt<3>("h03")) - wide.req_data.ready := T_218998 + wide.req_data.ready <= T_218998 node T_218999 = eq(state, UInt<3>("h01")) node T_219000 = eq(state, UInt<3>("h02")) node T_219001 = or(T_218999, T_219000) node T_219002 = eq(state, UInt<3>("h04")) node T_219003 = or(T_219001, T_219002) - narrow.req.valid := T_219003 - narrow.req.bits := out_buf + narrow.req.valid <= T_219003 + narrow.req.bits <= out_buf node T_219004 = eq(state, UInt<3>("h00")) node T_219005 = and(T_219004, wide.req_cmd.valid) when T_219005 : node T_219006 = mux(wide.req_cmd.bits.rw, UInt<3>("h02"), UInt<3>("h01")) - state := T_219006 + state <= T_219006 node T_219007 = eq(state, UInt<3>("h01")) node T_219008 = and(T_219007, adone) when T_219008 : - state := UInt<3>("h00") - send_cnt := UInt<1>("h00") + state <= UInt<3>("h00") + send_cnt <= UInt<1>("h00") node T_219010 = eq(state, UInt<3>("h02")) node T_219011 = and(T_219010, adone) when T_219011 : - state := UInt<3>("h03") - send_cnt := UInt<1>("h00") + state <= UInt<3>("h03") + send_cnt <= UInt<1>("h00") node T_219013 = eq(state, UInt<3>("h03")) node T_219014 = and(T_219013, wide.req_data.valid) - when T_219014 : state := UInt<3>("h04") + when T_219014 : state <= UInt<3>("h04") node T_219015 = eq(state, UInt<3>("h04")) node T_219016 = and(T_219015, ddone) when T_219016 : node T_219018 = addw(data_send_cnt, UInt<1>("h01")) - data_send_cnt := T_219018 + data_send_cnt <= T_219018 node T_219020 = eq(data_send_cnt, UInt<2>("h03")) node T_219021 = mux(T_219020, UInt<3>("h00"), UInt<3>("h03")) - state := T_219021 - send_cnt := UInt<1>("h00") + state <= T_219021 + send_cnt <= UInt<1>("h00") reg recv_cnt : UInt<4>, clock, reset - onreset recv_cnt := UInt<4>("h00") + onreset recv_cnt <= UInt<4>("h00") reg data_recv_cnt : UInt<2>, clock, reset - onreset data_recv_cnt := UInt<2>("h00") + onreset data_recv_cnt <= UInt<2>("h00") reg resp_val : UInt<1>, clock, reset - onreset resp_val := UInt<1>("h00") - resp_val := UInt<1>("h00") + onreset resp_val <= UInt<1>("h00") + resp_val <= UInt<1>("h00") when narrow.resp.valid : node T_219031 = addw(recv_cnt, UInt<1>("h01")) - recv_cnt := T_219031 + recv_cnt <= T_219031 node T_219033 = eq(recv_cnt, UInt<4>("h08")) when T_219033 : - recv_cnt := UInt<1>("h00") + recv_cnt <= UInt<1>("h00") node T_219036 = addw(data_recv_cnt, UInt<1>("h01")) - data_recv_cnt := T_219036 - resp_val := UInt<1>("h01") + data_recv_cnt <= T_219036 + resp_val <= UInt<1>("h01") node T_219038 = bits(in_buf, 143, 16) node T_219039 = cat(narrow.resp.bits, T_219038) - in_buf := T_219039 - wide.resp.valid := resp_val + in_buf <= T_219039 + wide.resp.valid <= resp_val wire T_219043 : {data : UInt<128>, tag : UInt<7>} - T_219043.tag := UInt<1>("h00") - T_219043.data := UInt<1>("h00") + T_219043.tag <= UInt<1>("h00") + T_219043.data <= UInt<1>("h00") node T_219048 = bits(in_buf, 6, 0) - T_219043.tag := T_219048 + T_219043.tag <= T_219048 node T_219049 = bits(in_buf, 134, 7) - T_219043.data := T_219049 - wide.resp.bits <> T_219043 + T_219043.data <= T_219049 + wide.resp.bits <- T_219043 diff --git a/test/passes/infer-widths/simple.fir b/test/passes/infer-widths/simple.fir index 13452ae2..e0d23c37 100644 --- a/test/passes/infer-widths/simple.fir +++ b/test/passes/infer-widths/simple.fir @@ -6,19 +6,19 @@ circuit top : input clk : Clock input reset : UInt<1> wire e : UInt<30> - e := UInt(1) + e <= UInt(1) reg y : UInt,clk,reset - y := e + y <= e wire a : UInt<20> - a := UInt(1) + a <= UInt(1) wire b : UInt<10> - b := UInt(1) + b <= UInt(1) wire c : UInt - c := UInt(1) + c <= UInt(1) wire z : UInt - z := mux(c,a,b) + z <= mux(c,a,b) diff --git a/test/passes/inline-indexers/bundle-vecs.fir b/test/passes/inline-indexers/bundle-vecs.fir index f4fc609d..9a28fc3e 100644 --- a/test/passes/inline-indexers/bundle-vecs.fir +++ b/test/passes/inline-indexers/bundle-vecs.fir @@ -4,15 +4,15 @@ circuit top : module top : wire i : UInt - i := UInt(1) + i <= UInt(1) wire j : UInt - j := UInt(1) + j <= UInt(1) wire a : { x : UInt<32>, flip y : UInt<32> }[2] - a[0].x := UInt(1) - a[0].y := UInt(1) - a[1].x := UInt(1) - a[1].y := UInt(1) + a[0].x <= UInt(1) + a[0].y <= UInt(1) + a[1].x <= UInt(1) + a[1].y <= UInt(1) ; CHECK: wire a{{[_$]+}}0{{[_$]+}}x : UInt<32> ; CHECK: wire a{{[_$]+}}0{{[_$]+}}y : UInt<32> ; CHECK: wire a{{[_$]+}}1{{[_$]+}}x : UInt<32> @@ -22,14 +22,14 @@ circuit top : infer accessor b = a[i] ; CHECK: wire b{{[_$]+}}x_2 : UInt<32> ; CHECK: node i_1 = i - ; CHECK: b{{[_$]+}}x_2 := a{{[_$]+}}0{{[_$]+}}x - ; CHECK: when eqv(i_1, UInt("h1")) : b{{[_$]+}}x_2 := a{{[_$]+}}1{{[_$]+}}x + ; CHECK: b{{[_$]+}}x_2 <= a{{[_$]+}}0{{[_$]+}}x + ; CHECK: when eqv(i_1, UInt("h1")) : b{{[_$]+}}x_2 <= a{{[_$]+}}1{{[_$]+}}x ; CHECK: wire b{{[_$]+}}y_2 : UInt<32> ; CHECK: node i_2 = i - ; CHECK: when eqv(i_2, UInt("h0")) : a{{[_$]+}}0{{[_$]+}}y := b{{[_$]+}}y_2 - ; CHECK: when eqv(i_2, UInt("h1")) : a{{[_$]+}}1{{[_$]+}}y := b{{[_$]+}}y_2 - j := b.x - b.y := UInt(1) + ; CHECK: when eqv(i_2, UInt("h0")) : a{{[_$]+}}0{{[_$]+}}y <= b{{[_$]+}}y_2 + ; CHECK: when eqv(i_2, UInt("h1")) : a{{[_$]+}}1{{[_$]+}}y <= b{{[_$]+}}y_2 + j <= b.x + b.y <= UInt(1) ; CHECK: Finished Inline Indexers ; CHECK: Done! diff --git a/test/passes/inline-indexers/init-vecs.fir b/test/passes/inline-indexers/init-vecs.fir index 149215c3..fa2b1553 100644 --- a/test/passes/inline-indexers/init-vecs.fir +++ b/test/passes/inline-indexers/init-vecs.fir @@ -4,11 +4,11 @@ circuit top : module top : wire outs : UInt<32>[2][1] - outs[0][0] := UInt(1) - outs[0][1] := UInt(1) + outs[0][0] <= UInt(1) + outs[0][1] <= UInt(1) write accessor out = outs[UInt(0)] - out[0] := UInt(1) + out[0] <= UInt(1) ; CHECK: Done! diff --git a/test/passes/inline-indexers/simple.fir b/test/passes/inline-indexers/simple.fir index 095094d3..0d28abfb 100644 --- a/test/passes/inline-indexers/simple.fir +++ b/test/passes/inline-indexers/simple.fir @@ -6,14 +6,14 @@ circuit top : output o : UInt wire m : UInt<32>[2] wire i : UInt - m[0] := UInt("h1") - m[1] := UInt("h1") - i := UInt("h1") + m[0] <= UInt("h1") + m[1] <= UInt("h1") + i <= UInt("h1") infer accessor a = m[i] - o := a + o <= a -;CHECK: a_2 := m$0 -;CHECK: when eqv(i_1, UInt("h1")) : a_2 := m$1 +;CHECK: a_2 <= m$0 +;CHECK: when eqv(i_1, UInt("h1")) : a_2 <= m$1 diff --git a/test/passes/inline-indexers/simple2.fir b/test/passes/inline-indexers/simple2.fir index 13fc4416..c3562b0d 100644 --- a/test/passes/inline-indexers/simple2.fir +++ b/test/passes/inline-indexers/simple2.fir @@ -7,19 +7,19 @@ circuit top : output o2 : UInt wire m : UInt<32>[2] wire i : UInt - m[0] := UInt("h1") - m[1] := UInt("h1") - i := UInt("h1") + m[0] <= UInt("h1") + m[1] <= UInt("h1") + i <= UInt("h1") infer accessor a = m[i] - o1 := a - o2 := a + o1 <= a + o2 <= a ;CHECK: wire a_2 : UInt<32> -;CHECK: a_2 := m$0 -;CHECK: when eqv(i_1, UInt("h1")) : a_2 := m$1 +;CHECK: a_2 <= m$0 +;CHECK: when eqv(i_1, UInt("h1")) : a_2 <= m$1 ;CHECK: wire a_3 : UInt<32> -;CHECK: a_3 := m$0 -;CHECK: when eqv(i_2, UInt("h1")) : a_3 := m$1 +;CHECK: a_3 <= m$0 +;CHECK: when eqv(i_2, UInt("h1")) : a_3 <= m$1 diff --git a/test/passes/inline-indexers/simple3.fir b/test/passes/inline-indexers/simple3.fir index b6a7616c..1ef4c192 100644 --- a/test/passes/inline-indexers/simple3.fir +++ b/test/passes/inline-indexers/simple3.fir @@ -6,14 +6,14 @@ circuit top : input in : UInt<32> input i : UInt<1> wire m : UInt<32>[2] - m[0] := UInt("h1") - m[1] := UInt("h1") + m[0] <= UInt("h1") + m[1] <= UInt("h1") infer accessor a = m[i] - a := in + a <= in ;CHECK: wire a_2 : UInt<32> -;CHECK: when eqv(i_1, UInt("h0")) : m$0 := a_2 -;CHECK: when eqv(i_1, UInt("h1")) : m$1 := a_2 +;CHECK: when eqv(i_1, UInt("h0")) : m$0 <= a_2 +;CHECK: when eqv(i_1, UInt("h1")) : m$1 <= a_2 diff --git a/test/passes/inline-indexers/simple4.fir b/test/passes/inline-indexers/simple4.fir index 129de4de..0f16b669 100644 --- a/test/passes/inline-indexers/simple4.fir +++ b/test/passes/inline-indexers/simple4.fir @@ -6,18 +6,18 @@ circuit top : input in : {x : UInt<32>, y : UInt<32>} input i : UInt<1> wire m : {x : UInt<32>, y : UInt<32>}[2] - m[0].x := UInt("h1") - m[0].y := UInt("h1") - m[1].x := UInt("h1") - m[1].y := UInt("h1") + m[0].x <= UInt("h1") + m[0].y <= UInt("h1") + m[1].x <= UInt("h1") + m[1].y <= UInt("h1") infer accessor a = m[i] - a.x := in.x + a.x <= in.x ;CHECK: wire a$x_2 : UInt<32> ;CHECK: node i_1 = i -;CHECK: when eqv(i_1, UInt("h0")) : m$0$x := a$x_2 -;CHECK: when eqv(i_1, UInt("h1")) : m$1$x := a$x_2 -;CHECK: a$x_2 := in$x +;CHECK: when eqv(i_1, UInt("h0")) : m$0$x <= a$x_2 +;CHECK: when eqv(i_1, UInt("h1")) : m$1$x <= a$x_2 +;CHECK: a$x_2 <= in$x ;CHECK: Finished Inline Indexers ;CHECK: Done! diff --git a/test/passes/inline-indexers/simple5.fir b/test/passes/inline-indexers/simple5.fir index 3affa941..544d1f90 100644 --- a/test/passes/inline-indexers/simple5.fir +++ b/test/passes/inline-indexers/simple5.fir @@ -4,18 +4,18 @@ circuit top : module top : output o : UInt - o := UInt(1) + o <= UInt(1) wire m : UInt<32>[2] wire i : UInt - m[0] := UInt("h1") - m[1] := UInt("h1") - i := UInt("h1") + m[0] <= UInt("h1") + m[1] <= UInt("h1") + i <= UInt("h1") when i : infer accessor a = m[i] - o := a + o <= a ;CHECK: when i : -;CHECK: a_2 := m$0 -;CHECK: when eqv(i_1, UInt("h1")) : a_2 := m$1 +;CHECK: a_2 <= m$0 +;CHECK: when eqv(i_1, UInt("h1")) : a_2 <= m$1 ;CHECK: Finished Inline Indexers ;CHECK: Done! diff --git a/test/passes/inline-indexers/simple6.fir b/test/passes/inline-indexers/simple6.fir index b177fba2..a6f59012 100644 --- a/test/passes/inline-indexers/simple6.fir +++ b/test/passes/inline-indexers/simple6.fir @@ -9,16 +9,16 @@ circuit top : wire i : UInt wire j : UInt - m[0][0] := in - m[1][0] := in - m[0][1] := in - m[1][1] := in - i := UInt("h1") - j := UInt("h1") + m[0][0] <= in + m[1][0] <= in + m[0][1] <= in + m[1][1] <= in + i <= UInt("h1") + j <= UInt("h1") write accessor a = m[i] write accessor b = a[j] - b.x := value + b.x <= value ;CHECK: wire b$x_2 : UInt<32> ;CHECK: node j_1 = j @@ -26,19 +26,19 @@ circuit top : ;CHECK: wire a$0$x_2 : UInt<32> ;CHECK: node i_1 = i ;CHECK: when eqv(i_1, UInt("h0")) : -;CHECK: m$0$0$x := a$0$x_2 +;CHECK: m$0$0$x <= a$0$x_2 ;CHECK: when eqv(i_1, UInt("h1")) : -;CHECK: m$1$0$x := a$0$x_2 -;CHECK: a$0$x_2 := b$x_2 +;CHECK: m$1$0$x <= a$0$x_2 +;CHECK: a$0$x_2 <= b$x_2 ;CHECK: when eqv(j_1, UInt("h1")) : ;CHECK: wire a$1$x_2 : UInt<32> ;CHECK: node i_2 = i ;CHECK: when eqv(i_2, UInt("h0")) : -;CHECK: m$0$1$x := a$1$x_2 +;CHECK: m$0$1$x <= a$1$x_2 ;CHECK: when eqv(i_2, UInt("h1")) : -;CHECK: m$1$1$x := a$1$x_2 -;CHECK: a$1$x_2 := b$x_2 -;CHECK: b$x_2 := value +;CHECK: m$1$1$x <= a$1$x_2 +;CHECK: a$1$x_2 <= b$x_2 +;CHECK: b$x_2 <= value diff --git a/test/passes/inline-indexers/simple7.fir b/test/passes/inline-indexers/simple7.fir index cc9c6231..2ac85a58 100644 --- a/test/passes/inline-indexers/simple7.fir +++ b/test/passes/inline-indexers/simple7.fir @@ -6,8 +6,8 @@ circuit top : output out : UInt<64> input index : UInt<1> wire T_292 : UInt<64>[2] - T_292[0] := UInt(1) - T_292[1] := UInt(1) + T_292[0] <= UInt(1) + T_292[1] <= UInt(1) infer accessor T_297 = T_292[index] - out := T_297 + out <= T_297 ;CHECK: Done! diff --git a/test/passes/inline-indexers/simple8.fir b/test/passes/inline-indexers/simple8.fir index a02395a7..427dee98 100644 --- a/test/passes/inline-indexers/simple8.fir +++ b/test/passes/inline-indexers/simple8.fir @@ -9,22 +9,22 @@ circuit top : input clock : Clock input reset : UInt<1> - resp[0] := UInt<1>("h00") - resp[1] := UInt<1>("h00") - resp[2] := UInt<1>("h00") - resp[3] := UInt<1>("h00") - write.ready := UInt<1>("h00") - read.ready := UInt<1>("h00") + resp[0] <= UInt<1>("h00") + resp[1] <= UInt<1>("h00") + resp[2] <= UInt<1>("h00") + resp[3] <= UInt<1>("h00") + write.ready <= UInt<1>("h00") + read.ready <= UInt<1>("h00") node waddr = shr(write.bits.addr, 4) node raddr = shr(read.bits.addr, 4) node T_65 = bits(write.bits.way_en, 1, 0) node T_66 = bits(read.bits.way_en, 1, 0) wire T_75 : UInt<128>[2] - T_75[0] := UInt<1>("h00") - T_75[1] := UInt<1>("h00") + T_75[0] <= UInt<1>("h00") + T_75[1] <= UInt<1>("h00") reg T_81 : UInt<12>, clock, reset when read.valid : - T_81 := read.bits.addr + T_81 <= read.bits.addr skip cmem T_84 : UInt<128>[256], clock node T_86 = neq(T_65, UInt<1>("h00")) @@ -37,13 +37,13 @@ circuit top : node T_92 = bit(T_65, 0) node T_93 = bit(T_65, 1) wire T_95 : UInt<1>[2] - T_95[0] := T_92 - T_95[1] := T_93 + T_95[0] <= T_92 + T_95[1] <= T_93 node T_100 = subw(UInt<64>("h00"), T_95[0]) node T_102 = subw(UInt<64>("h00"), T_95[1]) wire T_104 : UInt<64>[2] - T_104[0] := T_100 - T_104[1] := T_102 + T_104[0] <= T_100 + T_104[1] <= T_102 node T_108 = cat(T_104[1], T_104[0]) infer accessor T_109 = T_84[waddr] node T_110 = not(T_108) @@ -51,19 +51,19 @@ circuit top : node T_112 = and(T_91, T_108) node T_113 = or(T_111, T_112) wire T_114 : UInt<128> - T_114 := UInt<1>("h00") - T_114 := T_113 + T_114 <= UInt<1>("h00") + T_114 <= T_113 infer accessor T_116 = T_84[waddr] - T_116 := T_114 + T_116 <= T_114 skip node T_118 = neq(T_66, UInt<1>("h00")) node T_119 = and(T_118, read.valid) reg T_120 : UInt<8>, clock, reset when T_119 : - T_120 := raddr + T_120 <= raddr skip infer accessor T_121 = T_84[T_120] - T_75[0] := T_121 + T_75[0] <= T_121 cmem T_124 : UInt<128>[256], clock node T_126 = neq(T_65, UInt<1>("h00")) node T_127 = and(T_126, write.valid) @@ -75,13 +75,13 @@ circuit top : node T_132 = bit(T_65, 0) node T_133 = bit(T_65, 1) wire T_135 : UInt<1>[2] - T_135[0] := T_132 - T_135[1] := T_133 + T_135[0] <= T_132 + T_135[1] <= T_133 node T_140 = subw(UInt<64>("h00"), T_135[0]) node T_142 = subw(UInt<64>("h00"), T_135[1]) wire T_144 : UInt<64>[2] - T_144[0] := T_140 - T_144[1] := T_142 + T_144[0] <= T_140 + T_144[1] <= T_142 node T_148 = cat(T_144[1], T_144[0]) infer accessor T_149 = T_124[waddr] node T_150 = not(T_148) @@ -89,51 +89,51 @@ circuit top : node T_152 = and(T_131, T_148) node T_153 = or(T_151, T_152) wire T_154 : UInt<128> - T_154 := UInt<1>("h00") - T_154 := T_153 + T_154 <= UInt<1>("h00") + T_154 <= T_153 infer accessor T_156 = T_124[waddr] - T_156 := T_154 + T_156 <= T_154 skip node T_158 = neq(T_66, UInt<1>("h00")) node T_159 = and(T_158, read.valid) reg T_160 : UInt<8>, clock, reset when T_159 : - T_160 := raddr + T_160 <= raddr skip infer accessor T_161 = T_124[T_160] - T_75[1] := T_161 + T_75[1] <= T_161 node T_162 = bits(T_75[0], 63, 0) node T_163 = bits(T_75[1], 63, 0) wire T_165 : UInt<64>[2] - T_165[0] := T_162 - T_165[1] := T_163 + T_165[0] <= T_162 + T_165[1] <= T_163 node T_169 = bits(T_81, 3, 3) infer accessor T_170 = T_165[T_169] wire T_172 : UInt<64>[2] - T_172[0] := T_170 - T_172[1] := T_165[1] + T_172[0] <= T_170 + T_172[1] <= T_165[1] node T_176 = cat(T_172[1], T_172[0]) - resp[0] := T_176 + resp[0] <= T_176 node T_177 = bits(T_75[0], 127, 64) node T_178 = bits(T_75[1], 127, 64) wire T_180 : UInt<64>[2] - T_180[0] := T_177 - T_180[1] := T_178 + T_180[0] <= T_177 + T_180[1] <= T_178 node T_184 = bits(T_81, 3, 3) infer accessor T_185 = T_180[T_184] wire T_187 : UInt<64>[2] - T_187[0] := T_185 - T_187[1] := T_180[1] + T_187[0] <= T_185 + T_187[1] <= T_180[1] node T_191 = cat(T_187[1], T_187[0]) - resp[1] := T_191 + resp[1] <= T_191 node T_192 = bits(write.bits.way_en, 3, 2) node T_193 = bits(read.bits.way_en, 3, 2) wire T_202 : UInt<128>[2] - T_202[0] := UInt<1>("h00") - T_202[1] := UInt<1>("h00") + T_202[0] <= UInt<1>("h00") + T_202[1] <= UInt<1>("h00") reg T_208 : UInt<12>, clock, reset when read.valid : - T_208 := read.bits.addr + T_208 <= read.bits.addr skip cmem T_211 : UInt<128>[256], clock node T_213 = neq(T_192, UInt<1>("h00")) @@ -146,13 +146,13 @@ circuit top : node T_219 = bit(T_192, 0) node T_220 = bit(T_192, 1) wire T_222 : UInt<1>[2] - T_222[0] := T_219 - T_222[1] := T_220 + T_222[0] <= T_219 + T_222[1] <= T_220 node T_227 = subw(UInt<64>("h00"), T_222[0]) node T_229 = subw(UInt<64>("h00"), T_222[1]) wire T_231 : UInt<64>[2] - T_231[0] := T_227 - T_231[1] := T_229 + T_231[0] <= T_227 + T_231[1] <= T_229 node T_235 = cat(T_231[1], T_231[0]) infer accessor T_236 = T_211[waddr] node T_237 = not(T_235) @@ -160,19 +160,19 @@ circuit top : node T_239 = and(T_218, T_235) node T_240 = or(T_238, T_239) wire T_241 : UInt<128> - T_241 := UInt<1>("h00") - T_241 := T_240 + T_241 <= UInt<1>("h00") + T_241 <= T_240 infer accessor T_243 = T_211[waddr] - T_243 := T_241 + T_243 <= T_241 skip node T_245 = neq(T_193, UInt<1>("h00")) node T_246 = and(T_245, read.valid) reg T_247 : UInt<8>, clock, reset when T_246 : - T_247 := raddr + T_247 <= raddr skip infer accessor T_248 = T_211[T_247] - T_202[0] := T_248 + T_202[0] <= T_248 cmem T_251 : UInt<128>[256], clock node T_253 = neq(T_192, UInt<1>("h00")) node T_254 = and(T_253, write.valid) @@ -184,13 +184,13 @@ circuit top : node T_259 = bit(T_192, 0) node T_260 = bit(T_192, 1) wire T_262 : UInt<1>[2] - T_262[0] := T_259 - T_262[1] := T_260 + T_262[0] <= T_259 + T_262[1] <= T_260 node T_267 = subw(UInt<64>("h00"), T_262[0]) node T_269 = subw(UInt<64>("h00"), T_262[1]) wire T_271 : UInt<64>[2] - T_271[0] := T_267 - T_271[1] := T_269 + T_271[0] <= T_267 + T_271[1] <= T_269 node T_275 = cat(T_271[1], T_271[0]) infer accessor T_276 = T_251[waddr] node T_277 = not(T_275) @@ -198,43 +198,43 @@ circuit top : node T_279 = and(T_258, T_275) node T_280 = or(T_278, T_279) wire T_281 : UInt<128> - T_281 := UInt<1>("h00") - T_281 := T_280 + T_281 <= UInt<1>("h00") + T_281 <= T_280 infer accessor T_283 = T_251[waddr] - T_283 := T_281 + T_283 <= T_281 skip node T_285 = neq(T_193, UInt<1>("h00")) node T_286 = and(T_285, read.valid) reg T_287 : UInt<8>, clock, reset when T_286 : - T_287 := raddr + T_287 <= raddr skip infer accessor T_288 = T_251[T_287] - T_202[1] := T_288 + T_202[1] <= T_288 node T_289 = bits(T_202[0], 63, 0) node T_290 = bits(T_202[1], 63, 0) wire T_292 : UInt<64>[2] - T_292[0] := T_289 - T_292[1] := T_290 + T_292[0] <= T_289 + T_292[1] <= T_290 node T_296 = bits(T_208, 3, 3) infer accessor T_297 = T_292[T_296] wire T_299 : UInt<64>[2] - T_299[0] := T_297 - T_299[1] := T_292[1] + T_299[0] <= T_297 + T_299[1] <= T_292[1] node T_303 = cat(T_299[1], T_299[0]) - resp[2] := T_303 + resp[2] <= T_303 node T_304 = bits(T_202[0], 127, 64) node T_305 = bits(T_202[1], 127, 64) wire T_307 : UInt<64>[2] - T_307[0] := T_304 - T_307[1] := T_305 + T_307[0] <= T_304 + T_307[1] <= T_305 node T_311 = bits(T_208, 3, 3) infer accessor T_312 = T_307[T_311] wire T_314 : UInt<64>[2] - T_314[0] := T_312 - T_314[1] := T_307[1] + T_314[0] <= T_312 + T_314[1] <= T_307[1] node T_318 = cat(T_314[1], T_314[0]) - resp[3] := T_318 - read.ready := UInt<1>("h01") - write.ready := UInt<1>("h01") + resp[3] <= T_318 + read.ready <= UInt<1>("h01") + write.ready <= UInt<1>("h01") ;CHECK: Done! diff --git a/test/passes/inline-indexers/simple9.fir b/test/passes/inline-indexers/simple9.fir index a40abb17..766e161c 100644 --- a/test/passes/inline-indexers/simple9.fir +++ b/test/passes/inline-indexers/simple9.fir @@ -9,10 +9,10 @@ circuit top : input clock : Clock output out : UInt<1> reg T_4590 : UInt<1>[2], clock, reset - T_4590[0] := UInt(0) - T_4590[1] := UInt(0) - out := UInt(0) + T_4590[0] <= UInt(0) + T_4590[1] <= UInt(0) + out <= UInt(0) when T_4910 : infer accessor T_4911 = T_4590[T_4581] - out := T_4911 + out <= T_4911 ;CHECK: Done! diff --git a/test/passes/inline/gcd.fir b/test/passes/inline/gcd.fir index 6ae42834..781b949c 100644 --- a/test/passes/inline/gcd.fir +++ b/test/passes/inline/gcd.fir @@ -7,7 +7,7 @@ circuit top : input x : UInt input y : UInt output q : UInt - q := subw(x, y) + q <= subw(x, y) module gcd : input a : UInt<16> input b : UInt<16> @@ -17,22 +17,22 @@ circuit top : output z : UInt<16> reg x : UInt,clk,reset reg y : UInt,clk,reset - onreset x := UInt(0) - onreset y := UInt(42) + onreset x <= UInt(0) + onreset y <= UInt(42) when gt(x, y) : inst s of subtracter - s.x := x - s.y := y - x := s.q + s.x <= x + s.y <= y + x <= s.q else : inst s2 of subtracter - s2.x := x - s2.y := y - y := s2.q + s2.x <= x + s2.y <= y + y <= s2.q when e : - x := a - y := b - z := x + x <= a + y <= b + z <= x module top : input a : UInt<16> input b : UInt<16> @@ -40,11 +40,11 @@ circuit top : input reset : UInt<1> output z : UInt inst i of gcd - i.a := a - i.b := b - i.clk := clk - i.reset := reset - i.e := UInt(1) - z := i.z + i.a <= a + i.b <= b + i.clk <= clk + i.reset <= reset + i.e <= UInt(1) + z <= i.z ; CHECK: Finished Inline Instances diff --git a/test/passes/jacktest/ALUTop.fir b/test/passes/jacktest/ALUTop.fir index ef1ac7a9..74abe0bd 100644 --- a/test/passes/jacktest/ALUTop.fir +++ b/test/passes/jacktest/ALUTop.fir @@ -49,12 +49,12 @@ circuit ALUTop : node T_194 = eq(UInt<4>(0), alu_op) node oot = mux(T_194, T_157, T_193) node T_195 = bits(oot, 31, 0) - out := T_195 + out <= T_195 node T_196 = bit(alu_op, 0) node T_197 = subw(UInt<1>(0), B) node T_198 = mux(T_196, T_197, B) node T_199 = addw(A, T_198) - sum := T_199 + sum <= T_199 module ALUdec : input opcode : UInt<7> input funct : UInt<3> @@ -97,7 +97,7 @@ circuit ALUTop : node T_232 = mux(T_231, UInt<4>(0), T_230) node T_233 = eq(UInt<7>(55), opcode) node alu_op2 = mux(T_233, UInt<4>(11), T_232) - alu_op := alu_op2 + alu_op <= alu_op2 module ALUTop : input B : UInt<32> output out : UInt<32> @@ -108,10 +108,10 @@ circuit ALUTop : inst alu of ALU inst alu_dec of ALUdec - alu_dec.opcode := opcode - alu_dec.funct := funct - alu_dec.add_rshift_type := add_rshift_type - alu.A := A - alu.B := B - out := alu.out - alu.alu_op := alu_dec.alu_op + alu_dec.opcode <= opcode + alu_dec.funct <= funct + alu_dec.add_rshift_type <= add_rshift_type + alu.A <= A + alu.B <= B + out <= alu.out + alu.alu_op <= alu_dec.alu_op diff --git a/test/passes/jacktest/ComplexAssign.fir b/test/passes/jacktest/ComplexAssign.fir index e3858765..9ce51652 100644 --- a/test/passes/jacktest/ComplexAssign.fir +++ b/test/passes/jacktest/ComplexAssign.fir @@ -7,9 +7,9 @@ circuit ComplexAssign : input e : UInt<1> when e : wire T_18 : {re : UInt<10>, im : UInt<10>} - T_18 := in - out.re := T_18.re - out.im := T_18.im + T_18 <= in + out.re <= T_18.re + out.im <= T_18.im else : - out.re := UInt<1>(0) - out.im := UInt<1>(0) + out.re <= UInt<1>(0) + out.im <= UInt<1>(0) diff --git a/test/passes/jacktest/Counter.fir b/test/passes/jacktest/Counter.fir index a04ddf2f..db2b5d62 100644 --- a/test/passes/jacktest/Counter.fir +++ b/test/passes/jacktest/Counter.fir @@ -9,10 +9,10 @@ circuit Counter : input amt : UInt<4> reg T_13 : UInt<8>,clk,reset - onreset T_13 := UInt<8>(0) + onreset T_13 <= UInt<8>(0) when inc : node T_14 = addw(T_13, amt) node T_15 = gt(T_14, UInt<8>(255)) node T_16 = mux(T_15, UInt<1>(0), T_14) - T_13 := T_16 - tot := T_13 + T_13 <= T_16 + tot <= T_13 diff --git a/test/passes/jacktest/EnableShiftRegister.fir b/test/passes/jacktest/EnableShiftRegister.fir index 902098b7..7937d37f 100644 --- a/test/passes/jacktest/EnableShiftRegister.fir +++ b/test/passes/jacktest/EnableShiftRegister.fir @@ -9,16 +9,16 @@ circuit EnableShiftRegister : input shift : UInt<1> reg r0 : UInt<4>,clk,reset - onreset r0 := UInt<4>(0) + onreset r0 <= UInt<4>(0) reg r1 : UInt<4>,clk,reset - onreset r1 := UInt<4>(0) + onreset r1 <= UInt<4>(0) reg r2 : UInt<4>,clk,reset - onreset r2 := UInt<4>(0) + onreset r2 <= UInt<4>(0) reg r3 : UInt<4>,clk,reset - onreset r3 := UInt<4>(0) + onreset r3 <= UInt<4>(0) when shift : - r0 := in - r1 := r0 - r2 := r1 - r3 := r2 - out := r3 + r0 <= in + r1 <= r0 + r2 <= r1 + r3 <= r2 + out <= r3 diff --git a/test/passes/jacktest/LFSR16.fir b/test/passes/jacktest/LFSR16.fir index b8e31e99..770ac3e6 100644 --- a/test/passes/jacktest/LFSR16.fir +++ b/test/passes/jacktest/LFSR16.fir @@ -8,7 +8,7 @@ circuit LFSR16 : input reset : UInt<1> reg res : UInt<16>,clk,reset - onreset res := UInt<16>(1) + onreset res <= UInt<16>(1) when inc : node T_16 = bit(res, 0) node T_17 = bit(res, 2) @@ -19,5 +19,5 @@ circuit LFSR16 : node T_22 = xor(T_20, T_21) node T_23 = bits(res, 15, 1) node T_24 = cat(T_22, T_23) - res := T_24 - out := res + res <= T_24 + out <= res diff --git a/test/passes/jacktest/MemorySearch.fir b/test/passes/jacktest/MemorySearch.fir index be6b3274..1e07596c 100644 --- a/test/passes/jacktest/MemorySearch.fir +++ b/test/passes/jacktest/MemorySearch.fir @@ -10,26 +10,26 @@ circuit MemorySearch : output done : UInt<1> reg index : UInt<3>,clk,reset - onreset index := UInt<3>(0) + onreset index <= UInt<3>(0) wire elts : UInt<4>[7] - elts[0] := UInt<4>(0) - elts[1] := UInt<4>(4) - elts[2] := UInt<4>(15) - elts[3] := UInt<4>(14) - elts[4] := UInt<4>(2) - elts[5] := UInt<4>(5) - elts[6] := UInt<4>(13) + elts[0] <= UInt<4>(0) + elts[1] <= UInt<4>(4) + elts[2] <= UInt<4>(15) + elts[3] <= UInt<4>(14) + elts[4] <= UInt<4>(2) + elts[5] <= UInt<4>(5) + elts[6] <= UInt<4>(13) infer accessor elt = elts[index] node T_35 = not(en) node T_36 = eq(elt, target) node T_37 = eq(index, UInt<3>(7)) node T_38 = or(T_36, T_37) node end = and(T_35, T_38) - when en : index := UInt<1>(0) + when en : index <= UInt<1>(0) else : node T_39 = not(end) when T_39 : node T_40 = addw(index, UInt<1>(1)) - index := T_40 - done := end - address := index + index <= T_40 + done <= end + address <= index diff --git a/test/passes/jacktest/ModuleVec.fir b/test/passes/jacktest/ModuleVec.fir index 8ac27aaf..9a8e7f2c 100644 --- a/test/passes/jacktest/ModuleVec.fir +++ b/test/passes/jacktest/ModuleVec.fir @@ -6,13 +6,13 @@ circuit ModuleVec : output out : UInt<32> node T_33 = addw(in, UInt<1>(1)) - out := T_33 + out <= T_33 module PlusOne_25 : input in : UInt<32> output out : UInt<32> node T_34 = addw(in, UInt<1>(1)) - out := T_34 + out <= T_34 module ModuleVec : input ins : UInt<32>[2] output outs : UInt<32>[2] @@ -20,9 +20,9 @@ circuit ModuleVec : inst T_35 of PlusOne inst T_36 of PlusOne_25 wire pluses : {flip in : UInt<32>, out : UInt<32>}[2] - pluses[0] := T_35 - pluses[1] := T_36 - pluses[0].in := ins[0] - outs[0] := pluses[0].out - pluses[1].in := ins[1] - outs[1] := pluses[1].out + pluses[0] <= T_35 + pluses[1] <= T_36 + pluses[0].in <= ins[0] + outs[0] <= pluses[0].out + pluses[1].in <= ins[1] + outs[1] <= pluses[1].out diff --git a/test/passes/jacktest/Mul.fir b/test/passes/jacktest/Mul.fir index 51753ece..8a3223e7 100644 --- a/test/passes/jacktest/Mul.fir +++ b/test/passes/jacktest/Mul.fir @@ -7,23 +7,23 @@ circuit Mul : output z : UInt<4> wire tbl : UInt<4>[16] - tbl[0] := UInt<4>(0) - tbl[1] := UInt<4>(0) - tbl[2] := UInt<4>(0) - tbl[3] := UInt<4>(0) - tbl[4] := UInt<4>(0) - tbl[5] := UInt<4>(1) - tbl[6] := UInt<4>(2) - tbl[7] := UInt<4>(3) - tbl[8] := UInt<4>(0) - tbl[9] := UInt<4>(2) - tbl[10] := UInt<4>(4) - tbl[11] := UInt<4>(6) - tbl[12] := UInt<4>(0) - tbl[13] := UInt<4>(3) - tbl[14] := UInt<4>(6) - tbl[15] := UInt<4>(9) + tbl[0] <= UInt<4>(0) + tbl[1] <= UInt<4>(0) + tbl[2] <= UInt<4>(0) + tbl[3] <= UInt<4>(0) + tbl[4] <= UInt<4>(0) + tbl[5] <= UInt<4>(1) + tbl[6] <= UInt<4>(2) + tbl[7] <= UInt<4>(3) + tbl[8] <= UInt<4>(0) + tbl[9] <= UInt<4>(2) + tbl[10] <= UInt<4>(4) + tbl[11] <= UInt<4>(6) + tbl[12] <= UInt<4>(0) + tbl[13] <= UInt<4>(3) + tbl[14] <= UInt<4>(6) + tbl[15] <= UInt<4>(9) node T_42 = shl(x, 2) node T_43 = or(T_42, y) infer accessor T_44 = tbl[T_43] - z := T_44 + z <= T_44 diff --git a/test/passes/jacktest/RegisterVecShift.fir b/test/passes/jacktest/RegisterVecShift.fir index 02ae03b5..eb2a0f34 100644 --- a/test/passes/jacktest/RegisterVecShift.fir +++ b/test/passes/jacktest/RegisterVecShift.fir @@ -12,19 +12,19 @@ circuit RegisterVecShift : reg delays : UInt<4>[4],clk,reset when reset : wire T_33 : UInt<4>[4] - T_33[0] := UInt<4>(0) - T_33[1] := UInt<4>(0) - T_33[2] := UInt<4>(0) - T_33[3] := UInt<4>(0) - delays := T_33 + T_33[0] <= UInt<4>(0) + T_33[1] <= UInt<4>(0) + T_33[2] <= UInt<4>(0) + T_33[3] <= UInt<4>(0) + delays <= T_33 when load : - delays[0] := ins[0] - delays[1] := ins[1] - delays[2] := ins[2] - delays[3] := ins[3] + delays[0] <= ins[0] + delays[1] <= ins[1] + delays[2] <= ins[2] + delays[3] <= ins[3] else : when shift : - delays[0] := ins[0] - delays[1] := delays[0] - delays[2] := delays[1] - delays[3] := delays[2] - out := delays[3] + delays[0] <= ins[0] + delays[1] <= delays[0] + delays[2] <= delays[1] + delays[3] <= delays[2] + out <= delays[3] diff --git a/test/passes/jacktest/Rom.fir b/test/passes/jacktest/Rom.fir index 382ca5c9..6e4b3cc7 100644 --- a/test/passes/jacktest/Rom.fir +++ b/test/passes/jacktest/Rom.fir @@ -6,21 +6,21 @@ circuit Rom : input addr : UInt<4> wire r : UInt<5>[16] - r[0] := UInt<5>(0) - r[1] := UInt<5>(2) - r[2] := UInt<5>(4) - r[3] := UInt<5>(6) - r[4] := UInt<5>(8) - r[5] := UInt<5>(10) - r[6] := UInt<5>(12) - r[7] := UInt<5>(14) - r[8] := UInt<5>(16) - r[9] := UInt<5>(18) - r[10] := UInt<5>(20) - r[11] := UInt<5>(22) - r[12] := UInt<5>(24) - r[13] := UInt<5>(26) - r[14] := UInt<5>(28) - r[15] := UInt<5>(30) + r[0] <= UInt<5>(0) + r[1] <= UInt<5>(2) + r[2] <= UInt<5>(4) + r[3] <= UInt<5>(6) + r[4] <= UInt<5>(8) + r[5] <= UInt<5>(10) + r[6] <= UInt<5>(12) + r[7] <= UInt<5>(14) + r[8] <= UInt<5>(16) + r[9] <= UInt<5>(18) + r[10] <= UInt<5>(20) + r[11] <= UInt<5>(22) + r[12] <= UInt<5>(24) + r[13] <= UInt<5>(26) + r[14] <= UInt<5>(28) + r[15] <= UInt<5>(30) infer accessor T_39 = r[addr] - out := T_39 + out <= T_39 diff --git a/test/passes/jacktest/Stack.fir b/test/passes/jacktest/Stack.fir index f4fd896c..ed718331 100644 --- a/test/passes/jacktest/Stack.fir +++ b/test/passes/jacktest/Stack.fir @@ -12,26 +12,26 @@ circuit Stack : cmem stack_mem : UInt<32>[16],clk reg sp : UInt<5>,clk,reset - onreset sp := UInt<5>(0) + onreset sp <= UInt<5>(0) reg out : UInt<32>,clk,reset - onreset out := UInt<32>(0) + onreset out <= UInt<32>(0) when en : node T_30 = lt(sp, UInt<5>(16)) node T_31 = and(push, T_30) when T_31 : infer accessor T_32 = stack_mem[sp] - T_32 := dataIn + T_32 <= dataIn node T_33 = addw(sp, UInt<1>(1)) - sp := T_33 + sp <= T_33 else : node T_34 = gt(sp, UInt<1>(0)) node T_35 = and(pop, T_34) when T_35 : node T_36 = subw(sp, UInt<1>(1)) - sp := T_36 + sp <= T_36 node T_37 = gt(sp, UInt<1>(0)) when T_37 : node T_38 = subw(sp, UInt<1>(1)) infer accessor T_39 = stack_mem[T_38] - out := T_39 - dataOut := out + out <= T_39 + dataOut <= out diff --git a/test/passes/jacktest/Tbl.fir b/test/passes/jacktest/Tbl.fir index 22c5fd5c..4ae87360 100644 --- a/test/passes/jacktest/Tbl.fir +++ b/test/passes/jacktest/Tbl.fir @@ -9,11 +9,11 @@ circuit Tbl : input we : UInt<1> cmem m : UInt<10>[256],clk - o := UInt<1>(0) + o <= UInt<1>(0) when we : infer accessor T_13 = m[i] node T_14 = bits(d, 9, 0) - T_13 := T_14 + T_13 <= T_14 else : infer accessor T_15 = m[i] - o := T_15 + o <= T_15 diff --git a/test/passes/jacktest/VendingMachine.fir b/test/passes/jacktest/VendingMachine.fir index 338df3f4..5ecfe522 100644 --- a/test/passes/jacktest/VendingMachine.fir +++ b/test/passes/jacktest/VendingMachine.fir @@ -9,24 +9,24 @@ circuit VendingMachine : input reset : UInt<1> reg state : UInt<3>,clk,reset - onreset state := UInt<3>(0) + onreset state <= UInt<3>(0) node T_22 = eq(state, UInt<3>(0)) when T_22 : - when nickel : state := UInt<3>(1) - when dime : state := UInt<3>(2) + when nickel : state <= UInt<3>(1) + when dime : state <= UInt<3>(2) node T_23 = eq(state, UInt<3>(1)) when T_23 : - when nickel : state := UInt<3>(2) - when dime : state := UInt<3>(3) + when nickel : state <= UInt<3>(2) + when dime : state <= UInt<3>(3) node T_24 = eq(state, UInt<3>(2)) when T_24 : - when nickel : state := UInt<3>(3) - when dime : state := UInt<3>(4) + when nickel : state <= UInt<3>(3) + when dime : state <= UInt<3>(4) node T_25 = eq(state, UInt<3>(3)) when T_25 : - when nickel : state := UInt<3>(4) - when dime : state := UInt<3>(4) + when nickel : state <= UInt<3>(4) + when dime : state <= UInt<3>(4) node T_26 = eq(state, UInt<3>(4)) - when T_26 : state := UInt<3>(0) + when T_26 : state <= UInt<3>(0) node T_27 = eq(state, UInt<3>(4)) - valid := T_27 + valid <= T_27 diff --git a/test/passes/jacktest/gcd.fir b/test/passes/jacktest/gcd.fir index c461efe3..99667b3b 100644 --- a/test/passes/jacktest/gcd.fir +++ b/test/passes/jacktest/gcd.fir @@ -15,13 +15,13 @@ circuit GCD : node T_17 = gt(x, y) when T_17 : node T_18 = subw(x, y) - x := T_18 + x <= T_18 else : node T_19 = subw(y, x) - y := T_19 + y <= T_19 when e : - x := a - y := b - z := x + x <= a + y <= b + z <= x node T_20 = eq(y, UInt<1>(0)) - v := T_20 + v <= T_20 diff --git a/test/passes/jacktest/risc.fir b/test/passes/jacktest/risc.fir index a28dc5a5..fdc80ee1 100644 --- a/test/passes/jacktest/risc.fir +++ b/test/passes/jacktest/risc.fir @@ -14,7 +14,7 @@ circuit Risc : cmem file : UInt<32>[256],clk cmem code : UInt<32>[256],clk reg pc : UInt<8>,clk,reset - onreset pc := UInt<8>(0) + onreset pc <= UInt<8>(0) infer accessor inst = code[pc] node op = bits(inst, 31, 24) node rci = bits(inst, 23, 16) @@ -27,28 +27,28 @@ circuit Risc : infer accessor T_54 = file[rbi] node rb = mux(T_53, UInt<1>(0), T_54) wire rc : UInt<32> - valid := UInt<1>(0) - out := UInt<1>(0) - rc := UInt<1>(0) + valid <= UInt<1>(0) + out <= UInt<1>(0) + rc <= UInt<1>(0) when isWr : infer accessor T_55 = code[wrAddr] - T_55 := wrData - else : when boot : pc := UInt<1>(0) + T_55 <= wrData + else : when boot : pc <= UInt<1>(0) else : node T_56 = eq(UInt<1>(0), op) when T_56 : node T_57 = addw(ra, rb) - rc := T_57 + rc <= T_57 node T_58 = eq(UInt<1>(1), op) when T_58 : node T_59 = shl(rai, 8) node T_60 = or(T_59, rbi) - rc := T_60 - out := rc + rc <= T_60 + out <= rc node T_61 = eq(rci, UInt<8>(255)) - when T_61 : valid := UInt<1>(1) + when T_61 : valid <= UInt<1>(1) else : infer accessor T_62 = file[rci] - T_62 := rc + T_62 <= rc node T_63 = addw(pc, UInt<1>(1)) - pc := T_63 + pc <= T_63 diff --git a/test/passes/lower-to-ground/accessor.fir b/test/passes/lower-to-ground/accessor.fir index 4d55d0f6..c712fdc2 100644 --- a/test/passes/lower-to-ground/accessor.fir +++ b/test/passes/lower-to-ground/accessor.fir @@ -15,18 +15,18 @@ circuit top : infer accessor b = a[i] ; CHECK: indexer b = (a{{[_$]+}}0 a{{[_$]+}}1 a{{[_$]+}}2 a{{[_$]+}}3)[i] : UInt<32> - j := b + j <= b infer accessor c = a[i] ; CHECK: indexer (a{{[_$]+}}0 a{{[_$]+}}1 a{{[_$]+}}2 a{{[_$]+}}3)[i] = c : UInt<32> - c := j + c <= j cmem p : UInt<32>[4],clk infer accessor t = p[i] ; CHECK: read accessor t = p[i] - j := t + j <= t infer accessor r = p[i] ; CHECK: write accessor r = p[i] - r := j + r <= j ; CHECK: Finished Lower To Ground diff --git a/test/passes/lower-to-ground/bundle-vecs.fir b/test/passes/lower-to-ground/bundle-vecs.fir index 7d37e65c..b0de26f4 100644 --- a/test/passes/lower-to-ground/bundle-vecs.fir +++ b/test/passes/lower-to-ground/bundle-vecs.fir @@ -15,12 +15,12 @@ circuit top : infer accessor b = a[i] ; CHECK: indexer b{{[_$]+}}x = (a{{[_$]+}}0{{[_$]+}}x a{{[_$]+}}1{{[_$]+}}x)[i] : UInt<32> ; CHECK: indexer (a{{[_$]+}}0{{[_$]+}}y a{{[_$]+}}1{{[_$]+}}y)[i] = b{{[_$]+}}y : UInt<32> - j := b + j <= b infer accessor c = a[i] ; CHECK: indexer (a{{[_$]+}}0{{[_$]+}}x a{{[_$]+}}1{{[_$]+}}x)[i] = c{{[_$]+}}x : UInt<32> ; CHECK: indexer c{{[_$]+}}y = (a{{[_$]+}}0{{[_$]+}}y a{{[_$]+}}1{{[_$]+}}y)[i] : UInt<32> - c := j + c <= j ; CHECK: Finished Lower To Ground diff --git a/test/passes/lower-to-ground/bundle.fir b/test/passes/lower-to-ground/bundle.fir index 06558e44..ccf942ee 100644 --- a/test/passes/lower-to-ground/bundle.fir +++ b/test/passes/lower-to-ground/bundle.fir @@ -8,10 +8,10 @@ circuit top : input c : { x : UInt<5>[5], flip y : { x : UInt<5>[3], flip y : SInt<5> } } wire a : { x : UInt<5>, flip y : SInt<5>} wire b : { x : UInt<5>, flip y : SInt<5>} - a := b + a <= b inst i of m - i.a := a - b := i.b + i.a <= a + b <= i.b wire d : UInt<5>[5] ;CHECK: Lower To Ground @@ -35,13 +35,13 @@ circuit top : ;CHECK: wire a{{[_$]+}}y : SInt<5> ;CHECK: wire b{{[_$]+}}x : UInt<5> ;CHECK: wire b{{[_$]+}}y : SInt<5> -;CHECK: a{{[_$]+}}x := b{{[_$]+}}x -;CHECK: b{{[_$]+}}y := a{{[_$]+}}y +;CHECK: a{{[_$]+}}x <= b{{[_$]+}}x +;CHECK: b{{[_$]+}}y <= a{{[_$]+}}y ;CHECK: inst i of m -;CHECK: i.a{{[_$]+}}x := a{{[_$]+}}x -;CHECK: a{{[_$]+}}y := i.a{{[_$]+}}y -;CHECK: b{{[_$]+}}x := i.b{{[_$]+}}x -;CHECK: i.b{{[_$]+}}y := b{{[_$]+}}y +;CHECK: i.a{{[_$]+}}x <= a{{[_$]+}}x +;CHECK: a{{[_$]+}}y <= i.a{{[_$]+}}y +;CHECK: b{{[_$]+}}x <= i.b{{[_$]+}}x +;CHECK: i.b{{[_$]+}}y <= b{{[_$]+}}y ;CHECK: wire d{{[_$]+}}0 : UInt<5> ;CHECK: wire d{{[_$]+}}1 : UInt<5> ;CHECK: wire d{{[_$]+}}2 : UInt<5> diff --git a/test/passes/lower-to-ground/instance.fir b/test/passes/lower-to-ground/instance.fir index 8d6beb93..ecc2d40b 100644 --- a/test/passes/lower-to-ground/instance.fir +++ b/test/passes/lower-to-ground/instance.fir @@ -4,7 +4,7 @@ circuit top : module source : output data : UInt<16> input ready : UInt<1> - data := UInt(16) + data <= UInt(16) module sink : input data : UInt<16> output ready : UInt<1> @@ -13,23 +13,23 @@ circuit top : wire connect2 : { flip data : UInt<16>, ready: UInt<1> } inst src of source inst snk of sink - connect := src - connect2 := snk + connect <= src + connect2 <= snk ; CHECK: Resolve Genders -; CHECK: connect@<g:f> := src@<g:m> -; CHECK: connect2@<g:f> := snk@<g:m> +; CHECK: connect@<g:f> <= src@<g:m> +; CHECK: connect2@<g:f> <= snk@<g:m> ; CHECK: Finished Resolve Genders ; CHECK: Lower To Ground -; CHECK: connect{{[_$]+}}data@<g:f> := src@<g:m>.data@<g:m> -; CHECK: src@<g:m>.ready@<g:f> := connect{{[_$]+}}ready@<g:m> -; CHECK: snk@<g:m>.data@<g:f> := connect2{{[_$]+}}data@<g:m> -; CHECK: connect2{{[_$]+}}ready@<g:f> := snk@<g:m>.ready@<g:m> +; CHECK: connect{{[_$]+}}data@<g:f> <= src@<g:m>.data@<g:m> +; CHECK: src@<g:m>.ready@<g:f> <= connect{{[_$]+}}ready@<g:m> +; CHECK: snk@<g:m>.data@<g:f> <= connect2{{[_$]+}}data@<g:m> +; CHECK: connect2{{[_$]+}}ready@<g:f> <= snk@<g:m>.ready@<g:m> ; CHECK: Finished Lower To Ground diff --git a/test/passes/lower-to-ground/nested-vec.fir b/test/passes/lower-to-ground/nested-vec.fir index aa208b01..0c58f267 100644 --- a/test/passes/lower-to-ground/nested-vec.fir +++ b/test/passes/lower-to-ground/nested-vec.fir @@ -17,7 +17,7 @@ circuit top : infer accessor b = a[i] ; CHECK: indexer b{{[_$]+}}x = (a{{[_$]+}}0{{[_$]+}}x a{{[_$]+}}1{{[_$]+}}x)[i] : UInt<32> ; CHECK: indexer (a{{[_$]+}}0{{[_$]+}}y a{{[_$]+}}1{{[_$]+}}y)[i] = b{{[_$]+}}y : UInt<32> - j := b + j <= b cmem m : { x : UInt<32>, y : UInt<32> }[2],clk ; CHECK: cmem m{{[_$]+}}x : UInt<32>[2] @@ -27,9 +27,9 @@ circuit top : ; CHECK: accessor c{{[_$]+}}x = m{{[_$]+}}x[i] ; CHECK: accessor c{{[_$]+}}y = m{{[_$]+}}y[i] - c := k - ; CHECK: c{{[_$]+}}x := k{{[_$]+}}x - ; CHECK: c{{[_$]+}}y := k{{[_$]+}}y + c <= k + ; CHECK: c{{[_$]+}}x <= k{{[_$]+}}x + ; CHECK: c{{[_$]+}}y <= k{{[_$]+}}y ; CHECK: Finished Lower To Ground diff --git a/test/passes/lower-to-ground/register.fir b/test/passes/lower-to-ground/register.fir index 75b4fe88..99f63153 100644 --- a/test/passes/lower-to-ground/register.fir +++ b/test/passes/lower-to-ground/register.fir @@ -11,13 +11,13 @@ reg r1 : { x : UInt, y : SInt },clk,reset wire q : { x : UInt, y : SInt } - onreset r1 := q + onreset r1 <= q ; CHECK: reg r1{{[_$]+}}x : UInt ; CHECK: reg r1{{[_$]+}}y : SInt ; CHECK: wire q{{[_$]+}}x : UInt ; CHECK: wire q{{[_$]+}}y : SInt - ; CHECK: onreset r1{{[_$]+}}x := q{{[_$]+}}x - ; CHECK: onreset r1{{[_$]+}}y := q{{[_$]+}}y + ; CHECK: onreset r1{{[_$]+}}x <= q{{[_$]+}}x + ; CHECK: onreset r1{{[_$]+}}y <= q{{[_$]+}}y ; CHECK: Finished Lower To Ground diff --git a/test/passes/lower-to-ground/test.fir b/test/passes/lower-to-ground/test.fir index db78da84..4cf61462 100644 --- a/test/passes/lower-to-ground/test.fir +++ b/test/passes/lower-to-ground/test.fir @@ -4,13 +4,13 @@ circuit Top : module Queue : output out : {valid : UInt<1>, flip ready : UInt<1>} - out.valid := UInt(1) + out.valid <= UInt(1) module Top : output this : {out : {valid : UInt<1>, flip ready : UInt<1>}} inst queue of Queue - this.out := queue.out + this.out <= queue.out wire w : { x : UInt<5>, flip y : UInt<5>} - w.x := UInt(1) + w.x <= UInt(1) wire a : UInt<5> - a := UInt(1) - w.y := a + a <= UInt(1) + w.y <= a diff --git a/test/passes/resolve-genders/accessor.fir b/test/passes/resolve-genders/accessor.fir index 4d816238..64797ece 100644 --- a/test/passes/resolve-genders/accessor.fir +++ b/test/passes/resolve-genders/accessor.fir @@ -4,31 +4,31 @@ circuit top : module top : wire m : UInt<32>[2][2][2] - m[0][0][0] := UInt(1) - m[1][0][0] := UInt(1) - m[0][1][0] := UInt(1) - m[1][1][0] := UInt(1) - m[0][0][1] := UInt(1) - m[1][0][1] := UInt(1) - m[0][1][1] := UInt(1) - m[1][1][1] := UInt(1) + m[0][0][0] <= UInt(1) + m[1][0][0] <= UInt(1) + m[0][1][0] <= UInt(1) + m[1][1][0] <= UInt(1) + m[0][0][1] <= UInt(1) + m[1][0][1] <= UInt(1) + m[0][1][1] <= UInt(1) + m[1][1][1] <= UInt(1) wire i : UInt - i := UInt(1) + i <= UInt(1) infer accessor a = m[i] ;CHECK: accessor a = m@<g:m>[i@<g:m>]@<g:m> infer accessor b = a[i] ;CHECK: accessor b = a@<g:m>[i@<g:m>]@<g:m> infer accessor c = b[i] ;CHECK: accessor c = b@<g:m>[i@<g:m>]@<g:m> wire j : UInt - j := c + j <= c infer accessor x = m[i] ;CHECK: accessor x = m@<g:f>[i@<g:m>]@<g:f> - x[0][0] := UInt(1) - x[1][0] := UInt(1) - x[0][1] := UInt(1) - x[1][1] := UInt(1) + x[0][0] <= UInt(1) + x[1][0] <= UInt(1) + x[0][1] <= UInt(1) + x[1][1] <= UInt(1) infer accessor y = x[i] ;CHECK: accessor y = x@<g:f>[i@<g:m>]@<g:f> - y[0] := UInt(1) - y[1] := UInt(1) + y[0] <= UInt(1) + y[1] <= UInt(1) infer accessor z = y[i] ;CHECK: accessor z = y@<g:f>[i@<g:m>]@<g:f> - z := j + z <= j ; CHECK: Finished Resolve Genders diff --git a/test/passes/resolve-genders/bigenders.fir b/test/passes/resolve-genders/bigenders.fir index 7bdd707c..a13390f7 100644 --- a/test/passes/resolve-genders/bigenders.fir +++ b/test/passes/resolve-genders/bigenders.fir @@ -6,8 +6,8 @@ circuit top : input i : UInt<10> output o : UInt<10> wire w : {x : UInt<10>, flip y : UInt<10>} - w.x := i - w.y := i - o := w.x - o := w.y + w.x <= i + w.y <= i + o <= w.x + o <= w.y ; CHECK: Finished Resolve Genders diff --git a/test/passes/resolve-genders/bulk.fir b/test/passes/resolve-genders/bulk.fir index 193758ec..7e746a37 100644 --- a/test/passes/resolve-genders/bulk.fir +++ b/test/passes/resolve-genders/bulk.fir @@ -9,6 +9,6 @@ circuit top : module top : inst src of source inst snk of sink - snk.bundle := src.bundle + snk.bundle <= src.bundle ; CHECK: Finished Resolve Genders diff --git a/test/passes/resolve-genders/gcd.fir b/test/passes/resolve-genders/gcd.fir index 70556474..85b6474b 100644 --- a/test/passes/resolve-genders/gcd.fir +++ b/test/passes/resolve-genders/gcd.fir @@ -6,8 +6,8 @@ circuit top : input x : UInt input y : UInt output z : UInt - z := subw(x, y) - ;CHECK: z@<g:f> := subw(x@<g:m>, y@<g:m>) + z <= subw(x, y) + ;CHECK: z@<g:f> <= subw(x@<g:m>, y@<g:m>) module gcd : input a : UInt<16> input b : UInt<16> @@ -19,28 +19,28 @@ circuit top : reg x : UInt,clk,reset reg y : UInt,clk,reset ; CHECK: reg x : UInt - onreset x := UInt(0) - onreset y := UInt(42) + onreset x <= UInt(0) + onreset y <= UInt(42) when gt(x, y) : ;CHECK: when gt(x@<g:m>, y@<g:m>) : inst s of subtracter ;CHECK: inst s of subtracter@<g:m> - s.x := x - s.y := y - x := s.z - ;CHECK: s@<g:m>.x@<g:f> := x@<g:m> - ;CHECK: s@<g:m>.y@<g:f> := y@<g:m> - ;CHECK: x@<g:f> := s@<g:m>.z@<g:m> + s.x <= x + s.y <= y + x <= s.z + ;CHECK: s@<g:m>.x@<g:f> <= x@<g:m> + ;CHECK: s@<g:m>.y@<g:f> <= y@<g:m> + ;CHECK: x@<g:f> <= s@<g:m>.z@<g:m> else : inst s2 of subtracter - s2.x := x - s2.y := y - y := s2.z + s2.x <= x + s2.y <= y + y <= s2.z when e : - x := a - y := b - v := eq(v, UInt(0)) - z := x + x <= a + y <= b + v <= eq(v, UInt(0)) + z <= x module top : input clk : Clock input reset : UInt<1> @@ -48,11 +48,11 @@ circuit top : input b : UInt<16> output z : UInt inst i of gcd - i.a := a - i.b := b - i.clk := clk - i.reset := reset - i.e := UInt(1) - z := i.z + i.a <= a + i.b <= b + i.clk <= clk + i.reset <= reset + i.e <= UInt(1) + z <= i.z ; CHECK: Finished Resolve Genders diff --git a/test/passes/resolve-genders/ports.fir b/test/passes/resolve-genders/ports.fir index 88eb1000..57c8721d 100644 --- a/test/passes/resolve-genders/ports.fir +++ b/test/passes/resolve-genders/ports.fir @@ -5,7 +5,7 @@ circuit top : module source : output data : UInt<16> input ready : UInt<1> - data := UInt(16) + data <= UInt(16) module sink : input data : UInt<16> output ready : UInt<1> @@ -13,9 +13,9 @@ circuit top : wire connect : { data : UInt<16>, flip ready: UInt<1> } inst src of source ;CHECK: inst src of source@<g:m> inst snk of sink ;CHECK: inst snk of sink@<g:m> - connect.data := src.data ;CHECK: connect@<g:f>.data@<g:f> := src@<g:m>.data@<g:m> - src.ready := connect.ready ;CHECK: src@<g:m>.ready@<g:f> := connect@<g:f>.ready@<g:m> - snk.data := connect.data ;CHECK: snk@<g:m>.data@<g:f> := connect@<g:m>.data@<g:m> - connect.ready := snk.ready ;CHECK: connect@<g:m>.ready@<g:f> := snk@<g:m>.ready@<g:m> + connect.data <= src.data ;CHECK: connect@<g:f>.data@<g:f> := src@<g:m>.data@<g:m> + src.ready <= connect.ready ;CHECK: src@<g:m>.ready@<g:f> := connect@<g:f>.ready@<g:m> + snk.data <= connect.data ;CHECK: snk@<g:m>.data@<g:f> := connect@<g:m>.data@<g:m> + connect.ready <= snk.ready ;CHECK: connect@<g:m>.ready@<g:f> := snk@<g:m>.ready@<g:m> ; CHECK: Finished Resolve Genders diff --git a/test/passes/resolve-genders/rdwraccessor.fir b/test/passes/resolve-genders/rdwraccessor.fir index 238cfa80..35f88071 100644 --- a/test/passes/resolve-genders/rdwraccessor.fir +++ b/test/passes/resolve-genders/rdwraccessor.fir @@ -4,28 +4,28 @@ circuit top : module top : wire m : UInt<32>[2][2][2] - m[0][0][0] := UInt(1) - m[1][0][0] := UInt(1) - m[0][1][0] := UInt(1) - m[1][1][0] := UInt(1) - m[0][0][1] := UInt(1) - m[1][0][1] := UInt(1) - m[0][1][1] := UInt(1) - m[1][1][1] := UInt(1) + m[0][0][0] <= UInt(1) + m[1][0][0] <= UInt(1) + m[0][1][0] <= UInt(1) + m[1][1][0] <= UInt(1) + m[0][0][1] <= UInt(1) + m[1][0][1] <= UInt(1) + m[0][1][1] <= UInt(1) + m[1][1][1] <= UInt(1) wire i : UInt - i := UInt(1) + i <= UInt(1) rdwr accessor a = m[i] ;CHECK: accessor a = m@<g:b>[i@<g:m>]@<g:b> rdwr accessor b = a[i] ;CHECK: accessor b = a@<g:b>[i@<g:m>]@<g:b> rdwr accessor c = b[i] ;CHECK: accessor c = b@<g:b>[i@<g:m>]@<g:b> wire j : UInt - j := c - c := j + j <= c + c <= j rdwr accessor x = m[i] ;CHECK: accessor x = m@<g:b>[i@<g:m>]@<g:b> rdwr accessor y = x[i] ;CHECK: accessor y = x@<g:b>[i@<g:m>]@<g:b> rdwr accessor z = y[i] ;CHECK: accessor z = y@<g:b>[i@<g:m>]@<g:b> - z := j - j := z + z <= j + j <= z ; CHECK: Finished Resolve Genders ; CHECK: Done! diff --git a/test/passes/resolve-genders/subbundle.fir b/test/passes/resolve-genders/subbundle.fir index 9df4b058..f734d08b 100644 --- a/test/passes/resolve-genders/subbundle.fir +++ b/test/passes/resolve-genders/subbundle.fir @@ -7,7 +7,7 @@ circuit top : input reset : UInt<1> wire w : { flip x : UInt<10>} reg r : { flip x : UInt<10>},clk,reset - w := r ; CHECK r$x := w$x - w.x := r.x ; CHECK w$x := r$x + w <= r ; CHECK r$x := w$x + w.x <= r.x ; CHECK w$x := r$x ; CHECK: Finished Lower To Ground diff --git a/test/passes/resolve-kinds/gcd.fir b/test/passes/resolve-kinds/gcd.fir index 2f8deb4e..3583c81a 100644 --- a/test/passes/resolve-kinds/gcd.fir +++ b/test/passes/resolve-kinds/gcd.fir @@ -6,8 +6,8 @@ circuit top : input x : UInt input y : UInt output z : UInt - z := subw(x, y) - ;CHECK: z@<k:port> := subw(x@<k:port>, y@<k:port>) + z <= subw(x, y) + ;CHECK: z@<k:port> <= subw(x@<k:port>, y@<k:port>) module gcd : input clk : Clock input reset : UInt<1> @@ -18,24 +18,24 @@ circuit top : output v : UInt<1> reg x : UInt,clk,reset reg y : UInt,clk,reset - onreset x := UInt(0) - onreset y := UInt(42) + onreset x <= UInt(0) + onreset y <= UInt(42) when gt(x, y) : inst s of subtracter - s.x := x - ;CHECK: s@<k:inst>.x := x@<k:reg> - s.y := y - x := s.z + s.x <= x + ;CHECK: s@<k:inst>.x <= x@<k:reg> + s.y <= y + x <= s.z else : inst s2 of subtracter - s2.x := x - s2.y := y - y := s2.z + s2.x <= x + s2.y <= y + y <= s2.z when e : - x := a - y := b - v := eq(v, UInt(0)) - z := x + x <= a + y <= b + v <= eq(v, UInt(0)) + z <= x module top : input a : UInt<16> input b : UInt<16> @@ -44,13 +44,13 @@ circuit top : output z : UInt inst i of gcd ;CHECK: inst i of gcd@<k:module> - i.a := a - i.b := b - i.clk := clk - i.reset := reset - i.e := UInt(1) - z := i.z - ;CHECK: z@<k:port> := i@<k:inst>.z + i.a <= a + i.b <= b + i.clk <= clk + i.reset <= reset + i.e <= UInt(1) + z <= i.z + ;CHECK: z@<k:port> <= i@<k:inst>.z ; CHECK: Finished Resolve Kinds diff --git a/test/passes/split-exp/gcd.fir b/test/passes/split-exp/gcd.fir index 0317d634..1f032c04 100644 --- a/test/passes/split-exp/gcd.fir +++ b/test/passes/split-exp/gcd.fir @@ -6,7 +6,7 @@ circuit top : input x : UInt input y : UInt output q : UInt - q := subw(x, y) + q <= subw(x, y) module gcd : input clk : Clock input reset : UInt<1> @@ -16,22 +16,22 @@ circuit top : output z : UInt<16> reg x : UInt,clk,reset reg y : UInt,clk,reset - onreset x := UInt(0) - onreset y := UInt(42) + onreset x <= UInt(0) + onreset y <= UInt(42) when gt(x, y) : inst s of subtracter - s.x := x - s.y := y - x := s.q + s.x <= x + s.y <= y + x <= s.q else : inst s2 of subtracter - s2.x := x - s2.y := y - y := s2.q + s2.x <= x + s2.y <= y + y <= s2.q when e : - x := a - y := b - z := x + x <= a + y <= b + z <= x module top : input clk : Clock input reset : UInt<1> @@ -39,11 +39,11 @@ circuit top : input b : UInt<16> output z : UInt inst i of gcd - i.clk := clk - i.reset := reset - i.a := a - i.b := b - i.e := UInt(1) - z := i.z + i.clk <= clk + i.reset <= reset + i.a <= a + i.b <= b + i.e <= UInt(1) + z <= i.z ; CHECK: Finished Split Expressions diff --git a/test/passes/split-exp/primop.fir b/test/passes/split-exp/primop.fir index b2f0af82..caccf57b 100644 --- a/test/passes/split-exp/primop.fir +++ b/test/passes/split-exp/primop.fir @@ -6,15 +6,15 @@ circuit Top : output out : UInt<1> wire m : UInt<1>[3] - m[0] := UInt(0) - m[1] := UInt(0) - m[2] := UInt(0) + m[0] <= UInt(0) + m[1] <= UInt(0) + m[2] <= UInt(0) wire x : UInt<1> - x := not(UInt(1)) + x <= not(UInt(1)) infer accessor a = m[x] - out := a + out <= a diff --git a/test/passes/split-exp/split-in-when.fir b/test/passes/split-exp/split-in-when.fir index 58819d22..b72a1d95 100644 --- a/test/passes/split-exp/split-in-when.fir +++ b/test/passes/split-exp/split-in-when.fir @@ -11,13 +11,13 @@ circuit Top : reg out : UInt<10>,clk,p - when bit(subw(a,c),3) : out := mux(eqv(bits(UInt(32),4,0),UInt(13)),addw(a,addw(b,c)),subw(c,b)) + when bit(subw(a,c),3) : out <= mux(eqv(bits(UInt(32),4,0),UInt(13)),addw(a,addw(b,c)),subw(c,b)) ;CHECK: node F = subw(a, c) ;CHECK: node out_1 = eqv(UInt("h0"), UInt("hd")) ;CHECK: node out_3 = addw(b, c) ;CHECK: node out_2 = addw(a, out_3) ;CHECK: node out_4 = subw(c, b) -;CHECK: when bit(F, 3) : out := mux(out_1, out_2, out_4) +;CHECK: when bit(F, 3) : out <= mux(out_1, out_2, out_4) ;CHECK: Finished Split Expressions diff --git a/test/passes/to-flo/gcd.fir b/test/passes/to-flo/gcd.fir index 7e156e34..680c2a9a 100644 --- a/test/passes/to-flo/gcd.fir +++ b/test/passes/to-flo/gcd.fir @@ -7,7 +7,7 @@ circuit top : input x : UInt input y : UInt output q : UInt - q := subw(x, y) + q <= subw(x, y) module gcd : input clk : Clock input reset : UInt<1> @@ -17,22 +17,22 @@ circuit top : output z : UInt<16> reg x : UInt,clk,reset reg y : UInt,clk,reset - onreset x := UInt(0) - onreset y := UInt(42) + onreset x <= UInt(0) + onreset y <= UInt(42) when gt(x, y) : inst s of subtracter - s.x := x - s.y := y - x := s.q + s.x <= x + s.y <= y + x <= s.q else : inst s2 of subtracter - s2.x := x - s2.y := y - y := s2.q + s2.x <= x + s2.y <= y + y <= s2.q when e : - x := a - y := b - z := x + x <= a + y <= b + z <= x module top : input a : UInt<16> input b : UInt<16> @@ -40,11 +40,11 @@ circuit top : input reset : UInt<1> output z : UInt inst i of gcd - i.clk := clk - i.reset := reset - i.a := a - i.b := b - i.e := UInt(1) - z := i.z + i.clk <= clk + i.reset <= reset + i.a <= a + i.b <= b + i.e <= UInt(1) + z <= i.z ;CHECK: Done! |