blob: a13390f771e3528b748bc7452ddcfdb2a17541ca (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
|
; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
;CHECK: Resolve Genders
circuit top :
module top :
input i : UInt<10>
output o : UInt<10>
wire w : {x : UInt<10>, flip y : UInt<10>}
w.x <= i
w.y <= i
o <= w.x
o <= w.y
; CHECK: Finished Resolve Genders
|
