WIP. Compiles and almost done with verilog backend. Need to think about emitting ports (and the assignments to them)

7 files changed, 33 insertions, 29 deletions

diff --git a/test/errors/high-form/Flip-Mem.fir b/test/errors/high-form/Flip-Mem.fir
index 38935b57..ebc3ddbf 100644
--- a/test/errors/high-form/Flip-Mem.fir
+++ b/test/errors/high-form/Flip-Mem.fir
@@ -5,5 +5,9 @@
 circuit Flip-Mem : 
   module Flip-Mem : 
     input clk : Clock
-    cmem mc : {x : UInt<3>, flip y : UInt<5>}[10], clk
-    smem ms : {x : UInt<3>, flip y : UInt<5>}[10], clk
+    mem mc : 
+       depth => 10
+       data-type => {x : UInt<3>, flip y : UInt<5>}
+       write-latency => 1
+       read-latency => 0
+    ;smem ms : {x : UInt<3>, flip y : UInt<5>}[10], clk
diff --git a/test/passes/to-verilog/gcd.fir b/test/passes/to-verilog/gcd.fir
index c79cc92e..cadd9ec8 100644
--- a/test/passes/to-verilog/gcd.fir
+++ b/test/passes/to-verilog/gcd.fir
@@ -6,7 +6,7 @@ circuit top :
       input x : UInt
       input y : UInt
       output q : UInt
-      q := subw(x, y)
+      q <= subw(x, y)
    module gcd :
       input clk : Clock
       input reset : UInt<1>
@@ -18,18 +18,18 @@ circuit top :
       reg y : UInt,clk,reset,UInt(42)
       when gt(x, y) :
          inst s of subtracter
-         s.x := x
-         s.y := y
-         x := s.q
+         s.x <= x
+         s.y <= y
+         x <= s.q
       else :
          inst s2 of subtracter
-         s2.x := x
-         s2.y := y
-         y := s2.q
+         s2.x <= x
+         s2.y <= y
+         y <= s2.q
       when e :
-         x := a
-         y := b
-      z := x
+         x <= a
+         y <= b
+      z <= x
    module top :
       input a : UInt<16>
       input b : UInt<16>
@@ -37,12 +37,12 @@ circuit top :
       input reset : UInt<1>
       output z : UInt
       inst i of gcd
-      i.clk := clk
-      i.reset := reset
-      i.a := a
-      i.b := b
-      i.e := UInt(1)
-      z := i.z
+      i.clk <= clk
+      i.reset <= reset
+      i.a <= a
+      i.b <= b
+      i.e <= UInt(1)
+      z <= i.z
 
 
 
diff --git a/test/passes/to-verilog/mem.fir b/test/passes/to-verilog/mem.fir
index 0d0e0e5f..5d1c60f0 100644
--- a/test/passes/to-verilog/mem.fir
+++ b/test/passes/to-verilog/mem.fir
@@ -7,6 +7,6 @@ circuit top :
       output read : UInt<30>
       cmem m : UInt<30>[128], clk
       read accessor x = m[UInt(0)]
-      read := x
+      read <= x
       
 
diff --git a/test/passes/to-verilog/rd-mem.fir b/test/passes/to-verilog/rd-mem.fir
index c21cd1c6..0bb86851 100644
--- a/test/passes/to-verilog/rd-mem.fir
+++ b/test/passes/to-verilog/rd-mem.fir
@@ -9,9 +9,9 @@ circuit top :
 
       smem m : UInt<32>[4],clk
       read accessor c = m[index] 
-      rdata := UInt(0)
+      rdata <= UInt(0)
       when ren :
-         rdata := c
+         rdata <= c
 
 : CHECK: module top(
 : CHECK:     output [31:0] rdata,
diff --git a/test/passes/to-verilog/rdwr-mem.fir b/test/passes/to-verilog/rdwr-mem.fir
index 667d831f..d056ecf6 100644
--- a/test/passes/to-verilog/rdwr-mem.fir
+++ b/test/passes/to-verilog/rdwr-mem.fir
@@ -12,9 +12,9 @@ circuit top :
       smem m : UInt<32>[4],clk
       rdwr accessor c = m[index] 
       when ren :
-         rdata := c
+         rdata <= c
       when wen :
-         c := wdata
+         c <= wdata
 
 
 ; CHECK: module top(
diff --git a/test/passes/to-verilog/shr.fir b/test/passes/to-verilog/shr.fir
index c4b4e4d2..1b8db9e0 100644
--- a/test/passes/to-verilog/shr.fir
+++ b/test/passes/to-verilog/shr.fir
@@ -7,7 +7,7 @@
 circuit HellaCache : 
   module TLB_60 : 
     output resp : {ppn : UInt<20>}
-    resp.ppn := UInt<1>("h00")
+    resp.ppn <= UInt<1>("h00")
 
   module HellaCache : 
     input clock : Clock
@@ -21,10 +21,10 @@ circuit HellaCache :
     node T_928 = bits(s1_req.addr, 11, 0)
     node s1_addr = cat(dtlb.resp.ppn, T_928)
     when s1_clk_en :
-      s2_req.addr := s1_addr
+      s2_req.addr <= s1_addr
 
-    s1_req.addr := UInt<?>(0)
-    s1_clk_en := UInt<?>(0)
+    s1_req.addr <= UInt<?>(0)
+    s1_clk_en <= UInt<?>(0)
 
     wire foo : UInt<28>
-    foo := shr(s1_addr, 3)
+    foo <= shr(s1_addr, 3)
diff --git a/test/passes/to-verilog/wr-mem.fir b/test/passes/to-verilog/wr-mem.fir
index 7641e894..b21491aa 100644
--- a/test/passes/to-verilog/wr-mem.fir
+++ b/test/passes/to-verilog/wr-mem.fir
@@ -10,7 +10,7 @@ circuit top :
       smem m : UInt<32>[4],clk
       write accessor c = m[index] 
       when wen :
-         c := wdata
+         c <= wdata
 
 ; CHECK: module top(
 ; CHECK:     input  [31:0] wdata,