WIP need to correctly output readwrite ports

11 files changed, 187 insertions, 31 deletions

diff --git a/test/passes/inline-indexers/bundle-vecs.fir b/test/passes/inline-indexers/bundle-vecs.fir
index 28826056..f4fc609d 100644
--- a/test/passes/inline-indexers/bundle-vecs.fir
+++ b/test/passes/inline-indexers/bundle-vecs.fir
@@ -20,14 +20,14 @@ circuit top :
 
 
       infer accessor b = a[i]
-      ; CHECK: wire b{{[_$]+}}x_1 : UInt<32>
+      ; CHECK: wire b{{[_$]+}}x_2 : UInt<32>
       ; CHECK: node i_1 = i
-      ; CHECK: b{{[_$]+}}x_1 := a{{[_$]+}}0{{[_$]+}}x
-      ; CHECK: when eqv(i_1, UInt("h1")) : b{{[_$]+}}x_1 := a{{[_$]+}}1{{[_$]+}}x      
-      ; CHECK: wire b{{[_$]+}}y_1 : UInt<32>
+      ; CHECK: b{{[_$]+}}x_2 := a{{[_$]+}}0{{[_$]+}}x
+      ; CHECK: when eqv(i_1, UInt("h1")) : b{{[_$]+}}x_2 := a{{[_$]+}}1{{[_$]+}}x      
+      ; CHECK: wire b{{[_$]+}}y_2 : UInt<32>
       ; CHECK: node i_2 = i
-      ; CHECK: when eqv(i_2, UInt("h0")) : a{{[_$]+}}0{{[_$]+}}y := b{{[_$]+}}y_1
-      ; CHECK: when eqv(i_2, UInt("h1")) : a{{[_$]+}}1{{[_$]+}}y := b{{[_$]+}}y_1
+      ; CHECK: when eqv(i_2, UInt("h0")) : a{{[_$]+}}0{{[_$]+}}y := b{{[_$]+}}y_2
+      ; CHECK: when eqv(i_2, UInt("h1")) : a{{[_$]+}}1{{[_$]+}}y := b{{[_$]+}}y_2
       j := b.x
       b.y := UInt(1)
       
diff --git a/test/passes/inline-indexers/simple.fir b/test/passes/inline-indexers/simple.fir
index ca186e97..095094d3 100644
--- a/test/passes/inline-indexers/simple.fir
+++ b/test/passes/inline-indexers/simple.fir
@@ -12,8 +12,8 @@ circuit top :
       infer accessor a = m[i] 
       o := a
 
-;CHECK: a_1 := m$0
-;CHECK: when eqv(i_1, UInt("h1")) : a_1 := m$1
+;CHECK: a_2 := m$0
+;CHECK: when eqv(i_1, UInt("h1")) : a_2 := m$1
 
 
 
diff --git a/test/passes/inline-indexers/simple2.fir b/test/passes/inline-indexers/simple2.fir
index 3b7d92af..13fc4416 100644
--- a/test/passes/inline-indexers/simple2.fir
+++ b/test/passes/inline-indexers/simple2.fir
@@ -14,12 +14,12 @@ circuit top :
       o1 := a
       o2 := a
 
-;CHECK: wire a_1 : UInt<32>
-;CHECK: a_1 := m$0
-;CHECK: when eqv(i_1, UInt("h1")) : a_1 := m$1
 ;CHECK: wire a_2 : UInt<32>
 ;CHECK: a_2 := m$0
-;CHECK: when eqv(i_2, UInt("h1")) : a_2 := m$1
+;CHECK: when eqv(i_1, UInt("h1")) : a_2 := m$1
+;CHECK: wire a_3 : UInt<32>
+;CHECK: a_3 := m$0
+;CHECK: when eqv(i_2, UInt("h1")) : a_3 := m$1
 
 
 
diff --git a/test/passes/inline-indexers/simple3.fir b/test/passes/inline-indexers/simple3.fir
index 688958a0..b6a7616c 100644
--- a/test/passes/inline-indexers/simple3.fir
+++ b/test/passes/inline-indexers/simple3.fir
@@ -11,9 +11,9 @@ circuit top :
       infer accessor a = m[i] 
       a := in
 
-;CHECK: wire a_1 : UInt<32>
-;CHECK: when eqv(i_1, UInt("h0")) : m$0 := a_1
-;CHECK: when eqv(i_1, UInt("h1")) : m$1 := a_1
+;CHECK: wire a_2 : UInt<32>
+;CHECK: when eqv(i_1, UInt("h0")) : m$0 := a_2
+;CHECK: when eqv(i_1, UInt("h1")) : m$1 := a_2
 
 
 
diff --git a/test/passes/inline-indexers/simple4.fir b/test/passes/inline-indexers/simple4.fir
index df045456..129de4de 100644
--- a/test/passes/inline-indexers/simple4.fir
+++ b/test/passes/inline-indexers/simple4.fir
@@ -13,11 +13,11 @@ circuit top :
       infer accessor a = m[i] 
       a.x := in.x
 
-;CHECK: wire a$x_1 : UInt<32>
+;CHECK: wire a$x_2 : UInt<32>
 ;CHECK: node i_1 = i
-;CHECK: when eqv(i_1, UInt("h0")) : m$0$x := a$x_1
-;CHECK: when eqv(i_1, UInt("h1")) : m$1$x := a$x_1
-;CHECK: a$x_1 := in$x
+;CHECK: when eqv(i_1, UInt("h0")) : m$0$x := a$x_2
+;CHECK: when eqv(i_1, UInt("h1")) : m$1$x := a$x_2
+;CHECK: a$x_2 := in$x
 ;CHECK: Finished Inline Indexers
 ;CHECK: Done!
 
diff --git a/test/passes/inline-indexers/simple5.fir b/test/passes/inline-indexers/simple5.fir
index 1da83cab..3affa941 100644
--- a/test/passes/inline-indexers/simple5.fir
+++ b/test/passes/inline-indexers/simple5.fir
@@ -15,7 +15,7 @@ circuit top :
          o := a
 
 ;CHECK: when i :
-;CHECK: a_1 := m$0
-;CHECK: when eqv(i_1, UInt("h1")) : a_1 := m$1
+;CHECK: a_2 := m$0
+;CHECK: when eqv(i_1, UInt("h1")) : a_2 := m$1
 ;CHECK: Finished Inline Indexers
 ;CHECK: Done!
diff --git a/test/passes/inline-indexers/simple6.fir b/test/passes/inline-indexers/simple6.fir
index e94efc7a..b177fba2 100644
--- a/test/passes/inline-indexers/simple6.fir
+++ b/test/passes/inline-indexers/simple6.fir
@@ -20,25 +20,25 @@ circuit top :
       write accessor b = a[j] 
       b.x := value
 
-;CHECK: wire b$x_1 : UInt<32>
+;CHECK: wire b$x_2 : UInt<32>
 ;CHECK: node j_1 = j
 ;CHECK: when eqv(j_1, UInt("h0")) :
-;CHECK:    wire a$0$x_1 : UInt<32>
+;CHECK:    wire a$0$x_2 : UInt<32>
 ;CHECK:    node i_1 = i
 ;CHECK:    when eqv(i_1, UInt("h0")) :
-;CHECK:       m$0$0$x := a$0$x_1         
+;CHECK:       m$0$0$x := a$0$x_2         
 ;CHECK:    when eqv(i_1, UInt("h1")) :
-;CHECK:       m$1$0$x := a$0$x_1         
-;CHECK:    a$0$x_1 := b$x_1      
+;CHECK:       m$1$0$x := a$0$x_2         
+;CHECK:    a$0$x_2 := b$x_2      
 ;CHECK: when eqv(j_1, UInt("h1")) :
-;CHECK:    wire a$1$x_1 : UInt<32>
+;CHECK:    wire a$1$x_2 : UInt<32>
 ;CHECK:    node i_2 = i
 ;CHECK:    when eqv(i_2, UInt("h0")) :
-;CHECK:       m$0$1$x := a$1$x_1         
+;CHECK:       m$0$1$x := a$1$x_2         
 ;CHECK:    when eqv(i_2, UInt("h1")) :
-;CHECK:       m$1$1$x := a$1$x_1         
-;CHECK:    a$1$x_1 := b$x_1      
-;CHECK: b$x_1 := value   
+;CHECK:       m$1$1$x := a$1$x_2         
+;CHECK:    a$1$x_2 := b$x_2      
+;CHECK: b$x_2 := value   
 
 
 
diff --git a/test/passes/resolve-genders/rdwraccessor.fir b/test/passes/resolve-genders/rdwraccessor.fir
new file mode 100644
index 00000000..238cfa80
--- /dev/null
+++ b/test/passes/resolve-genders/rdwraccessor.fir
@@ -0,0 +1,31 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p cg 2>&1 | tee %s.out | FileCheck %s
+
+;CHECK: Resolve Genders
+circuit top :
+   module top :
+      wire m : UInt<32>[2][2][2]
+      m[0][0][0] := UInt(1)
+      m[1][0][0] := UInt(1)
+      m[0][1][0] := UInt(1)
+      m[1][1][0] := UInt(1)
+      m[0][0][1] := UInt(1)
+      m[1][0][1] := UInt(1)
+      m[0][1][1] := UInt(1)
+      m[1][1][1] := UInt(1)
+      wire i : UInt
+      i := UInt(1)
+      rdwr accessor a = m[i] ;CHECK: accessor a = m@<g:b>[i@<g:m>]@<g:b>
+      rdwr accessor b = a[i] ;CHECK: accessor b = a@<g:b>[i@<g:m>]@<g:b>
+      rdwr accessor c = b[i] ;CHECK: accessor c = b@<g:b>[i@<g:m>]@<g:b>
+      wire j : UInt
+      j := c
+      c := j
+
+      rdwr accessor x = m[i] ;CHECK: accessor x = m@<g:b>[i@<g:m>]@<g:b>
+      rdwr accessor y = x[i] ;CHECK: accessor y = x@<g:b>[i@<g:m>]@<g:b>
+      rdwr accessor z = y[i] ;CHECK: accessor z = y@<g:b>[i@<g:m>]@<g:b>
+      z := j
+      j := z
+
+; CHECK: Finished Resolve Genders
+; CHECK: Done!
diff --git a/test/passes/to-verilog/rd-mem.fir b/test/passes/to-verilog/rd-mem.fir
new file mode 100644
index 00000000..c21cd1c6
--- /dev/null
+++ b/test/passes/to-verilog/rd-mem.fir
@@ -0,0 +1,42 @@
+; RUN: firrtl -i %s -o %s.v -X verilog &> %s.out ; cat %s.v | FileCheck %s
+
+circuit top :
+   module top :
+      output rdata : UInt<32>
+      input index : UInt<2>
+      input ren : UInt<1>
+      input clk : Clock
+
+      smem m : UInt<32>[4],clk
+      read accessor c = m[index] 
+      rdata := UInt(0)
+      when ren :
+         rdata := c
+
+: CHECK: module top(
+: CHECK:     output [31:0] rdata,
+: CHECK:     input  [1:0] index,
+: CHECK:     input  [0:0] ren,
+: CHECK:     input  [0:0] clk
+: CHECK: );
+: CHECK:   wire [31:0] c;
+: CHECK:   reg  [31:0] m [0:3];
+: CHECK:   reg  [1:0] index_1;
+: CHECK: `ifndef SYNTHESIS
+: CHECK:   integer initvar;
+: CHECK:   initial begin
+: CHECK:     #0.002;
+: CHECK:     for (initvar = 0; initvar < 4; initvar = initvar+1)
+: CHECK:       m[initvar] = {1{$random}};
+: CHECK:     index_1 = {1{$random}};
+: CHECK:   end
+: CHECK: `endif
+: CHECK:   assign c = m[index_1];
+: CHECK:   assign rdata = c;
+: CHECK:   always @(posedge clk) begin
+: CHECK:     if(ren) begin
+: CHECK:       index_1 <= index;
+: CHECK:     end
+: CHECK:   end
+: CHECK: endmodule
+: CHECK: 
diff --git a/test/passes/to-verilog/rdwr-mem.fir b/test/passes/to-verilog/rdwr-mem.fir
new file mode 100644
index 00000000..667d831f
--- /dev/null
+++ b/test/passes/to-verilog/rdwr-mem.fir
@@ -0,0 +1,47 @@
+; RUN: firrtl -i %s -o %s.v -X verilog &> %s.out ; cat %s.v | FileCheck %s
+
+circuit top :
+   module top :
+      output rdata : UInt<32>
+      input wdata : UInt<32>
+      input index : UInt<2>
+      input ren : UInt<1>
+      input wen : UInt<1>
+      input clk : Clock
+
+      smem m : UInt<32>[4],clk
+      rdwr accessor c = m[index] 
+      when ren :
+         rdata := c
+      when wen :
+         c := wdata
+
+
+; CHECK: module top(
+; CHECK:     output [31:0] rdata,
+; CHECK:     input  [1:0] index,
+; CHECK:     input  [0:0] ren,
+; CHECK:     input  [0:0] clk
+; CHECK: );
+; CHECK:   wire [31:0] c;
+; CHECK:   reg  [31:0] m [0:3];
+; CHECK:   reg  [1:0] index_1;
+; CHECK: `ifndef SYNTHESIS
+; CHECK:   integer initvar;
+; CHECK:   initial begin
+; CHECK:     #0.002;
+; CHECK:     for (initvar = 0; initvar < 4; initvar = initvar+1)
+; CHECK:       m[initvar] = {1{$random}};
+; CHECK:     index_1 = {1{$random}};
+; CHECK:   end
+; CHECK: `endif
+; CHECK:   assign rdata = m[index_1];
+; CHECK:   always @(posedge clk) begin
+; CHECK:     if(ren) begin
+; CHECK:       index_1 <= index;
+; CHECK:     end else if(wen) begin
+; CHECK:       m[index] <= wdata;
+; CHECK:     end
+; CHECK:   end
+; CHECK: endmodule
+
diff --git a/test/passes/to-verilog/wr-mem.fir b/test/passes/to-verilog/wr-mem.fir
new file mode 100644
index 00000000..7641e894
--- /dev/null
+++ b/test/passes/to-verilog/wr-mem.fir
@@ -0,0 +1,36 @@
+; RUN: firrtl -i %s -o %s.v -X verilog &> %s.out ; cat %s.v | FileCheck %s
+
+circuit top :
+   module top :
+      input wdata : UInt<32>
+      input index : UInt<2>
+      input wen : UInt<1>
+      input clk : Clock
+
+      smem m : UInt<32>[4],clk
+      write accessor c = m[index] 
+      when wen :
+         c := wdata
+
+; CHECK: module top(
+; CHECK:     input  [31:0] wdata,
+; CHECK:     input  [1:0] index,
+; CHECK:     input  [0:0] wen,
+; CHECK:     input  [0:0] clk
+; CHECK: );
+; CHECK:   reg  [31:0] m [0:3];
+; CHECK: `ifndef SYNTHESIS
+; CHECK:   integer initvar;
+; CHECK:   initial begin
+; CHECK:     #0.002;
+; CHECK:     for (initvar = 0; initvar < 4; initvar = initvar+1)
+; CHECK:       m[initvar] = {1{$random}};
+; CHECK:   end
+; CHECK: `endif
+; CHECK:   always @(posedge clk) begin
+; CHECK:     if(wen) begin
+; CHECK:       m[index] <= wdata;
+; CHECK:     end
+; CHECK:   end
+; CHECK: endmodule
+