diff options
| author | Andrew Waterman | 2015-10-01 15:24:06 -0700 |
|---|---|---|
| committer | Andrew Waterman | 2015-10-01 15:24:06 -0700 |
| commit | 0a9cc3d72fa2c6f19385efa8350f232e2e9faf10 (patch) | |
| tree | 362ab602a2d7d07e7ecfbf9570b03f0480ae4c2e /test | |
| parent | 42307c1f72c8799f8db52a6859c4b7b1ed114c3d (diff) | |
| parent | ded5cd987b8d275bbff3904903a37837a504098b (diff) | |
Merge pull request #43 from ucb-bar/new-semantics
Change of FIRRTL semantics!
Diffstat (limited to 'test')
| -rw-r--r-- | test/passes/expand-whens/reg-dwoc.fir | 2 | ||||
| -rw-r--r-- | test/passes/expand-whens/reg-wdc.fir | 6 | ||||
| -rw-r--r-- | test/passes/expand-whens/reg-wdoc.fir | 5 |
3 files changed, 6 insertions, 7 deletions
diff --git a/test/passes/expand-whens/reg-dwoc.fir b/test/passes/expand-whens/reg-dwoc.fir index c5ea4b41..60bd43a8 100644 --- a/test/passes/expand-whens/reg-dwoc.fir +++ b/test/passes/expand-whens/reg-dwoc.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.v -X verilog -p cd 2>&1 | tee %s.out | FileCheck %s circuit top : module top : input clk : Clock diff --git a/test/passes/expand-whens/reg-wdc.fir b/test/passes/expand-whens/reg-wdc.fir index a748dcc2..c6439860 100644 --- a/test/passes/expand-whens/reg-wdc.fir +++ b/test/passes/expand-whens/reg-wdc.fir @@ -1,5 +1,4 @@ ; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; XFAIL: * circuit top : module top : input clk : Clock @@ -16,8 +15,9 @@ circuit top : ; CHECK: module top : ; CHECK: wire p : UInt ; CHECK: reg r : UInt, clk, reset -; CHECK: p := UInt("h00000001") -; CHECK-NOT: when p : r := UInt("h00000002") +; CHECK: p := UInt("h1") +; CHECK-NOT: when p : r := UInt("h2") ; CHECK: Finished Expand Whens +; CHECK: Done! diff --git a/test/passes/expand-whens/reg-wdoc.fir b/test/passes/expand-whens/reg-wdoc.fir index 646397b8..de0bbfd6 100644 --- a/test/passes/expand-whens/reg-wdoc.fir +++ b/test/passes/expand-whens/reg-wdoc.fir @@ -1,5 +1,4 @@ ; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; XFAIL: * circuit top : module top : input clk : Clock @@ -17,8 +16,8 @@ circuit top : ; CHECK: module top : ; CHECK: wire p : UInt ; CHECK: reg r : UInt, clk, reset -; CHECK: p := UInt("h00000001") -; CHECK-NOT: when p : r := mux(reset, UInt("h00000001"), UInt("h00000002")) +; CHECK: p := UInt("h1") +; CHECK-NOT: when p : r := mux(reset, UInt("h1"), UInt("h2")) ; CHECK: Finished Expand Whens |