From ded5cd987b8d275bbff3904903a37837a504098b Mon Sep 17 00:00:00 2001
From: azidar
Date: Thu, 1 Oct 2015 09:56:11 -0700
Subject: Change of FIRRTL semantics!

Assignments to a register are no longer affected by enclosing when
statements:

when p :
  reg r : UInt,clk,reset
  r := a

will lower to:

reg r : UInt,clk,reset
r := a

instead of:

reg r : UInt,clk,reset
when p : r := a
---
 test/passes/expand-whens/reg-dwoc.fir | 2 +-
 test/passes/expand-whens/reg-wdc.fir  | 6 +++---
 test/passes/expand-whens/reg-wdoc.fir | 5 ++---
 3 files changed, 6 insertions(+), 7 deletions(-)

(limited to 'test')

diff --git a/test/passes/expand-whens/reg-dwoc.fir b/test/passes/expand-whens/reg-dwoc.fir
index c5ea4b41..60bd43a8 100644
--- a/test/passes/expand-whens/reg-dwoc.fir
+++ b/test/passes/expand-whens/reg-dwoc.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.v -X verilog -p cd 2>&1 | tee %s.out | FileCheck %s
 circuit top :
    module top :
       input clk : Clock
diff --git a/test/passes/expand-whens/reg-wdc.fir b/test/passes/expand-whens/reg-wdc.fir
index a748dcc2..c6439860 100644
--- a/test/passes/expand-whens/reg-wdc.fir
+++ b/test/passes/expand-whens/reg-wdc.fir
@@ -1,5 +1,4 @@
 ; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
-; XFAIL: *
 circuit top :
    module top :
       input clk : Clock
@@ -16,8 +15,9 @@ circuit top :
 ; CHECK:   module top :
 ; CHECK:     wire p : UInt
 ; CHECK:     reg r : UInt, clk, reset
-; CHECK:     p := UInt("h00000001")
-; CHECK-NOT: when p : r := UInt("h00000002")
+; CHECK:     p := UInt("h1")
+; CHECK-NOT: when p : r := UInt("h2")
 
 ; CHECK: Finished Expand Whens
 
+; CHECK: Done!
diff --git a/test/passes/expand-whens/reg-wdoc.fir b/test/passes/expand-whens/reg-wdoc.fir
index 646397b8..de0bbfd6 100644
--- a/test/passes/expand-whens/reg-wdoc.fir
+++ b/test/passes/expand-whens/reg-wdoc.fir
@@ -1,5 +1,4 @@
 ; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
-; XFAIL: *
 circuit top :
    module top :
       input clk : Clock
@@ -17,8 +16,8 @@ circuit top :
 ; CHECK:   module top :
 ; CHECK:     wire p : UInt
 ; CHECK:     reg r : UInt, clk, reset
-; CHECK:     p := UInt("h00000001")
-; CHECK-NOT:  when p : r := mux(reset, UInt("h00000001"), UInt("h00000002"))
+; CHECK:     p := UInt("h1")
+; CHECK-NOT:  when p : r := mux(reset, UInt("h1"), UInt("h2"))
 
 ; CHECK: Finished Expand Whens
 
-- 
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