diff options
| author | Andrew Waterman | 2015-10-01 15:15:09 -0700 |
|---|---|---|
| committer | Andrew Waterman | 2015-10-01 15:15:09 -0700 |
| commit | 42307c1f72c8799f8db52a6859c4b7b1ed114c3d (patch) | |
| tree | ffb6f0bc6f07b827b7f34814de232231bc82f968 /test | |
| parent | 8cbb0286f7b007fe54bf55452a25121357537dcb (diff) | |
| parent | 4726d8b6ca56435d861cb74f52f1237e3b43ae38 (diff) | |
Merge pull request #41 from ucb-bar/fix-init-accessor
Fix init accessor
Diffstat (limited to 'test')
23 files changed, 498 insertions, 44 deletions
diff --git a/test/errors/high-form/RemoveScope.fir b/test/errors/high-form/RemoveScope.fir index 395c6492..16498fd8 100644 --- a/test/errors/high-form/RemoveScope.fir +++ b/test/errors/high-form/RemoveScope.fir @@ -1,4 +1,5 @@ ; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s +; XFAIL: * ; CHECK: Done! circuit Top : diff --git a/test/errors/high-form/Unique.fir b/test/errors/high-form/Unique.fir index ea2bb881..60201b92 100644 --- a/test/errors/high-form/Unique.fir +++ b/test/errors/high-form/Unique.fir @@ -1,5 +1,4 @@ ; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; XFAIL: * ; CHECK: Reference x does not have a unique name. ; CHECK: Reference p does not have a unique name. diff --git a/test/passes/expand-accessors/accessor-mem.fir b/test/passes/expand-accessors/accessor-mem.fir index 1c055b48..6f8b63e3 100644 --- a/test/passes/expand-accessors/accessor-mem.fir +++ b/test/passes/expand-accessors/accessor-mem.fir @@ -8,16 +8,17 @@ circuit top : wire i : UInt<4> i := UInt(1) infer accessor a = m[i] ;CHECK: read accessor a = m[i] - infer accessor b = a[i] ;CHECK: b := (a[0] a[1])[i] - infer accessor c = b[i] ;CHECK: c := (b[0] b[1])[i] + infer accessor b = a[i] ;CHECK: indexer b = (a[0] a[1])[i] : UInt<32>[2] + infer accessor c = b[i] ;CHECK: indexer c = (b[0] b[1])[i] : UInt<32> wire j : UInt<32> j := c infer accessor x = m[i] ;CHECK: write accessor x = m[i] - infer accessor y = x[i] ;CHECK: (x[0] x[1])[i] := y + infer accessor y = x[i] ;CHECK: indexer (x[0] x[1])[i] = y : UInt<32>[2] y[0] := UInt(1) y[1] := UInt(1) - infer accessor z = y[i] ;CHECK: (y[0] y[1])[i] := z + infer accessor z = y[i] ;CHECK: indexer (y[0] y[1])[i] = z : UInt<32> z := j ; CHECK: Finished Expand Accessors +; CHECK: Done! diff --git a/test/passes/expand-accessors/accessor-vec.fir b/test/passes/expand-accessors/accessor-vec.fir index c505fbaf..96a5c74c 100644 --- a/test/passes/expand-accessors/accessor-vec.fir +++ b/test/passes/expand-accessors/accessor-vec.fir @@ -14,19 +14,19 @@ circuit top : m[1][1][1] := UInt(1) wire i : UInt i := UInt(1) - infer accessor a = m[i] ;CHECK: a := (m[0] m[1])[i] - infer accessor b = a[i] ;CHECK: b := (a[0] a[1])[i] - infer accessor c = b[i] ;CHECK: c := (b[0] b[1])[i] + infer accessor a = m[i] ;CHECK: indexer a = (m[0] m[1])[i] : UInt<32>[2][2] + infer accessor b = a[i] ;CHECK: indexer b = (a[0] a[1])[i] : UInt<32>[2] + infer accessor c = b[i] ;CHECK: indexer c = (b[0] b[1])[i] : UInt<32> wire j : UInt j := c - infer accessor x = m[i] ;CHECK: (m[0] m[1])[i] := x + infer accessor x = m[i] ;CHECK: indexer (m[0] m[1])[i] = x : UInt<32>[2][2] x[0][0] := UInt(1) x[1][0] := UInt(1) x[0][1] := UInt(1) x[1][1] := UInt(1) - infer accessor y = x[i] ;CHECK: (x[0] x[1])[i] := y - infer accessor z = y[i] ;CHECK: (y[0] y[1])[i] := z + infer accessor y = x[i] ;CHECK: indexer (x[0] x[1])[i] = y : UInt<32>[2] + infer accessor z = y[i] ;CHECK: indexer (y[0] y[1])[i] = z : UInt<32> y[0] := UInt(1) y[1] := UInt(1) z := j @@ -34,13 +34,14 @@ circuit top : wire p : {n : UInt<32>[2]} p.n[0] := UInt(1) p.n[1] := UInt(1) - infer accessor q = p.n[i] ;CHECK: (p.n[0] p.n[1])[i] := q + infer accessor q = p.n[i] ;CHECK: indexer (p.n[0] p.n[1])[i] = q : UInt<32> q := j wire r : {m : UInt<32>}[2] r[0].m := UInt(1) r[1].m := UInt(1) - infer accessor s = r[i] ;CHECK: s := (r[0] r[1])[i] + infer accessor s = r[i] ;CHECK: indexer s = (r[0] r[1])[i] : { m : UInt<32>} j := s.m ; CHECK: Finished Expand Accessors +; CHECK: Done! diff --git a/test/passes/expand-accessors/simple.fir b/test/passes/expand-accessors/simple.fir new file mode 100644 index 00000000..7f5a4eb8 --- /dev/null +++ b/test/passes/expand-accessors/simple.fir @@ -0,0 +1,15 @@ +; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s + +;CHECK: Expand Accessors +circuit top : + module top : + output o : UInt + wire m : UInt<32>[2] + wire i : UInt + m[0] := UInt("h1") + m[1] := UInt("h1") + i := UInt("h1") + infer accessor a = m[i] ;CHECK: indexer a = (m$0 m$1)[i] : UInt<32> + o := a + + diff --git a/test/passes/expand-accessors/simple2.fir b/test/passes/expand-accessors/simple2.fir new file mode 100644 index 00000000..54f8a507 --- /dev/null +++ b/test/passes/expand-accessors/simple2.fir @@ -0,0 +1,17 @@ +; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s + +;CHECK: Expand Accessors +circuit top : + module top : + output o1 : UInt + output o2 : UInt + wire m : UInt<32>[2] + wire i : UInt + m[0] := UInt("h1") + m[1] := UInt("h1") + i := UInt("h1") + infer accessor a = m[i] ;CHECK: indexer a = (m$0 m$1)[i] : UInt<32> + o1 := a + o2 := a + + diff --git a/test/passes/expand-whens/reg-and-when.fir b/test/passes/expand-whens/reg-and-when.fir index 9d23acf9..ac678b6d 100644 --- a/test/passes/expand-whens/reg-and-when.fir +++ b/test/passes/expand-whens/reg-and-when.fir @@ -1,5 +1,5 @@ ; RUN: firrtl -i %s -o %s.v -X verilog -p cd 2>&1 | tee %s.out ; cat %s.v | FileCheck %s -; CHECK: out_slow_bits <= fromhost_q$deq$valid ? fromhost_q$deq$bits : tohost_q$deq$bits; +; CHECK: out__slow__bits <= fromhost__q$deq$valid ? fromhost__q$deq$bits : tohost__q$deq$bits; circuit Top : module Top : input clock : Clock diff --git a/test/passes/infer-types/primops.fir b/test/passes/infer-types/primops.fir index 94f481f7..ac057c68 100644 --- a/test/passes/infer-types/primops.fir +++ b/test/passes/infer-types/primops.fir @@ -157,10 +157,10 @@ circuit top : node wnot = not(a) ;CHECK: node wnot = not(a@<t:UInt>)@<t:UInt> node unot = not(c) ;CHECK: node unot = not(c@<t:SInt>)@<t:SInt> - node wand_ = and(a, b) ;CHECK: node wand_ = and(a@<t:UInt>, b@<t:UInt>)@<t:UInt> + node WAND = and(a, b) ;CHECK: node WAND = and(a@<t:UInt>, b@<t:UInt>)@<t:UInt> node uand = and(c, d) ;CHECK: node uand = and(c@<t:SInt>, d@<t:SInt>)@<t:SInt> - node wor_ = or(a, b) ;CHECK: node wor_ = or(a@<t:UInt>, b@<t:UInt>)@<t:UInt> + node WOR = or(a, b) ;CHECK: node WOR = or(a@<t:UInt>, b@<t:UInt>)@<t:UInt> node uor = or(c, d) ;CHECK: node uor = or(c@<t:SInt>, d@<t:SInt>)@<t:SInt> node wxor = xor(a, b) ;CHECK: node wxor = xor(a@<t:UInt>, b@<t:UInt>)@<t:UInt> diff --git a/test/passes/expand-connect-indexed/bundle-vecs.fir b/test/passes/inline-indexers/bundle-vecs.fir index c41794e3..28826056 100644 --- a/test/passes/expand-connect-indexed/bundle-vecs.fir +++ b/test/passes/inline-indexers/bundle-vecs.fir @@ -1,6 +1,6 @@ ; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; CHECK: Expand Indexed Connects +; CHECK: Inline Indexers circuit top : module top : wire i : UInt @@ -20,16 +20,17 @@ circuit top : infer accessor b = a[i] - ; CHECK: wire b{{[_$]+}}x : UInt<32> - ; CHECK: wire b{{[_$]+}}y : UInt<32> - ; CHECK: b{{[_$]+}}x := a{{[_$]+}}0{{[_$]+}}x + ; CHECK: wire b{{[_$]+}}x_1 : UInt<32> ; CHECK: node i_1 = i - ; CHECK: when eqv(i_1, UInt("h1")) : b{{[_$]+}}x := a{{[_$]+}}1{{[_$]+}}x + ; CHECK: b{{[_$]+}}x_1 := a{{[_$]+}}0{{[_$]+}}x + ; CHECK: when eqv(i_1, UInt("h1")) : b{{[_$]+}}x_1 := a{{[_$]+}}1{{[_$]+}}x + ; CHECK: wire b{{[_$]+}}y_1 : UInt<32> ; CHECK: node i_2 = i - ; CHECK: when eqv(i_2, UInt("h0")) : a{{[_$]+}}0{{[_$]+}}y := b{{[_$]+}}y - ; CHECK: when eqv(i_2, UInt("h1")) : a{{[_$]+}}1{{[_$]+}}y := b{{[_$]+}}y + ; CHECK: when eqv(i_2, UInt("h0")) : a{{[_$]+}}0{{[_$]+}}y := b{{[_$]+}}y_1 + ; CHECK: when eqv(i_2, UInt("h1")) : a{{[_$]+}}1{{[_$]+}}y := b{{[_$]+}}y_1 j := b.x b.y := UInt(1) -; CHECK: Finished Expand Indexed Connects +; CHECK: Finished Inline Indexers +; CHECK: Done! diff --git a/test/passes/expand-connect-indexed/init-vecs.fir b/test/passes/inline-indexers/init-vecs.fir index 7d64a117..149215c3 100644 --- a/test/passes/expand-connect-indexed/init-vecs.fir +++ b/test/passes/inline-indexers/init-vecs.fir @@ -1,7 +1,6 @@ ; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; XFAIL: * -; CHECK: Expand Indexed Connects +; CHECK: Inline Indexers circuit top : module top : wire outs : UInt<32>[2][1] diff --git a/test/passes/inline-indexers/simple.fir b/test/passes/inline-indexers/simple.fir new file mode 100644 index 00000000..ca186e97 --- /dev/null +++ b/test/passes/inline-indexers/simple.fir @@ -0,0 +1,20 @@ +; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s + +;CHECK: Inline Indexers +circuit top : + module top : + output o : UInt + wire m : UInt<32>[2] + wire i : UInt + m[0] := UInt("h1") + m[1] := UInt("h1") + i := UInt("h1") + infer accessor a = m[i] + o := a + +;CHECK: a_1 := m$0 +;CHECK: when eqv(i_1, UInt("h1")) : a_1 := m$1 + + + +;CHECK: Done! diff --git a/test/passes/inline-indexers/simple2.fir b/test/passes/inline-indexers/simple2.fir new file mode 100644 index 00000000..3b7d92af --- /dev/null +++ b/test/passes/inline-indexers/simple2.fir @@ -0,0 +1,26 @@ +; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s + +;CHECK: Inline Indexers +circuit top : + module top : + output o1 : UInt + output o2 : UInt + wire m : UInt<32>[2] + wire i : UInt + m[0] := UInt("h1") + m[1] := UInt("h1") + i := UInt("h1") + infer accessor a = m[i] + o1 := a + o2 := a + +;CHECK: wire a_1 : UInt<32> +;CHECK: a_1 := m$0 +;CHECK: when eqv(i_1, UInt("h1")) : a_1 := m$1 +;CHECK: wire a_2 : UInt<32> +;CHECK: a_2 := m$0 +;CHECK: when eqv(i_2, UInt("h1")) : a_2 := m$1 + + + +;CHECK: Done! diff --git a/test/passes/inline-indexers/simple3.fir b/test/passes/inline-indexers/simple3.fir new file mode 100644 index 00000000..688958a0 --- /dev/null +++ b/test/passes/inline-indexers/simple3.fir @@ -0,0 +1,20 @@ +; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s + +;CHECK: Inline Indexers +circuit top : + module top : + input in : UInt<32> + input i : UInt<1> + wire m : UInt<32>[2] + m[0] := UInt("h1") + m[1] := UInt("h1") + infer accessor a = m[i] + a := in + +;CHECK: wire a_1 : UInt<32> +;CHECK: when eqv(i_1, UInt("h0")) : m$0 := a_1 +;CHECK: when eqv(i_1, UInt("h1")) : m$1 := a_1 + + + +;CHECK: Done! diff --git a/test/passes/inline-indexers/simple4.fir b/test/passes/inline-indexers/simple4.fir new file mode 100644 index 00000000..df045456 --- /dev/null +++ b/test/passes/inline-indexers/simple4.fir @@ -0,0 +1,25 @@ +; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s + +;CHECK: Inline Indexers +circuit top : + module top : + input in : {x : UInt<32>, y : UInt<32>} + input i : UInt<1> + wire m : {x : UInt<32>, y : UInt<32>}[2] + m[0].x := UInt("h1") + m[0].y := UInt("h1") + m[1].x := UInt("h1") + m[1].y := UInt("h1") + infer accessor a = m[i] + a.x := in.x + +;CHECK: wire a$x_1 : UInt<32> +;CHECK: node i_1 = i +;CHECK: when eqv(i_1, UInt("h0")) : m$0$x := a$x_1 +;CHECK: when eqv(i_1, UInt("h1")) : m$1$x := a$x_1 +;CHECK: a$x_1 := in$x +;CHECK: Finished Inline Indexers +;CHECK: Done! + + + diff --git a/test/passes/inline-indexers/simple5.fir b/test/passes/inline-indexers/simple5.fir new file mode 100644 index 00000000..1da83cab --- /dev/null +++ b/test/passes/inline-indexers/simple5.fir @@ -0,0 +1,21 @@ +; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s + +;CHECK: Inline Indexers +circuit top : + module top : + output o : UInt + o := UInt(1) + wire m : UInt<32>[2] + wire i : UInt + m[0] := UInt("h1") + m[1] := UInt("h1") + i := UInt("h1") + when i : + infer accessor a = m[i] + o := a + +;CHECK: when i : +;CHECK: a_1 := m$0 +;CHECK: when eqv(i_1, UInt("h1")) : a_1 := m$1 +;CHECK: Finished Inline Indexers +;CHECK: Done! diff --git a/test/passes/inline-indexers/simple6.fir b/test/passes/inline-indexers/simple6.fir new file mode 100644 index 00000000..e94efc7a --- /dev/null +++ b/test/passes/inline-indexers/simple6.fir @@ -0,0 +1,45 @@ +; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s + +;CHECK: Inline Indexers +circuit top : + module top : + input value : UInt<32> + input in : {x : UInt<32>, y : UInt<32>} + wire m :{x : UInt<32>, y : UInt<32>}[2][2] + wire i : UInt + wire j : UInt + + m[0][0] := in + m[1][0] := in + m[0][1] := in + m[1][1] := in + i := UInt("h1") + j := UInt("h1") + + write accessor a = m[i] + write accessor b = a[j] + b.x := value + +;CHECK: wire b$x_1 : UInt<32> +;CHECK: node j_1 = j +;CHECK: when eqv(j_1, UInt("h0")) : +;CHECK: wire a$0$x_1 : UInt<32> +;CHECK: node i_1 = i +;CHECK: when eqv(i_1, UInt("h0")) : +;CHECK: m$0$0$x := a$0$x_1 +;CHECK: when eqv(i_1, UInt("h1")) : +;CHECK: m$1$0$x := a$0$x_1 +;CHECK: a$0$x_1 := b$x_1 +;CHECK: when eqv(j_1, UInt("h1")) : +;CHECK: wire a$1$x_1 : UInt<32> +;CHECK: node i_2 = i +;CHECK: when eqv(i_2, UInt("h0")) : +;CHECK: m$0$1$x := a$1$x_1 +;CHECK: when eqv(i_2, UInt("h1")) : +;CHECK: m$1$1$x := a$1$x_1 +;CHECK: a$1$x_1 := b$x_1 +;CHECK: b$x_1 := value + + + +;CHECK: Done! diff --git a/test/passes/inline-indexers/simple7.fir b/test/passes/inline-indexers/simple7.fir new file mode 100644 index 00000000..cc9c6231 --- /dev/null +++ b/test/passes/inline-indexers/simple7.fir @@ -0,0 +1,13 @@ +; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s + +;CHECK: Inline Indexers +circuit top : + module top : + output out : UInt<64> + input index : UInt<1> + wire T_292 : UInt<64>[2] + T_292[0] := UInt(1) + T_292[1] := UInt(1) + infer accessor T_297 = T_292[index] + out := T_297 +;CHECK: Done! diff --git a/test/passes/inline-indexers/simple8.fir b/test/passes/inline-indexers/simple8.fir new file mode 100644 index 00000000..a02395a7 --- /dev/null +++ b/test/passes/inline-indexers/simple8.fir @@ -0,0 +1,240 @@ +; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s + +;CHECK: Inline Indexers +circuit top : + module top : + output resp : UInt<128>[4] + input write : {flip ready : UInt<1>, valid : UInt<1>, bits : {way_en : UInt<4>, addr : UInt<12>, wmask : UInt<2>, data : UInt<128>}} + input read : {flip ready : UInt<1>, valid : UInt<1>, bits : {way_en : UInt<4>, addr : UInt<12>}} + input clock : Clock + input reset : UInt<1> + + resp[0] := UInt<1>("h00") + resp[1] := UInt<1>("h00") + resp[2] := UInt<1>("h00") + resp[3] := UInt<1>("h00") + write.ready := UInt<1>("h00") + read.ready := UInt<1>("h00") + node waddr = shr(write.bits.addr, 4) + node raddr = shr(read.bits.addr, 4) + node T_65 = bits(write.bits.way_en, 1, 0) + node T_66 = bits(read.bits.way_en, 1, 0) + wire T_75 : UInt<128>[2] + T_75[0] := UInt<1>("h00") + T_75[1] := UInt<1>("h00") + reg T_81 : UInt<12>, clock, reset + when read.valid : + T_81 := read.bits.addr + skip + cmem T_84 : UInt<128>[256], clock + node T_86 = neq(T_65, UInt<1>("h00")) + node T_87 = and(T_86, write.valid) + node T_88 = bit(write.bits.wmask, 0) + node T_89 = and(T_87, T_88) + when T_89 : + node T_90 = bits(write.bits.data, 63, 0) + node T_91 = cat(T_90, T_90) + node T_92 = bit(T_65, 0) + node T_93 = bit(T_65, 1) + wire T_95 : UInt<1>[2] + T_95[0] := T_92 + T_95[1] := T_93 + node T_100 = subw(UInt<64>("h00"), T_95[0]) + node T_102 = subw(UInt<64>("h00"), T_95[1]) + wire T_104 : UInt<64>[2] + T_104[0] := T_100 + T_104[1] := T_102 + node T_108 = cat(T_104[1], T_104[0]) + infer accessor T_109 = T_84[waddr] + node T_110 = not(T_108) + node T_111 = and(T_109, T_110) + node T_112 = and(T_91, T_108) + node T_113 = or(T_111, T_112) + wire T_114 : UInt<128> + T_114 := UInt<1>("h00") + T_114 := T_113 + infer accessor T_116 = T_84[waddr] + T_116 := T_114 + skip + node T_118 = neq(T_66, UInt<1>("h00")) + node T_119 = and(T_118, read.valid) + reg T_120 : UInt<8>, clock, reset + when T_119 : + T_120 := raddr + skip + infer accessor T_121 = T_84[T_120] + T_75[0] := T_121 + cmem T_124 : UInt<128>[256], clock + node T_126 = neq(T_65, UInt<1>("h00")) + node T_127 = and(T_126, write.valid) + node T_128 = bit(write.bits.wmask, 1) + node T_129 = and(T_127, T_128) + when T_129 : + node T_130 = bits(write.bits.data, 127, 64) + node T_131 = cat(T_130, T_130) + node T_132 = bit(T_65, 0) + node T_133 = bit(T_65, 1) + wire T_135 : UInt<1>[2] + T_135[0] := T_132 + T_135[1] := T_133 + node T_140 = subw(UInt<64>("h00"), T_135[0]) + node T_142 = subw(UInt<64>("h00"), T_135[1]) + wire T_144 : UInt<64>[2] + T_144[0] := T_140 + T_144[1] := T_142 + node T_148 = cat(T_144[1], T_144[0]) + infer accessor T_149 = T_124[waddr] + node T_150 = not(T_148) + node T_151 = and(T_149, T_150) + node T_152 = and(T_131, T_148) + node T_153 = or(T_151, T_152) + wire T_154 : UInt<128> + T_154 := UInt<1>("h00") + T_154 := T_153 + infer accessor T_156 = T_124[waddr] + T_156 := T_154 + skip + node T_158 = neq(T_66, UInt<1>("h00")) + node T_159 = and(T_158, read.valid) + reg T_160 : UInt<8>, clock, reset + when T_159 : + T_160 := raddr + skip + infer accessor T_161 = T_124[T_160] + T_75[1] := T_161 + node T_162 = bits(T_75[0], 63, 0) + node T_163 = bits(T_75[1], 63, 0) + wire T_165 : UInt<64>[2] + T_165[0] := T_162 + T_165[1] := T_163 + node T_169 = bits(T_81, 3, 3) + infer accessor T_170 = T_165[T_169] + wire T_172 : UInt<64>[2] + T_172[0] := T_170 + T_172[1] := T_165[1] + node T_176 = cat(T_172[1], T_172[0]) + resp[0] := T_176 + node T_177 = bits(T_75[0], 127, 64) + node T_178 = bits(T_75[1], 127, 64) + wire T_180 : UInt<64>[2] + T_180[0] := T_177 + T_180[1] := T_178 + node T_184 = bits(T_81, 3, 3) + infer accessor T_185 = T_180[T_184] + wire T_187 : UInt<64>[2] + T_187[0] := T_185 + T_187[1] := T_180[1] + node T_191 = cat(T_187[1], T_187[0]) + resp[1] := T_191 + node T_192 = bits(write.bits.way_en, 3, 2) + node T_193 = bits(read.bits.way_en, 3, 2) + wire T_202 : UInt<128>[2] + T_202[0] := UInt<1>("h00") + T_202[1] := UInt<1>("h00") + reg T_208 : UInt<12>, clock, reset + when read.valid : + T_208 := read.bits.addr + skip + cmem T_211 : UInt<128>[256], clock + node T_213 = neq(T_192, UInt<1>("h00")) + node T_214 = and(T_213, write.valid) + node T_215 = bit(write.bits.wmask, 0) + node T_216 = and(T_214, T_215) + when T_216 : + node T_217 = bits(write.bits.data, 63, 0) + node T_218 = cat(T_217, T_217) + node T_219 = bit(T_192, 0) + node T_220 = bit(T_192, 1) + wire T_222 : UInt<1>[2] + T_222[0] := T_219 + T_222[1] := T_220 + node T_227 = subw(UInt<64>("h00"), T_222[0]) + node T_229 = subw(UInt<64>("h00"), T_222[1]) + wire T_231 : UInt<64>[2] + T_231[0] := T_227 + T_231[1] := T_229 + node T_235 = cat(T_231[1], T_231[0]) + infer accessor T_236 = T_211[waddr] + node T_237 = not(T_235) + node T_238 = and(T_236, T_237) + node T_239 = and(T_218, T_235) + node T_240 = or(T_238, T_239) + wire T_241 : UInt<128> + T_241 := UInt<1>("h00") + T_241 := T_240 + infer accessor T_243 = T_211[waddr] + T_243 := T_241 + skip + node T_245 = neq(T_193, UInt<1>("h00")) + node T_246 = and(T_245, read.valid) + reg T_247 : UInt<8>, clock, reset + when T_246 : + T_247 := raddr + skip + infer accessor T_248 = T_211[T_247] + T_202[0] := T_248 + cmem T_251 : UInt<128>[256], clock + node T_253 = neq(T_192, UInt<1>("h00")) + node T_254 = and(T_253, write.valid) + node T_255 = bit(write.bits.wmask, 1) + node T_256 = and(T_254, T_255) + when T_256 : + node T_257 = bits(write.bits.data, 127, 64) + node T_258 = cat(T_257, T_257) + node T_259 = bit(T_192, 0) + node T_260 = bit(T_192, 1) + wire T_262 : UInt<1>[2] + T_262[0] := T_259 + T_262[1] := T_260 + node T_267 = subw(UInt<64>("h00"), T_262[0]) + node T_269 = subw(UInt<64>("h00"), T_262[1]) + wire T_271 : UInt<64>[2] + T_271[0] := T_267 + T_271[1] := T_269 + node T_275 = cat(T_271[1], T_271[0]) + infer accessor T_276 = T_251[waddr] + node T_277 = not(T_275) + node T_278 = and(T_276, T_277) + node T_279 = and(T_258, T_275) + node T_280 = or(T_278, T_279) + wire T_281 : UInt<128> + T_281 := UInt<1>("h00") + T_281 := T_280 + infer accessor T_283 = T_251[waddr] + T_283 := T_281 + skip + node T_285 = neq(T_193, UInt<1>("h00")) + node T_286 = and(T_285, read.valid) + reg T_287 : UInt<8>, clock, reset + when T_286 : + T_287 := raddr + skip + infer accessor T_288 = T_251[T_287] + T_202[1] := T_288 + node T_289 = bits(T_202[0], 63, 0) + node T_290 = bits(T_202[1], 63, 0) + wire T_292 : UInt<64>[2] + T_292[0] := T_289 + T_292[1] := T_290 + node T_296 = bits(T_208, 3, 3) + infer accessor T_297 = T_292[T_296] + wire T_299 : UInt<64>[2] + T_299[0] := T_297 + T_299[1] := T_292[1] + node T_303 = cat(T_299[1], T_299[0]) + resp[2] := T_303 + node T_304 = bits(T_202[0], 127, 64) + node T_305 = bits(T_202[1], 127, 64) + wire T_307 : UInt<64>[2] + T_307[0] := T_304 + T_307[1] := T_305 + node T_311 = bits(T_208, 3, 3) + infer accessor T_312 = T_307[T_311] + wire T_314 : UInt<64>[2] + T_314[0] := T_312 + T_314[1] := T_307[1] + node T_318 = cat(T_314[1], T_314[0]) + resp[3] := T_318 + read.ready := UInt<1>("h01") + write.ready := UInt<1>("h01") +;CHECK: Done! diff --git a/test/passes/inline-indexers/simple9.fir b/test/passes/inline-indexers/simple9.fir new file mode 100644 index 00000000..a40abb17 --- /dev/null +++ b/test/passes/inline-indexers/simple9.fir @@ -0,0 +1,18 @@ +; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s + +;CHECK: Inline Indexers +circuit top : + module top : + input T_4910 : UInt<1> + input T_4581 : UInt<1> + input reset : UInt<1> + input clock : Clock + output out : UInt<1> + reg T_4590 : UInt<1>[2], clock, reset + T_4590[0] := UInt(0) + T_4590[1] := UInt(0) + out := UInt(0) + when T_4910 : + infer accessor T_4911 = T_4590[T_4581] + out := T_4911 +;CHECK: Done! diff --git a/test/passes/lower-to-ground/accessor.fir b/test/passes/lower-to-ground/accessor.fir index fd261e1e..4d55d0f6 100644 --- a/test/passes/lower-to-ground/accessor.fir +++ b/test/passes/lower-to-ground/accessor.fir @@ -14,13 +14,11 @@ circuit top : ; CHECK: wire a{{[_$]+}}3 : UInt<32> infer accessor b = a[i] - ; CHECK: wire b : UInt<32> - ; CHECK: b := (a{{[_$]+}}0 a{{[_$]+}}1 a{{[_$]+}}2 a{{[_$]+}}3)[i] + ; CHECK: indexer b = (a{{[_$]+}}0 a{{[_$]+}}1 a{{[_$]+}}2 a{{[_$]+}}3)[i] : UInt<32> j := b infer accessor c = a[i] - ; CHECK: wire c : UInt<32> - ; CHECK: (a{{[_$]+}}0 a{{[_$]+}}1 a{{[_$]+}}2 a{{[_$]+}}3)[i] := c + ; CHECK: indexer (a{{[_$]+}}0 a{{[_$]+}}1 a{{[_$]+}}2 a{{[_$]+}}3)[i] = c : UInt<32> c := j cmem p : UInt<32>[4],clk diff --git a/test/passes/lower-to-ground/bundle-vecs.fir b/test/passes/lower-to-ground/bundle-vecs.fir index 17927aef..7d37e65c 100644 --- a/test/passes/lower-to-ground/bundle-vecs.fir +++ b/test/passes/lower-to-ground/bundle-vecs.fir @@ -13,17 +13,13 @@ circuit top : ; CHECK: wire a{{[_$]+}}1{{[_$]+}}y : UInt<32> infer accessor b = a[i] - ; CHECK: wire b{{[_$]+}}x : UInt<32> - ; CHECK: wire b{{[_$]+}}y : UInt<32> - ; CHECK: b{{[_$]+}}x := (a{{[_$]+}}0{{[_$]+}}x a{{[_$]+}}1{{[_$]+}}x)[i] - ; CHECK: (a{{[_$]+}}0{{[_$]+}}y a{{[_$]+}}1{{[_$]+}}y)[i] := b{{[_$]+}}y + ; CHECK: indexer b{{[_$]+}}x = (a{{[_$]+}}0{{[_$]+}}x a{{[_$]+}}1{{[_$]+}}x)[i] : UInt<32> + ; CHECK: indexer (a{{[_$]+}}0{{[_$]+}}y a{{[_$]+}}1{{[_$]+}}y)[i] = b{{[_$]+}}y : UInt<32> j := b infer accessor c = a[i] - ; CHECK: wire c{{[_$]+}}x : UInt<32> - ; CHECK: wire c{{[_$]+}}y : UInt<32> - ; CHECK: (a{{[_$]+}}0{{[_$]+}}x a{{[_$]+}}1{{[_$]+}}x)[i] := c{{[_$]+}}x - ; CHECK: c{{[_$]+}}y := (a{{[_$]+}}0{{[_$]+}}y a{{[_$]+}}1{{[_$]+}}y)[i] + ; CHECK: indexer (a{{[_$]+}}0{{[_$]+}}x a{{[_$]+}}1{{[_$]+}}x)[i] = c{{[_$]+}}x : UInt<32> + ; CHECK: indexer c{{[_$]+}}y = (a{{[_$]+}}0{{[_$]+}}y a{{[_$]+}}1{{[_$]+}}y)[i] : UInt<32> c := j diff --git a/test/passes/lower-to-ground/nested-vec.fir b/test/passes/lower-to-ground/nested-vec.fir index d484a6dc..aa208b01 100644 --- a/test/passes/lower-to-ground/nested-vec.fir +++ b/test/passes/lower-to-ground/nested-vec.fir @@ -15,10 +15,8 @@ circuit top : ; CHECK: wire a{{[_$]+}}1{{[_$]+}}y : UInt<32> infer accessor b = a[i] - ; CHECK: wire b{{[_$]+}}x : UInt<32> - ; CHECK: wire b{{[_$]+}}y : UInt<32> - ; CHECK: b{{[_$]+}}x := (a{{[_$]+}}0{{[_$]+}}x a{{[_$]+}}1{{[_$]+}}x)[i] - ; CHECK: (a{{[_$]+}}0{{[_$]+}}y a{{[_$]+}}1{{[_$]+}}y)[i] := b{{[_$]+}}y + ; CHECK: indexer b{{[_$]+}}x = (a{{[_$]+}}0{{[_$]+}}x a{{[_$]+}}1{{[_$]+}}x)[i] : UInt<32> + ; CHECK: indexer (a{{[_$]+}}0{{[_$]+}}y a{{[_$]+}}1{{[_$]+}}y)[i] = b{{[_$]+}}y : UInt<32> j := b cmem m : { x : UInt<32>, y : UInt<32> }[2],clk diff --git a/test/passes/split-exp/split-in-when.fir b/test/passes/split-exp/split-in-when.fir index ddf6a155..58819d22 100644 --- a/test/passes/split-exp/split-in-when.fir +++ b/test/passes/split-exp/split-in-when.fir @@ -13,11 +13,11 @@ circuit Top : when bit(subw(a,c),3) : out := mux(eqv(bits(UInt(32),4,0),UInt(13)),addw(a,addw(b,c)),subw(c,b)) -;CHECK: node T = subw(a, c) +;CHECK: node F = subw(a, c) ;CHECK: node out_1 = eqv(UInt("h0"), UInt("hd")) ;CHECK: node out_3 = addw(b, c) ;CHECK: node out_2 = addw(a, out_3) ;CHECK: node out_4 = subw(c, b) -;CHECK: when bit(T, 3) : out := mux(out_1, out_2, out_4) +;CHECK: when bit(F, 3) : out := mux(out_1, out_2, out_4) ;CHECK: Finished Split Expressions |