Fixed a bunch of tests, and minor bugs

20 files changed, 52 insertions, 60 deletions

diff --git a/test/errors/gender/ReadOutput.fir b/test/errors/gender/ReadOutput.fir
index fd3607d0..f9e8f7b4 100644
--- a/test/errors/gender/ReadOutput.fir
+++ b/test/errors/gender/ReadOutput.fir
@@ -1,5 +1,5 @@
 ; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
-; CHECK: Expression out$y is used as a sink but can only be used as a source.
+; CHECK: Expression out is used as a source but can only be used as a sink.
 
 circuit BTB :
   module BTB : 
diff --git a/test/errors/high-form/Flip-Mem.fir b/test/errors/high-form/Flip-Mem.fir
index ebc3ddbf..a8cb67ca 100644
--- a/test/errors/high-form/Flip-Mem.fir
+++ b/test/errors/high-form/Flip-Mem.fir
@@ -1,6 +1,5 @@
 ; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
 ; CHECK: Memory mc cannot be a bundle type with flips.
-; CHECK: Memory ms cannot be a bundle type with flips.
 
 circuit Flip-Mem : 
   module Flip-Mem : 
diff --git a/test/errors/high-form/InvalidSubexp.fir b/test/errors/high-form/InvalidSubexp.fir
index 23c155e2..d0ad34c0 100644
--- a/test/errors/high-form/InvalidSubexp.fir
+++ b/test/errors/high-form/InvalidSubexp.fir
@@ -1,6 +1,6 @@
 ; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
-; CHECK: Invalid index access to non-reference.
-; CHECK: Invalid subfield access to non-reference.
+; CHECK: Invalid access to non-reference.
+; CHECK: Invalid access to non-reference.
 
 circuit Top :
   module Top :
diff --git a/test/errors/high-form/Printf.fir b/test/errors/high-form/Printf.fir
index 7f285d3e..5580182b 100644
--- a/test/errors/high-form/Printf.fir
+++ b/test/errors/high-form/Printf.fir
@@ -4,9 +4,10 @@ circuit Top :
   module Top : 
     input x : {y : UInt<1>}
     input p : UInt<1>
-    printf("Hello World%!\n",x)
-    printf("Hello World%")
-    printf("Hello World%d %s %h %x",x,x,x)
+    input clk : Clock
+    printf(clk,p,"Hello World%!\n",x)
+    printf(clk,p,"Hello World%")
+    printf(clk,p,"Hello World%d %s %h %x",x,x,x)
 
 ;CHECK: Bad printf format: "%!"
 ;CHECK: Bad printf format: trailing "%"
diff --git a/test/errors/parser/InstanceNotRef.fir b/test/errors/parser/InstanceNotRef.fir
index a6996fee..0760f168 100644
--- a/test/errors/parser/InstanceNotRef.fir
+++ b/test/errors/parser/InstanceNotRef.fir
@@ -1,5 +1,5 @@
 ; RUN: firrtl -i %s -o %s.flo -x X -p c | tee %s.out | FileCheck %s
-; CHECK: FIRRTL Parsing Error: Expected a reference expression here.
+; CHECK: FIRRTL Parsing Error: Expected a statement here.
 
 circuit Top :
   module Top :
diff --git a/test/features/InitAccessor.fir b/test/features/InitAccessor.fir
index 6261ec01..5a81a62e 100644
--- a/test/features/InitAccessor.fir
+++ b/test/features/InitAccessor.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.v -X verilog -p cT 2>&1 | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
 
 ;CHECK: Done!
 circuit Top : 
diff --git a/test/passes/jacktest/Counter.fir b/test/passes/jacktest/Counter.fir
index db2b5d62..4e23ba26 100644
--- a/test/passes/jacktest/Counter.fir
+++ b/test/passes/jacktest/Counter.fir
@@ -8,8 +8,7 @@ circuit Counter :
     output tot : UInt<8>
     input amt : UInt<4>
     
-    reg T_13 : UInt<8>,clk,reset
-    onreset T_13 <= UInt<8>(0)
+    reg T_13 : UInt<8>,clk,reset,UInt<8>(0)
     when inc : 
       node T_14 = addw(T_13, amt)
       node T_15 = gt(T_14, UInt<8>(255))
diff --git a/test/passes/jacktest/EnableShiftRegister.fir b/test/passes/jacktest/EnableShiftRegister.fir
index 7937d37f..d7e91665 100644
--- a/test/passes/jacktest/EnableShiftRegister.fir
+++ b/test/passes/jacktest/EnableShiftRegister.fir
@@ -8,14 +8,10 @@ circuit EnableShiftRegister :
     output out : UInt<4>
     input shift : UInt<1>
     
-    reg r0 : UInt<4>,clk,reset
-    onreset r0 <= UInt<4>(0)
-    reg r1 : UInt<4>,clk,reset
-    onreset r1 <= UInt<4>(0)
-    reg r2 : UInt<4>,clk,reset
-    onreset r2 <= UInt<4>(0)
-    reg r3 : UInt<4>,clk,reset
-    onreset r3 <= UInt<4>(0)
+    reg r0 : UInt<4>,clk,reset,UInt<4>(0)
+    reg r1 : UInt<4>,clk,reset,UInt<4>(0)
+    reg r2 : UInt<4>,clk,reset,UInt<4>(0)
+    reg r3 : UInt<4>,clk,reset,UInt<4>(0)
     when shift : 
       r0 <= in
       r1 <= r0
diff --git a/test/passes/jacktest/LFSR16.fir b/test/passes/jacktest/LFSR16.fir
index 770ac3e6..a4052623 100644
--- a/test/passes/jacktest/LFSR16.fir
+++ b/test/passes/jacktest/LFSR16.fir
@@ -7,8 +7,7 @@ circuit LFSR16 :
     input clk : Clock
     input reset : UInt<1>
     
-    reg res : UInt<16>,clk,reset
-    onreset res <= UInt<16>(1)
+    reg res : UInt<16>,clk,reset,UInt<16>(1)
     when inc : 
       node T_16 = bit(res, 0)
       node T_17 = bit(res, 2)
diff --git a/test/passes/jacktest/MemorySearch.fir b/test/passes/jacktest/MemorySearch.fir
index 1e07596c..1abc50a2 100644
--- a/test/passes/jacktest/MemorySearch.fir
+++ b/test/passes/jacktest/MemorySearch.fir
@@ -9,8 +9,7 @@ circuit MemorySearch :
     input reset : UInt<1>
     output done : UInt<1>
     
-    reg index : UInt<3>,clk,reset
-    onreset index <= UInt<3>(0)
+    reg index : UInt<3>,clk,reset,UInt<3>(0)
     wire elts : UInt<4>[7]
     elts[0] <= UInt<4>(0)
     elts[1] <= UInt<4>(4)
@@ -19,7 +18,7 @@ circuit MemorySearch :
     elts[4] <= UInt<4>(2)
     elts[5] <= UInt<4>(5)
     elts[6] <= UInt<4>(13)
-    infer accessor elt = elts[index]
+    node elt = elts[index]
     node T_35 = not(en)
     node T_36 = eq(elt, target)
     node T_37 = eq(index, UInt<3>(7))
diff --git a/test/passes/jacktest/Mul.fir b/test/passes/jacktest/Mul.fir
index 8a3223e7..370c84a7 100644
--- a/test/passes/jacktest/Mul.fir
+++ b/test/passes/jacktest/Mul.fir
@@ -25,5 +25,5 @@ circuit Mul :
     tbl[15] <= UInt<4>(9)
     node T_42 = shl(x, 2)
     node T_43 = or(T_42, y)
-    infer accessor T_44 = tbl[T_43]
+    node T_44 = tbl[T_43]
     z <= T_44
diff --git a/test/passes/jacktest/RegisterVecShift.fir b/test/passes/jacktest/RegisterVecShift.fir
index eb2a0f34..61376a62 100644
--- a/test/passes/jacktest/RegisterVecShift.fir
+++ b/test/passes/jacktest/RegisterVecShift.fir
@@ -9,7 +9,7 @@ circuit RegisterVecShift :
     input shift : UInt<1>
     input ins : UInt<4>[4]
     
-    reg delays : UInt<4>[4],clk,reset
+    reg delays : UInt<4>[4],clk,reset,delays
     when reset : 
       wire T_33 : UInt<4>[4]
       T_33[0] <= UInt<4>(0)
diff --git a/test/passes/jacktest/Rom.fir b/test/passes/jacktest/Rom.fir
index 6e4b3cc7..db76b9c7 100644
--- a/test/passes/jacktest/Rom.fir
+++ b/test/passes/jacktest/Rom.fir
@@ -22,5 +22,5 @@ circuit Rom :
     r[13] <= UInt<5>(26)
     r[14] <= UInt<5>(28)
     r[15] <= UInt<5>(30)
-    infer accessor T_39 = r[addr]
+    node T_39 = r[addr]
     out <= T_39
diff --git a/test/passes/jacktest/Stack.fir b/test/passes/jacktest/Stack.fir
index ed718331..9b35c3f4 100644
--- a/test/passes/jacktest/Stack.fir
+++ b/test/passes/jacktest/Stack.fir
@@ -1,4 +1,6 @@
 ; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
+;CHECK: Finished Low Form Check
+;CHECK-NOT: stack_mem.T_32.mask <= UInt("h0")
 ;CHECK: Done!
 circuit Stack : 
   module Stack : 
@@ -10,16 +12,14 @@ circuit Stack :
     output dataOut : UInt<32>
     input dataIn : UInt<32>
     
-    cmem stack_mem : UInt<32>[16],clk
-    reg sp : UInt<5>,clk,reset
-    onreset sp <= UInt<5>(0)
-    reg out : UInt<32>,clk,reset
-    onreset out <= UInt<32>(0)
+    cmem stack_mem : UInt<32>[16]
+    reg sp : UInt<5>,clk,reset,UInt<5>(0)
+    reg out : UInt<32>,clk,reset,UInt<32>(0)
     when en : 
       node T_30 = lt(sp, UInt<5>(16))
       node T_31 = and(push, T_30)
       when T_31 : 
-        infer accessor T_32 = stack_mem[sp]
+        write mport T_32 = stack_mem[sp],clk
         T_32 <= dataIn
         node T_33 = addw(sp, UInt<1>(1))
         sp <= T_33
@@ -32,6 +32,6 @@ circuit Stack :
       node T_37 = gt(sp, UInt<1>(0))
       when T_37 : 
         node T_38 = subw(sp, UInt<1>(1))
-        infer accessor T_39 = stack_mem[T_38]
+        read mport T_39 = stack_mem[T_38],clk
         out <= T_39
     dataOut <= out
diff --git a/test/passes/jacktest/VendingMachine.fir b/test/passes/jacktest/VendingMachine.fir
index 5ecfe522..79cebbe1 100644
--- a/test/passes/jacktest/VendingMachine.fir
+++ b/test/passes/jacktest/VendingMachine.fir
@@ -8,8 +8,7 @@ circuit VendingMachine :
     input clk : Clock
     input reset : UInt<1>
     
-    reg state : UInt<3>,clk,reset
-    onreset state <= UInt<3>(0)
+    reg state : UInt<3>,clk,reset,UInt<3>(0)
     node T_22 = eq(state, UInt<3>(0))
     when T_22 : 
       when nickel : state <= UInt<3>(1)
diff --git a/test/passes/jacktest/gcd.fir b/test/passes/jacktest/gcd.fir
index 99667b3b..dd3443f1 100644
--- a/test/passes/jacktest/gcd.fir
+++ b/test/passes/jacktest/gcd.fir
@@ -10,8 +10,8 @@ circuit GCD :
     input a : UInt<16>
     input b : UInt<16>
     
-    reg x : UInt<16>,clk,reset
-    reg y : UInt<16>,clk,reset
+    reg x : UInt<16>,clk,reset,x
+    reg y : UInt<16>,clk,reset,y
     node T_17 = gt(x, y)
     when T_17 : 
       node T_18 = subw(x, y)
diff --git a/test/passes/jacktest/risc.fir b/test/passes/jacktest/risc.fir
index fdc80ee1..e4516db4 100644
--- a/test/passes/jacktest/risc.fir
+++ b/test/passes/jacktest/risc.fir
@@ -13,8 +13,7 @@ circuit Risc :
     
     cmem file : UInt<32>[256],clk
     cmem code : UInt<32>[256],clk
-    reg pc : UInt<8>,clk,reset
-    onreset pc <= UInt<8>(0)
+    reg pc : UInt<8>,clk,reset,UInt<8>(0)
     infer accessor inst = code[pc]
     node op = bits(inst, 31, 24)
     node rci = bits(inst, 23, 16)
diff --git a/test/passes/lower-to-ground/bundle-vecs.fir b/test/passes/lower-to-ground/bundle-vecs.fir
index 719033cb..9821f69b 100644
--- a/test/passes/lower-to-ground/bundle-vecs.fir
+++ b/test/passes/lower-to-ground/bundle-vecs.fir
@@ -25,20 +25,20 @@ circuit top :
 ;CHECK: wire GEN_3 : UInt<32>
 ;CHECK: j_x <= GEN
 ;CHECK: j_y <= GEN_3
-;CHECK: node a_0_x = eqv(UInt("h0"), i)
-;CHECK: a_0_x <= mux(a_0_x, GEN_2, UInt("h0"))
-;CHECK: node a_0_y = eqv(UInt("h0"), i)
-;CHECK: a_0_y <= mux(a_0_y, GEN_1, UInt("h0"))
-;CHECK: node a_1_x = eqv(UInt("h1"), i)
-;CHECK: a_1_x <= mux(a_1_x, GEN_2, UInt("h0"))
-;CHECK: node a_1_y = eqv(UInt("h1"), i)
-;CHECK: a_1_y <= mux(a_1_y, GEN_1, UInt("h0"))
-;CHECK: node GEN_4 = eqv(UInt("h1"), i)
-;CHECK: GEN <= mux(GEN_4, a_1_x, a_0_x)
+;CHECK: node GEN_4 = eqv(UInt("h0"), i)
+;CHECK: a_0_x <= mux(GEN_4, GEN_2, UInt("h0"))
+;CHECK: node GEN_5 = eqv(UInt("h0"), i)
+;CHECK: a_0_y <= mux(GEN_5, GEN_1, UInt("h0"))
+;CHECK: node GEN_6 = eqv(UInt("h1"), i)
+;CHECK: a_1_x <= mux(GEN_6, GEN_2, UInt("h0"))
+;CHECK: node GEN_7 = eqv(UInt("h1"), i)
+;CHECK: a_1_y <= mux(GEN_7, GEN_1, UInt("h0"))
+;CHECK: node GEN_8 = eqv(UInt("h1"), i)
+;CHECK: GEN <= mux(GEN_8, a_1_x, a_0_x)
 ;CHECK: GEN_1 <= j_y
 ;CHECK: GEN_2 <= j_x
-;CHECK: node GEN_5 = eqv(UInt("h1"), i)
-;CHECK: GEN_3 <= mux(GEN_5, a_1_y, a_0_y)   
+;CHECK: node GEN_9 = eqv(UInt("h1"), i)
+;CHECK: GEN_3 <= mux(GEN_9, a_1_y, a_0_y)   
 
 ; CHECK: Finished Lower Types
 
diff --git a/test/passes/lower-to-ground/bundle.fir b/test/passes/lower-to-ground/bundle.fir
index b2ea2d63..a8f8ad78 100644
--- a/test/passes/lower-to-ground/bundle.fir
+++ b/test/passes/lower-to-ground/bundle.fir
@@ -4,7 +4,7 @@ circuit top :
    module m :
       input  a : { x : UInt<5>, flip y: SInt<5>}
       output b : { x : UInt<5>, flip y: SInt<5>}
-      a.y <= UInt(0)
+      a.y <= SInt(0)
       b.x <= UInt(0)
    module top :
       input c : { x : UInt<5>[5], flip y : { x : UInt<5>[3], flip y : SInt<5> } }
diff --git a/test/passes/split-exp/split-in-when.fir b/test/passes/split-exp/split-in-when.fir
index a6d0a2c5..06a3cc53 100644
--- a/test/passes/split-exp/split-in-when.fir
+++ b/test/passes/split-exp/split-in-when.fir
@@ -13,12 +13,13 @@ circuit Top :
 
       when bit(subw(a,c),3) : out <= mux(eqv(bits(UInt(32),4,0),UInt(13)),addw(a,addw(b,c)),subw(c,b))
 
-;CHECK: node out_1 = subw(a, c)
-;CHECK: node out_2 = bit(out_1, 3)
-;CHECK: node out_3 = eqv(UInt("h0"), UInt("hd"))
-;CHECK: node out_4 = addw(b, c)
-;CHECK: node out_5 = addw(a, out_4)
-;CHECK: node out_6 = subw(c, b)
-;CHECK: node out_7 = mux(out_3, out_5, out_6)
+;CHECK: node GEN = subw(a, c)
+;CHECK: node GEN_1 = bit(GEN, 3)
+;CHECK: node GEN_2 = eqv(UInt("h0"), UInt("hd"))
+;CHECK: node GEN_3 = addw(b, c)
+;CHECK: node GEN_4 = addw(a, GEN_3)
+;CHECK: node GEN_5 = subw(c, b)
+;CHECK: node GEN_6 = mux(GEN_2, GEN_4, GEN_5)
+;CHECK: out <= mux(GEN_1, GEN_6, out)   
 
 ;CHECK: Finished Split Expressions