Added src and test files

1 files changed, 24 insertions, 0 deletions

diff --git a/test/chirrtl/wacc-wdc.fir b/test/chirrtl/wacc-wdc.fir
new file mode 100644
index 00000000..71b86d70
--- /dev/null
+++ b/test/chirrtl/wacc-wdc.fir
@@ -0,0 +1,24 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
+circuit top :
+   module top :
+      input clk : Clock
+      wire p : UInt
+      cmem m : UInt<4>[10]
+      p <= UInt(1)
+      when p :
+         write mport a = m[UInt(3)],clk
+         a <= UInt(2)
+
+; CHECK: Expand Whens
+
+; CHECK: circuit top :
+; CHECK:   module top :
+; CHECK:     wire p : UInt
+; CHECK:     cmem m : UInt<4>[10], clk
+; CHECK:     write accessor a = m[UInt("h3")]
+; CHECK:     p <= UInt("h1")
+; CHECK:     when p : a <= UInt("h2")
+
+; CHECK: Finished Expand Whens
+
+