diff options
| author | azidar | 2015-09-30 09:28:08 -0700 |
|---|---|---|
| committer | azidar | 2015-09-30 09:28:08 -0700 |
| commit | 4fefd791eed5ede508a7d47a3f21bf7790d05514 (patch) | |
| tree | cd8e2d451037cd6d393ca8c41bb07e8a8fcdfafa /test | |
| parent | 794e5ada06401a79ea5545e80fb7896bd61e9481 (diff) | |
Fixed naming bug where __1 was matching. Caused lots o issues.
Diffstat (limited to 'test')
| -rw-r--r-- | test/passes/expand-whens/reg-and-when.fir | 2 | ||||
| -rw-r--r-- | test/passes/infer-types/primops.fir | 4 | ||||
| -rw-r--r-- | test/passes/split-exp/split-in-when.fir | 4 |
3 files changed, 5 insertions, 5 deletions
diff --git a/test/passes/expand-whens/reg-and-when.fir b/test/passes/expand-whens/reg-and-when.fir index 9d23acf9..ac678b6d 100644 --- a/test/passes/expand-whens/reg-and-when.fir +++ b/test/passes/expand-whens/reg-and-when.fir @@ -1,5 +1,5 @@ ; RUN: firrtl -i %s -o %s.v -X verilog -p cd 2>&1 | tee %s.out ; cat %s.v | FileCheck %s -; CHECK: out_slow_bits <= fromhost_q$deq$valid ? fromhost_q$deq$bits : tohost_q$deq$bits; +; CHECK: out__slow__bits <= fromhost__q$deq$valid ? fromhost__q$deq$bits : tohost__q$deq$bits; circuit Top : module Top : input clock : Clock diff --git a/test/passes/infer-types/primops.fir b/test/passes/infer-types/primops.fir index 94f481f7..ac057c68 100644 --- a/test/passes/infer-types/primops.fir +++ b/test/passes/infer-types/primops.fir @@ -157,10 +157,10 @@ circuit top : node wnot = not(a) ;CHECK: node wnot = not(a@<t:UInt>)@<t:UInt> node unot = not(c) ;CHECK: node unot = not(c@<t:SInt>)@<t:SInt> - node wand_ = and(a, b) ;CHECK: node wand_ = and(a@<t:UInt>, b@<t:UInt>)@<t:UInt> + node WAND = and(a, b) ;CHECK: node WAND = and(a@<t:UInt>, b@<t:UInt>)@<t:UInt> node uand = and(c, d) ;CHECK: node uand = and(c@<t:SInt>, d@<t:SInt>)@<t:SInt> - node wor_ = or(a, b) ;CHECK: node wor_ = or(a@<t:UInt>, b@<t:UInt>)@<t:UInt> + node WOR = or(a, b) ;CHECK: node WOR = or(a@<t:UInt>, b@<t:UInt>)@<t:UInt> node uor = or(c, d) ;CHECK: node uor = or(c@<t:SInt>, d@<t:SInt>)@<t:SInt> node wxor = xor(a, b) ;CHECK: node wxor = xor(a@<t:UInt>, b@<t:UInt>)@<t:UInt> diff --git a/test/passes/split-exp/split-in-when.fir b/test/passes/split-exp/split-in-when.fir index ddf6a155..58819d22 100644 --- a/test/passes/split-exp/split-in-when.fir +++ b/test/passes/split-exp/split-in-when.fir @@ -13,11 +13,11 @@ circuit Top : when bit(subw(a,c),3) : out := mux(eqv(bits(UInt(32),4,0),UInt(13)),addw(a,addw(b,c)),subw(c,b)) -;CHECK: node T = subw(a, c) +;CHECK: node F = subw(a, c) ;CHECK: node out_1 = eqv(UInt("h0"), UInt("hd")) ;CHECK: node out_3 = addw(b, c) ;CHECK: node out_2 = addw(a, out_3) ;CHECK: node out_4 = subw(c, b) -;CHECK: when bit(T, 3) : out := mux(out_1, out_2, out_4) +;CHECK: when bit(F, 3) : out := mux(out_1, out_2, out_4) ;CHECK: Finished Split Expressions |