| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2020-09-16 | Change to Apache 2.0 License (#1901) | Chick Markley | |
| 2020-07-27 | Update RightShiftTests.fir to avoid buggy Counter pattern | Albert Magyar | |
| * See freechipsproject/chisel3#1408 | |||
| 2018-06-28 | Protobuf (#832) | Jack Koenig | |
| Add support for ProtoBuf serialization and deserialization * Add support for additional features in .proto description Features added: Info, Fixed[Type|Literal], AnalogType, Attach, Params * Add support for .pb input files This involves an API change where FIRRTL no longer implicitly adds .fir to input file names | |||
| 2017-06-27 | Emitting reg update mux tree, only walk netlist for wires and nodes | Jack Koenig | |
| Fixes bug where the Verilog emitter could pull the next value for a register that feeds a second register, removing the first register from the second register's update. | |||
| 2016-12-08 | Clk2clock - rename the implicit "clk" module input "clock" (#387) | Jim Lawson | |
| * Rename implict module "clk" input to "clock". This doesn't rename all the "self-contained" test instances. nor the memory "clk" enables, nor the implict module "clk"s in the regress .fir files. * Consistency: rename implict module "clk" input to "clock" in "self-contained" test instances. This doesn't rename the memory "clk" enables, nor the implict module "clk"s in the regress .fir files. | |||
| 2016-08-17 | Change RW port names (#236) | Angie Wang | |
| * Updated FIRRTL spec + related code for readwrite ports. (write) data -> wdata & mask -> wmask for clarity * Also removed simple.fir that snuck into master branch. | |||
| 2016-08-15 | Remove stanza (#231) | Adam Izraelevitz | |
| * Removed stanza implementation/tests. In the future we can move the stanza tests over, but for now they should be deleted. * Added back integration .fir files * Added Makefile to give Travis hooks * Added firrtl script (was ignored before) | |||
| 2016-05-24 | Add integration test for single-ported memory | jackkoenig | |
| 2016-04-08 | Fixed bug in Remove Accesses where a WSubAccess's index was not checked for ↵ | Adam Izraelevitz | |
| accesses. Fixes #105 | |||
| 2016-03-15 | Revamp string literal handling | jackkoenig | |
| 2016-03-10 | Add support for right shift by amount larger than argument width | jackkoenig | |
| 2016-03-03 | Add some integration tests: successful compilation and execution | jackkoenig | |
| 2016-02-24 | Fixed printf bugs in scala and stanza versions. Required special casing ↵ | Adam Izraelevitz | |
| prints in SplitExp, and emitting expressions instead of their toString counterparts | |||
| 2016-02-09 | Merge branch 'master' of github.com:ucb-bar/firrtl | azidar | |
| 2016-02-09 | Added remaining check passes. Ready for open sourcing | azidar | |
| 2016-02-09 | Bug fixes, close to getting correct rocket-firrtl.fir through | azidar | |
| 2016-02-09 | Added Lower Types. | azidar | |
| 2016-02-09 | Added test for UInt/SInts that take strings | azidar | |
| 2016-02-09 | Changed stanza output of UInt/SInt to include widths. Made tests match ↵ | azidar | |
| accordingly | |||
| 2016-02-08 | Escape quotes in strings before emitting as Verilog | Palmer Dabbelt | |
| Without this we get failures with the current rocket-chip, when there are assertions with escaped strings in them. | |||
| 2016-01-29 | Update parser tests to match 0.2.0 spec, Scala FIRRTL passes these tests | Jack | |
| 2016-01-28 | Fixed rdwr and wr to verilog tests | azidar | |
| 2016-01-28 | Fixed bug where subaccess indexes were being classified as female, | azidar | |
| mucking up the chirrtl->firrtl transform. #56. | |||
| 2016-01-28 | Changed rmode to wmode | azidar | |
| 2016-01-28 | Use IsInvalid instead of Poisons in chirrtl -> firrtl transform | azidar | |
| 2016-01-28 | Added tests for previous commit | azidar | |
| 2016-01-28 | Added addw to working ir as an optimized verilog emission | azidar | |
| 2016-01-28 | Fixed bug and updated test for changing mod to rem | azidar | |
| 2016-01-28 | Updated all tests to pass | azidar | |
| 2016-01-28 | Changed register syntax for optional reset and init values | azidar | |
| 2016-01-27 | Reworked readwriter types | azidar | |
| 2016-01-27 | Fixed additional tests and inferring rdwr ports in chirrtl | jackkoenig | |
| 2016-01-25 | Fixed bug where poisons were not being declared | azidar | |
| 2016-01-25 | Added verilog rename pass | azidar | |
| 2016-01-25 | Added isinvalid and validif | azidar | |
| 2016-01-25 | Fixed support for muxes and nodes with passive aggregate types | azidar | |
| 2016-01-25 | Fixed one more test | azidar | |
| 2016-01-25 | Changed tests to pass with change to postfix of generated name | azidar | |
| 2016-01-24 | Fixed tests that broke from changing verilog backend and removing mask from ↵ | azidar | |
| write mport declaration | |||
| 2016-01-24 | Added muxing on passive aggregate types | azidar | |
| 2016-01-24 | Added DefMemory to CInfer Types | azidar | |
| 2016-01-23 | Fixed bug where the write mask wasn't being generated correctly | azidar | |
| 2016-01-23 | Added inference to mports | azidar | |
| 2016-01-23 | Added prefix checker, now compliant with firrtl spec | azidar | |
| 2016-01-23 | Changed chirrtl to not require known mask values | azidar | |
| 2016-01-17 | Fixed error where memory of size 1 would create an index of size 0. This can ↵ | azidar | |
| be fixed in the future with a pass that removes these memories | |||
| 2016-01-17 | Added check for uint on access index type | azidar | |
| 2016-01-17 | BIT-AND, BIT-OR, and BIT-XOR now can accept SInts. Fixed tests | azidar | |
| 2016-01-16 | Added a bunch of tests and added firrtl-stanza and firrtl-scala to .gitignore | azidar | |
| 2016-01-16 | Fixed all tests so they either pass are marked as expected failures | azidar | |
 |
index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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