BIT-AND, BIT-OR, and BIT-XOR now can accept SInts. Fixed tests

3 files changed, 0 insertions, 82 deletions

diff --git a/test/passes/expand-whens/one-when.fir b/test/passes/expand-whens/one-when.fir
deleted file mode 100644
index 6eb341d7..00000000
--- a/test/passes/expand-whens/one-when.fir
+++ /dev/null
@@ -1,40 +0,0 @@
-; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
-; XFAIL: *
-
-; CHECK: Expand Whens
-circuit top :
-   module top :
-      input clk : Clock
-      input reset : UInt<1>
-      mem m : 
-         data-type => UInt<1>
-         depth => 2
-         read-latency => 0
-         write-latency => 1
-      wire i : UInt<1>
-      wire p : UInt<1>
-      wire j : UInt<1>
-      j <= UInt(1)
-      reg r : UInt<1>, clk, reset,i
-
-      p <= j
-      when p :
-        
-        infer accessor a = m[i] 
-        i <= a
-        infer accessor b = m[i]
-        b <= i
-      else :
-        infer accessor c = m[i]
-        i <= c
-        infer accessor d = m[i] 
-        d <= i
-      infer accessor e = m[i]
-      when p :
-        p <= i
-        when e :
-           p <= p
-           r <= p
-        
-
-; CHECK: Finished Expand Whens
diff --git a/test/passes/expand-whens/two-when.fir b/test/passes/expand-whens/two-when.fir
deleted file mode 100644
index 38e02c5e..00000000
--- a/test/passes/expand-whens/two-when.fir
+++ /dev/null
@@ -1,40 +0,0 @@
-; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
-; XFAIL: *
-
-; CHECK: Expand Whens
-circuit top :
-   module top :
-      input clk : Clock
-      cmem m :{ x : UInt<1>, y : UInt<1> }[2], clk
-      wire i : UInt<1>
-      i <= UInt(1)
-      wire p : UInt<1>
-      p <= UInt(1)
-      wire q : { x : UInt<1>, y : UInt<1> }
-      when p :
-        wire p2 : UInt<1>
-        p2 <= UInt(1)
-        when p2 :
-          infer accessor a = m[i] 
-          q <= a
-          infer accessor b = m[i]
-          b <= q
-        else :
-          infer accessor c = m[i] 
-          q <= c
-          infer accessor d = m[i]
-          d <= q
-      else :
-        wire p3 : UInt<1>
-        p3 <= UInt(1)
-        when p3 :
-          infer accessor w = m[i] 
-          q <= w
-          infer accessor x = m[i]
-          x <= q
-        else :
-          infer accessor y = m[i] 
-          q <= y
-          infer accessor z = m[i]
-          z <= q
-; CHECK: Finished Expand Whens
diff --git a/test/passes/infer-types/primops.fir b/test/passes/infer-types/primops.fir
index d2a09367..102a94ae 100644
--- a/test/passes/infer-types/primops.fir
+++ b/test/passes/infer-types/primops.fir
@@ -1,6 +1,4 @@
 ; RUN: firrtl -i %s -o %s.v -X verilog -p ct 2>&1 | tee %s.out | FileCheck %s
-; XFAIL: *
-; TODO Talk to Andrew about bit operations (and, or, etc.) on SInts
 
 ;CHECK: Infer Types
 circuit top :