Added muxing on passive aggregate types

6 files changed, 32 insertions, 6 deletions

diff --git a/test/errors/high-form/NumArgs.fir b/test/errors/high-form/NumArgs.fir
index 6c083905..7db78509 100644
--- a/test/errors/high-form/NumArgs.fir
+++ b/test/errors/high-form/NumArgs.fir
@@ -1,11 +1,9 @@
 ; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
-; CHECK: Primop mux requires 3 expression arguments.
 ; CHECK: Primop add requires 2 expression arguments.
 ; CHECK: Primop bits requires 2 integer arguments.
 
 circuit Top : 
   module Top : 
-    node x = mux(UInt(1),UInt(1))
     node y = add(SInt(1),UInt(1),UInt(1))
     node z = bits(UInt(1),1,2,3)
 
diff --git a/test/errors/type/MuxWithFlips.fir b/test/errors/type/MuxWithFlips.fir
new file mode 100644
index 00000000..9a8b2170
--- /dev/null
+++ b/test/errors/type/MuxWithFlips.fir
@@ -0,0 +1,12 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
+; CHECK: [module Top]  Must mux between passive types.
+; CHECK: [module Top]  A mux condition must be of type UInt.
+
+circuit Top : 
+  module Top : 
+    input c : SInt<1>
+    input x : {x : UInt, flip y : UInt}
+    input y : {x : UInt, flip y : UInt}
+    output z : {x : UInt, flip y : UInt}
+    z <= mux(c,x,y)
+
diff --git a/test/errors/type/NodeWithFlips.fir b/test/errors/type/NodeWithFlips.fir
index 0b8b9e6b..2030955f 100644
--- a/test/errors/type/NodeWithFlips.fir
+++ b/test/errors/type/NodeWithFlips.fir
@@ -1,5 +1,5 @@
 ; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
-; CHECK: Node must be a ground type.
+; CHECK: Node must be a passive type.
 
 circuit Top : 
   module Top : 
diff --git a/test/errors/type/Primop.fir b/test/errors/type/Primop.fir
index f687c754..dcf19935 100644
--- a/test/errors/type/Primop.fir
+++ b/test/errors/type/Primop.fir
@@ -1,7 +1,7 @@
 ; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
-; CHECK: Primop mux requires all operands to have the same type.
+; CHECK: Must mux between equivalent types.
 ; CHECK: Primop add cannot operate on non-ground types.
-; CHECK: Primop mux requires argument SInt("h1") to be a UInt type.
+; CHECK: A mux condition must be of type UInt.
 
 circuit Top : 
   module Top :
diff --git a/test/features/InitAccessor.fir b/test/features/InitAccessor.fir
index 5a81a62e..6261ec01 100644
--- a/test/features/InitAccessor.fir
+++ b/test/features/InitAccessor.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.v -X verilog -p cT 2>&1 | tee %s.out | FileCheck %s
 
 ;CHECK: Done!
 circuit Top : 
diff --git a/test/features/MuxBundle.fir b/test/features/MuxBundle.fir
new file mode 100644
index 00000000..764078d5
--- /dev/null
+++ b/test/features/MuxBundle.fir
@@ -0,0 +1,16 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
+;CHECK: Expand Connects
+circuit Top : 
+  module Top : 
+    input a: {w:UInt<42>,x:UInt<20>}
+    input b: {w:UInt<42>,x:UInt<20>}
+    input c: {w:UInt<42>,x:UInt<20>}
+    input p : UInt<1>
+    output d: {w:UInt<42>,x:UInt<20>}
+    d <= mux(p,mux(p,a,b),c)
+;CHECK: d.w <= mux(p, mux(p, a.w, b.w), c.w)
+;CHECK: d.x <= mux(p, mux(p, a.x, b.x), c.x)   
+
+;CHECK: Finished Expand Connects
+;CHECK: Done!
+