Added verilog rename pass

1 files changed, 18 insertions, 0 deletions

diff --git a/test/features/VerilogRename.fir b/test/features/VerilogRename.fir
new file mode 100644
index 00000000..f8fceaa9
--- /dev/null
+++ b/test/features/VerilogRename.fir
@@ -0,0 +1,18 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
+circuit Top :
+   module Top :
+      input with : Clock
+      output unsigned : Clock
+      wire trireg : Clock
+      unsigned <= with
+      trireg <= with
+
+;CHECK: Verilog Rename
+
+;CHECK: input with$ : Clock
+;CHECK: output unsigned$ : Clock
+;CHECK: wire trireg$ : Clock
+;CHECK: trireg$ <= with$
+;CHECK: unsigned$ <= with$   
+
+;CHECK: Done!