From eeb565de1005927bcfd7bde15bd1d4e09394cb78 Mon Sep 17 00:00:00 2001
From: azidar
Date: Mon, 25 Jan 2016 15:59:59 -0800
Subject: Added verilog rename pass

---
 test/features/VerilogRename.fir | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)
 create mode 100644 test/features/VerilogRename.fir

(limited to 'test')

diff --git a/test/features/VerilogRename.fir b/test/features/VerilogRename.fir
new file mode 100644
index 00000000..f8fceaa9
--- /dev/null
+++ b/test/features/VerilogRename.fir
@@ -0,0 +1,18 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
+circuit Top :
+   module Top :
+      input with : Clock
+      output unsigned : Clock
+      wire trireg : Clock
+      unsigned <= with
+      trireg <= with
+
+;CHECK: Verilog Rename
+
+;CHECK: input with$ : Clock
+;CHECK: output unsigned$ : Clock
+;CHECK: wire trireg$ : Clock
+;CHECK: trireg$ <= with$
+;CHECK: unsigned$ <= with$   
+
+;CHECK: Done!
-- 
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