diff options
| author | Adam Izraelevitz | 2016-08-15 10:32:41 -0700 |
|---|---|---|
| committer | GitHub | 2016-08-15 10:32:41 -0700 |
| commit | bebd04c4c68c320b2b72325e348c726dc33beae6 (patch) | |
| tree | 69f6d4da577977cc7ff428b0545bb4735507aad0 /test | |
| parent | cca37c46fc0848f5dbf5f95ba60755ed6d60712b (diff) | |
Remove stanza (#231)
* Removed stanza implementation/tests.
In the future we can move the stanza tests over, but for now they should
be deleted.
* Added back integration .fir files
* Added Makefile to give Travis hooks
* Added firrtl script (was ignored before)
Diffstat (limited to 'test')
153 files changed, 0 insertions, 5765 deletions
diff --git a/test/chirrtl/infer-mport-dir.fir b/test/chirrtl/infer-mport-dir.fir deleted file mode 100644 index 50baeff2..00000000 --- a/test/chirrtl/infer-mport-dir.fir +++ /dev/null @@ -1,22 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; CHECK: Done! -circuit top : - module top : - input clk : Clock - wire p : UInt - wire q : UInt - cmem m : {a:UInt<4>,b:UInt<4>}[10] - p <= UInt(1) - q <= UInt(1) - wire x : {a:UInt<4>,b:UInt<4>} - x.a <= UInt(1) - x.b <= UInt(1) - when p : - infer mport a = m[UInt(3)],clk - infer mport b = m[UInt(3)],clk - infer mport c = m[UInt(3)],clk - when q : - a <= x - x <= b - c <= x - x <= c diff --git a/test/chirrtl/mask-bug.fir b/test/chirrtl/mask-bug.fir deleted file mode 100644 index b580c075..00000000 --- a/test/chirrtl/mask-bug.fir +++ /dev/null @@ -1,20 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; CHECK: Done! -circuit top : - module top : - input clk : Clock - wire p : UInt - wire q : UInt - cmem m : {a:UInt<4>,b:{c: UInt<4>,d:UInt<4>}}[10] - p <= UInt(1) - q <= UInt(1) - wire x : {a:UInt<4>,b:{c: UInt<4>,d:UInt<4>}} - x.a <= UInt(1) - x.b.c <= UInt(1) - x.b.d <= UInt(1) - when p : - write mport a = m[UInt(3)],clk - when q : - a <- x - - diff --git a/test/chirrtl/wacc-wdc.fir b/test/chirrtl/wacc-wdc.fir deleted file mode 100644 index 3cb5141d..00000000 --- a/test/chirrtl/wacc-wdc.fir +++ /dev/null @@ -1,54 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -circuit top : - module top : - input clk : Clock - wire p : UInt - wire q : UInt - cmem m : {a:UInt<4>,b:UInt<4>}[10] - p <= UInt(1) - q <= UInt(1) - wire x : {a:UInt<4>,b:UInt<4>} - x.a <= UInt(1) - x.b <= UInt(1) - when p : - write mport a = m[UInt(3)],clk - when q : - a <= x - - -; CHECK: Remove CHIRRTL - -; CHECK: circuit top : -; CHECK: module top : -; CHECK: input clk : Clock -; CHECK: wire p : UInt -; CHECK: wire q : UInt -; CHECK: mem m : -; CHECK: data-type => { a : UInt<4>, b : UInt<4>} -; CHECK: depth => 10 -; CHECK: write-latency => 1 -; CHECK: read-latency => 0 -; CHECK: writer => a -; CHECK: m.a.addr is invalid -; CHECK: m.a.clk <= clk -; CHECK: m.a.en <= UInt<1>("h0") -; CHECK: m.a.data is invalid -; CHECK: m.a.mask.a <= UInt<1>("h0") -; CHECK: m.a.mask.b <= UInt<1>("h0") -; CHECK: p <= UInt<1>("h1") -; CHECK: q <= UInt<1>("h1") -; CHECK: wire x : { a : UInt<4>, b : UInt<4>} -; CHECK: x.a <= UInt<1>("h1") -; CHECK: x.b <= UInt<1>("h1") -; CHECK: when p : -; CHECK: m.a.addr <= UInt<2>("h3") -; CHECK: m.a.en <= UInt<1>("h1") -; CHECK: when q : -; CHECK: m.a.data <= x -; CHECK: m.a.mask.a <= UInt<1>("h1") -; CHECK: m.a.mask.b <= UInt<1>("h1") - -; CHECK: Finished Remove CHIRRTL -; CHECK: Done! - - diff --git a/test/custom/when-coverage/gcd.fir b/test/custom/when-coverage/gcd.fir deleted file mode 100644 index b07c313b..00000000 --- a/test/custom/when-coverage/gcd.fir +++ /dev/null @@ -1,52 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilute -s coverage -s when-scope -p c 2>&1 | tee %s.out | FileCheck %s -; XFAIL: * - -;CHECK: Verilog -circuit top : - module subtracter : - input x : UInt - input y : UInt - output q : UInt - q <= subw(x, y) - module gcd : - input a : UInt<16> - input b : UInt<16> - input e : UInt<1> - input clk : Clock - input reset : UInt<1> - output z : UInt<16> - output v : UInt<1> - reg x : UInt,clk,reset - reg y : UInt,clk,reset - onreset x <= UInt(0) - onreset y <= UInt(42) - when gt(x, y) : - inst s of subtracter - s.x <= x - s.y <= y - x <= s.q - else : - inst s2 of subtracter - s2.x <= x - s2.y <= y - y <= s2.q - when e : - x <= a - y <= b - v <= eqv(v, UInt(0)) - z <= x - module top : - input a : UInt<16> - input b : UInt<16> - input clk : Clock - input reset : UInt<1> - output z : UInt - inst i of gcd - i.a <= a - i.b <= b - i.e <= UInt(1) - i.clk <= clk - i.reset <= reset - z <= i.z -;CHECK: Done! - diff --git a/test/errors/gender/BulkWrong.fir b/test/errors/gender/BulkWrong.fir deleted file mode 100644 index c9b24aa2..00000000 --- a/test/errors/gender/BulkWrong.fir +++ /dev/null @@ -1,26 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; CHECK: Expression in is used as a sink but can only be used as a source. -; CHECK: Expression out.y is used as a sink but can only be used as a source. -; CHECK: Expression in.y.z is used as a sink but can only be used as a source. -; CHECK: Expression in.y.z is used as a sink but can only be used as a source. - -circuit BTB : - module BTB : - input in : {x : UInt<1>, flip y : {flip z : UInt<1>}} - output out : {x : UInt<1>, flip y : {flip z : UInt<1>}} - - in <- out - out.y <- in.y - out.y.z <- in.y.z - - wire w : {x : UInt<1>, flip y : {flip z : UInt<1>}} - w <- in - in.y <- w.y - in.y.z <- w.y.z - - w.x <= add(in.x,in.y.z) - - out <- in - in.y <- out.y - in.y.z <- out.y.z - diff --git a/test/errors/gender/InstancePorts.fir b/test/errors/gender/InstancePorts.fir deleted file mode 100644 index 3f5ae8c7..00000000 --- a/test/errors/gender/InstancePorts.fir +++ /dev/null @@ -1,17 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; CHECK-NOT: Expression queue.in is used as a sink but can only be used as a source. -; CHECK: Done! - -circuit BTB : - module Queue : - input in : UInt<1> - output out : UInt<1> - out <= in - module BTB : - input time : UInt<1> - output out : UInt<1> - - inst queue of Queue - queue.in <= time - out <= queue.in - diff --git a/test/errors/gender/ReadOutput.fir b/test/errors/gender/ReadOutput.fir deleted file mode 100644 index f9e8f7b4..00000000 --- a/test/errors/gender/ReadOutput.fir +++ /dev/null @@ -1,12 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; CHECK: Expression out is used as a source but can only be used as a sink. - -circuit BTB : - module BTB : - output out : {x : UInt<1>, flip y : UInt<1>} - - wire w : {x : UInt<1>, flip y : UInt<1>} - w.x <= UInt(1) - w.y <= UInt(1) - out.x <= UInt(1) - w <- out diff --git a/test/errors/gender/bad_bulk_connect.fir b/test/errors/gender/bad_bulk_connect.fir deleted file mode 100644 index 984d8da0..00000000 --- a/test/errors/gender/bad_bulk_connect.fir +++ /dev/null @@ -1,328 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; CHECK: Expression out.grant is used as a sink but can only be used as a source. - -circuit ClientTileLinkIOWrapper_49 : - module ClientTileLinkIOWrapper_49 : - input clock : Clock - input reset : UInt<1> - input in : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}} - output out : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}} - - in.grant.bits.g_type <= UInt<1>("h00") - in.grant.bits.is_builtin_type <= UInt<1>("h00") - in.grant.bits.manager_xact_id <= UInt<1>("h00") - in.grant.bits.client_xact_id <= UInt<1>("h00") - in.grant.bits.data <= UInt<1>("h00") - in.grant.bits.addr_beat <= UInt<1>("h00") - in.grant.valid <= UInt<1>("h00") - in.acquire.ready <= UInt<1>("h00") - out.release.bits.voluntary <= UInt<1>("h00") - out.release.bits.r_type <= UInt<1>("h00") - out.release.bits.data <= UInt<1>("h00") - out.release.bits.addr_beat <= UInt<1>("h00") - out.release.bits.client_xact_id <= UInt<1>("h00") - out.release.bits.addr_block <= UInt<1>("h00") - out.release.valid <= UInt<1>("h00") - out.probe.ready <= UInt<1>("h00") - out.grant.ready <= UInt<1>("h00") - out.acquire.bits.union <= UInt<1>("h00") - out.acquire.bits.a_type <= UInt<1>("h00") - out.acquire.bits.is_builtin_type <= UInt<1>("h00") - out.acquire.bits.data <= UInt<1>("h00") - out.acquire.bits.addr_beat <= UInt<1>("h00") - out.acquire.bits.client_xact_id <= UInt<1>("h00") - out.acquire.bits.addr_block <= UInt<1>("h00") - out.acquire.valid <= UInt<1>("h00") - - wire T_173394 : UInt<2>[2] - T_173394[0] <= UInt<2>("h01") - T_173394[1] <= UInt<2>("h02") - wire T_173397 : UInt<2>[2] - T_173397[0] <= UInt<2>("h01") - T_173397[1] <= UInt<2>("h02") - wire T_173399 : UInt<2>[1] - T_173399[0] <= UInt<2>("h02") - wire T_173439 : UInt<2>[2] - T_173439[0] <= UInt<2>("h01") - T_173439[1] <= UInt<2>("h02") - wire T_173442 : UInt<2>[2] - T_173442[0] <= UInt<2>("h01") - T_173442[1] <= UInt<2>("h02") - wire T_173444 : UInt<2>[1] - T_173444[0] <= UInt<2>("h02") - wire T_173483 : UInt<2>[2] - T_173483[0] <= UInt<2>("h01") - T_173483[1] <= UInt<2>("h02") - wire T_173486 : UInt<2>[2] - T_173486[0] <= UInt<2>("h01") - T_173486[1] <= UInt<2>("h02") - wire T_173488 : UInt<2>[1] - T_173488[0] <= UInt<2>("h02") - wire T_173537 : UInt<2>[2] - T_173537[0] <= UInt<2>("h01") - T_173537[1] <= UInt<2>("h02") - wire T_173540 : UInt<2>[2] - T_173540[0] <= UInt<2>("h01") - T_173540[1] <= UInt<2>("h02") - wire T_173542 : UInt<2>[1] - T_173542[0] <= UInt<2>("h02") - wire T_173588 : UInt<2>[2] - T_173588[0] <= UInt<2>("h01") - T_173588[1] <= UInt<2>("h02") - wire T_173591 : UInt<2>[2] - T_173591[0] <= UInt<2>("h01") - T_173591[1] <= UInt<2>("h02") - wire T_173593 : UInt<2>[1] - T_173593[0] <= UInt<2>("h02") - wire T_173639 : UInt<2>[2] - T_173639[0] <= UInt<2>("h01") - T_173639[1] <= UInt<2>("h02") - wire T_173642 : UInt<2>[2] - T_173642[0] <= UInt<2>("h01") - T_173642[1] <= UInt<2>("h02") - wire T_173644 : UInt<2>[1] - T_173644[0] <= UInt<2>("h02") - wire T_173692 : UInt<2>[2] - T_173692[0] <= UInt<2>("h01") - T_173692[1] <= UInt<2>("h02") - wire T_173695 : UInt<2>[2] - T_173695[0] <= UInt<2>("h01") - T_173695[1] <= UInt<2>("h02") - wire T_173697 : UInt<2>[1] - T_173697[0] <= UInt<2>("h02") - wire T_173742 : UInt<2>[2] - T_173742[0] <= UInt<2>("h01") - T_173742[1] <= UInt<2>("h02") - wire T_173745 : UInt<2>[2] - T_173745[0] <= UInt<2>("h01") - T_173745[1] <= UInt<2>("h02") - wire T_173747 : UInt<2>[1] - T_173747[0] <= UInt<2>("h02") - wire T_173795 : UInt<2>[2] - T_173795[0] <= UInt<2>("h01") - T_173795[1] <= UInt<2>("h02") - wire T_173798 : UInt<2>[2] - T_173798[0] <= UInt<2>("h01") - T_173798[1] <= UInt<2>("h02") - wire T_173800 : UInt<2>[1] - T_173800[0] <= UInt<2>("h02") - wire T_173845 : UInt<2>[2] - T_173845[0] <= UInt<2>("h01") - T_173845[1] <= UInt<2>("h02") - wire T_173848 : UInt<2>[2] - T_173848[0] <= UInt<2>("h01") - T_173848[1] <= UInt<2>("h02") - wire T_173850 : UInt<2>[1] - T_173850[0] <= UInt<2>("h02") - wire T_173895 : UInt<2>[2] - T_173895[0] <= UInt<2>("h01") - T_173895[1] <= UInt<2>("h02") - wire T_173898 : UInt<2>[2] - T_173898[0] <= UInt<2>("h01") - T_173898[1] <= UInt<2>("h02") - wire T_173900 : UInt<2>[1] - T_173900[0] <= UInt<2>("h02") - wire T_173939 : UInt<2>[2] - T_173939[0] <= UInt<2>("h01") - T_173939[1] <= UInt<2>("h02") - wire T_173942 : UInt<2>[2] - T_173942[0] <= UInt<2>("h01") - T_173942[1] <= UInt<2>("h02") - wire T_173944 : UInt<2>[1] - T_173944[0] <= UInt<2>("h02") - wire T_173993 : UInt<2>[2] - T_173993[0] <= UInt<2>("h01") - T_173993[1] <= UInt<2>("h02") - wire T_173996 : UInt<2>[2] - T_173996[0] <= UInt<2>("h01") - T_173996[1] <= UInt<2>("h02") - wire T_173998 : UInt<2>[1] - T_173998[0] <= UInt<2>("h02") - wire T_174044 : UInt<2>[2] - T_174044[0] <= UInt<2>("h01") - T_174044[1] <= UInt<2>("h02") - wire T_174047 : UInt<2>[2] - T_174047[0] <= UInt<2>("h01") - T_174047[1] <= UInt<2>("h02") - wire T_174049 : UInt<2>[1] - T_174049[0] <= UInt<2>("h02") - wire T_174095 : UInt<2>[2] - T_174095[0] <= UInt<2>("h01") - T_174095[1] <= UInt<2>("h02") - wire T_174098 : UInt<2>[2] - T_174098[0] <= UInt<2>("h01") - T_174098[1] <= UInt<2>("h02") - wire T_174100 : UInt<2>[1] - T_174100[0] <= UInt<2>("h02") - wire T_174148 : UInt<2>[2] - T_174148[0] <= UInt<2>("h01") - T_174148[1] <= UInt<2>("h02") - wire T_174151 : UInt<2>[2] - T_174151[0] <= UInt<2>("h01") - T_174151[1] <= UInt<2>("h02") - wire T_174153 : UInt<2>[1] - T_174153[0] <= UInt<2>("h02") - wire T_174198 : UInt<2>[2] - T_174198[0] <= UInt<2>("h01") - T_174198[1] <= UInt<2>("h02") - wire T_174201 : UInt<2>[2] - T_174201[0] <= UInt<2>("h01") - T_174201[1] <= UInt<2>("h02") - wire T_174203 : UInt<2>[1] - T_174203[0] <= UInt<2>("h02") - wire T_174251 : UInt<2>[2] - T_174251[0] <= UInt<2>("h01") - T_174251[1] <= UInt<2>("h02") - wire T_174254 : UInt<2>[2] - T_174254[0] <= UInt<2>("h01") - T_174254[1] <= UInt<2>("h02") - wire T_174256 : UInt<2>[1] - T_174256[0] <= UInt<2>("h02") - wire T_174301 : UInt<2>[2] - T_174301[0] <= UInt<2>("h01") - T_174301[1] <= UInt<2>("h02") - wire T_174304 : UInt<2>[2] - T_174304[0] <= UInt<2>("h01") - T_174304[1] <= UInt<2>("h02") - wire T_174306 : UInt<2>[1] - T_174306[0] <= UInt<2>("h02") - wire T_174351 : UInt<2>[2] - T_174351[0] <= UInt<2>("h01") - T_174351[1] <= UInt<2>("h02") - wire T_174354 : UInt<2>[2] - T_174354[0] <= UInt<2>("h01") - T_174354[1] <= UInt<2>("h02") - wire T_174356 : UInt<2>[1] - T_174356[0] <= UInt<2>("h02") - wire T_174395 : UInt<2>[2] - T_174395[0] <= UInt<2>("h01") - T_174395[1] <= UInt<2>("h02") - wire T_174398 : UInt<2>[2] - T_174398[0] <= UInt<2>("h01") - T_174398[1] <= UInt<2>("h02") - wire T_174400 : UInt<2>[1] - T_174400[0] <= UInt<2>("h02") - wire T_174449 : UInt<2>[2] - T_174449[0] <= UInt<2>("h01") - T_174449[1] <= UInt<2>("h02") - wire T_174452 : UInt<2>[2] - T_174452[0] <= UInt<2>("h01") - T_174452[1] <= UInt<2>("h02") - wire T_174454 : UInt<2>[1] - T_174454[0] <= UInt<2>("h02") - wire T_174500 : UInt<2>[2] - T_174500[0] <= UInt<2>("h01") - T_174500[1] <= UInt<2>("h02") - wire T_174503 : UInt<2>[2] - T_174503[0] <= UInt<2>("h01") - T_174503[1] <= UInt<2>("h02") - wire T_174505 : UInt<2>[1] - T_174505[0] <= UInt<2>("h02") - wire T_174551 : UInt<2>[2] - T_174551[0] <= UInt<2>("h01") - T_174551[1] <= UInt<2>("h02") - wire T_174554 : UInt<2>[2] - T_174554[0] <= UInt<2>("h01") - T_174554[1] <= UInt<2>("h02") - wire T_174556 : UInt<2>[1] - T_174556[0] <= UInt<2>("h02") - wire T_174604 : UInt<2>[2] - T_174604[0] <= UInt<2>("h01") - T_174604[1] <= UInt<2>("h02") - wire T_174607 : UInt<2>[2] - T_174607[0] <= UInt<2>("h01") - T_174607[1] <= UInt<2>("h02") - wire T_174609 : UInt<2>[1] - T_174609[0] <= UInt<2>("h02") - wire T_174654 : UInt<2>[2] - T_174654[0] <= UInt<2>("h01") - T_174654[1] <= UInt<2>("h02") - wire T_174657 : UInt<2>[2] - T_174657[0] <= UInt<2>("h01") - T_174657[1] <= UInt<2>("h02") - wire T_174659 : UInt<2>[1] - T_174659[0] <= UInt<2>("h02") - wire T_174707 : UInt<2>[2] - T_174707[0] <= UInt<2>("h01") - T_174707[1] <= UInt<2>("h02") - wire T_174710 : UInt<2>[2] - T_174710[0] <= UInt<2>("h01") - T_174710[1] <= UInt<2>("h02") - wire T_174712 : UInt<2>[1] - T_174712[0] <= UInt<2>("h02") - wire T_174757 : UInt<2>[2] - T_174757[0] <= UInt<2>("h01") - T_174757[1] <= UInt<2>("h02") - wire T_174760 : UInt<2>[2] - T_174760[0] <= UInt<2>("h01") - T_174760[1] <= UInt<2>("h02") - wire T_174762 : UInt<2>[1] - T_174762[0] <= UInt<2>("h02") - wire T_174807 : UInt<2>[2] - T_174807[0] <= UInt<2>("h01") - T_174807[1] <= UInt<2>("h02") - wire T_174810 : UInt<2>[2] - T_174810[0] <= UInt<2>("h01") - T_174810[1] <= UInt<2>("h02") - wire T_174812 : UInt<2>[1] - T_174812[0] <= UInt<2>("h02") - wire T_174856 : UInt<2>[2] - T_174856[0] <= UInt<2>("h01") - T_174856[1] <= UInt<2>("h02") - wire T_174859 : UInt<2>[2] - T_174859[0] <= UInt<2>("h01") - T_174859[1] <= UInt<2>("h02") - wire T_174861 : UInt<2>[1] - T_174861[0] <= UInt<2>("h02") - wire T_174902 : UInt<2>[2] - T_174902[0] <= UInt<2>("h01") - T_174902[1] <= UInt<2>("h02") - wire T_174905 : UInt<2>[2] - T_174905[0] <= UInt<2>("h01") - T_174905[1] <= UInt<2>("h02") - wire T_174907 : UInt<2>[1] - T_174907[0] <= UInt<2>("h02") - wire T_174951 : UInt<2>[2] - T_174951[0] <= UInt<2>("h01") - T_174951[1] <= UInt<2>("h02") - wire T_174954 : UInt<2>[2] - T_174954[0] <= UInt<2>("h01") - T_174954[1] <= UInt<2>("h02") - wire T_174956 : UInt<2>[1] - T_174956[0] <= UInt<2>("h02") - wire T_174997 : UInt<2>[2] - T_174997[0] <= UInt<2>("h01") - T_174997[1] <= UInt<2>("h02") - wire T_175000 : UInt<2>[2] - T_175000[0] <= UInt<2>("h01") - T_175000[1] <= UInt<2>("h02") - wire T_175002 : UInt<2>[1] - T_175002[0] <= UInt<2>("h02") - wire T_175043 : UInt<2>[2] - T_175043[0] <= UInt<2>("h01") - T_175043[1] <= UInt<2>("h02") - wire T_175046 : UInt<2>[2] - T_175046[0] <= UInt<2>("h01") - T_175046[1] <= UInt<2>("h02") - wire T_175048 : UInt<2>[1] - T_175048[0] <= UInt<2>("h02") - wire T_175096 : UInt<2>[2] - T_175096[0] <= UInt<2>("h01") - T_175096[1] <= UInt<2>("h02") - wire T_175099 : UInt<2>[2] - T_175099[0] <= UInt<2>("h01") - T_175099[1] <= UInt<2>("h02") - wire T_175101 : UInt<2>[1] - T_175101[0] <= UInt<2>("h02") - wire T_175146 : UInt<2>[2] - T_175146[0] <= UInt<2>("h01") - T_175146[1] <= UInt<2>("h02") - wire T_175149 : UInt<2>[2] - T_175149[0] <= UInt<2>("h01") - T_175149[1] <= UInt<2>("h02") - wire T_175151 : UInt<2>[1] - T_175151[0] <= UInt<2>("h02") - out.acquire <- in.acquire - out.grant <- in.grant - out.probe.ready <= UInt<1>("h01") - out.release.valid <= UInt<1>("h00") diff --git a/test/errors/high-form/Flip-Mem.fir b/test/errors/high-form/Flip-Mem.fir deleted file mode 100644 index a8cb67ca..00000000 --- a/test/errors/high-form/Flip-Mem.fir +++ /dev/null @@ -1,12 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; CHECK: Memory mc cannot be a bundle type with flips. - -circuit Flip-Mem : - module Flip-Mem : - input clk : Clock - mem mc : - depth => 10 - data-type => {x : UInt<3>, flip y : UInt<5>} - write-latency => 1 - read-latency => 0 - ;smem ms : {x : UInt<3>, flip y : UInt<5>}[10], clk diff --git a/test/errors/high-form/Flip-Poison.fir b/test/errors/high-form/Flip-Poison.fir deleted file mode 100644 index 278d3b74..00000000 --- a/test/errors/high-form/Flip-Poison.fir +++ /dev/null @@ -1,8 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; CHECK: Poison p cannot be a bundle type with flips. - -circuit Flip-Poison : - module Flip-Poison : - input clk : Clock - poison p : {x : UInt<10>, flip y : UInt<10>} - diff --git a/test/errors/high-form/InstanceNotModule.fir b/test/errors/high-form/InstanceNotModule.fir deleted file mode 100644 index aa49b26b..00000000 --- a/test/errors/high-form/InstanceNotModule.fir +++ /dev/null @@ -1,8 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; CHECK: Module Top2 is not defined. - -circuit Top : - module Top : - wire x : UInt<1> - inst t of Top2 - diff --git a/test/errors/high-form/InvalidLOC.fir b/test/errors/high-form/InvalidLOC.fir deleted file mode 100644 index 8329cc02..00000000 --- a/test/errors/high-form/InvalidLOC.fir +++ /dev/null @@ -1,12 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; CHECK: Invalid connect to an expression that is not a reference or a WritePort. -; CHECK: Invalid connect to an expression that is not a reference or a WritePort. -; CHECK: Invalid connect to an expression that is not a reference or a WritePort. - -circuit Top : - module Top : - wire x : UInt - add(x,x) <= UInt(1) - UInt(1) <= UInt(1) - SInt(1) <= UInt(1) - diff --git a/test/errors/high-form/InvalidSubexp.fir b/test/errors/high-form/InvalidSubexp.fir deleted file mode 100644 index d0ad34c0..00000000 --- a/test/errors/high-form/InvalidSubexp.fir +++ /dev/null @@ -1,9 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; CHECK: Invalid access to non-reference. -; CHECK: Invalid access to non-reference. - -circuit Top : - module Top : - wire x : UInt<4> - add(x,x)[10] <= UInt(1) - add(x,x).x <= UInt(1) diff --git a/test/errors/high-form/NegUInt.fir b/test/errors/high-form/NegUInt.fir deleted file mode 100644 index 8249f791..00000000 --- a/test/errors/high-form/NegUInt.fir +++ /dev/null @@ -1,7 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; CHECK: UIntValue cannot be negative. - -circuit Top : - module Top : - wire x : UInt<4> - x <= UInt(-2) diff --git a/test/errors/high-form/NegVecSize.fir b/test/errors/high-form/NegVecSize.fir deleted file mode 100644 index 8a89d4e6..00000000 --- a/test/errors/high-form/NegVecSize.fir +++ /dev/null @@ -1,7 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; CHECK: Vector type size cannot be negative - -circuit Top : - module Top : - wire x : UInt<3>[-5] - diff --git a/test/errors/high-form/NegWidth.fir b/test/errors/high-form/NegWidth.fir deleted file mode 100644 index 1eb54a34..00000000 --- a/test/errors/high-form/NegWidth.fir +++ /dev/null @@ -1,7 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; CHECK: Width cannot be negative or zero. - -circuit Top : - module Top : - wire x : UInt<-3> - diff --git a/test/errors/high-form/NumArgs.fir b/test/errors/high-form/NumArgs.fir deleted file mode 100644 index 7db78509..00000000 --- a/test/errors/high-form/NumArgs.fir +++ /dev/null @@ -1,9 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; CHECK: Primop add requires 2 expression arguments. -; CHECK: Primop bits requires 2 integer arguments. - -circuit Top : - module Top : - node y = add(SInt(1),UInt(1),UInt(1)) - node z = bits(UInt(1),1,2,3) - diff --git a/test/errors/high-form/Prefix.fir b/test/errors/high-form/Prefix.fir deleted file mode 100644 index ba4a28a2..00000000 --- a/test/errors/high-form/Prefix.fir +++ /dev/null @@ -1,9 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; CHECK: Symbol x$z$y is a prefix. - -circuit Top : - module Top : - wire x : UInt<2> - wire x$z$y : UInt<1> - - diff --git a/test/errors/high-form/Printf.fir b/test/errors/high-form/Printf.fir deleted file mode 100644 index 5580182b..00000000 --- a/test/errors/high-form/Printf.fir +++ /dev/null @@ -1,16 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s - -circuit Top : - module Top : - input x : {y : UInt<1>} - input p : UInt<1> - input clk : Clock - printf(clk,p,"Hello World%!\n",x) - printf(clk,p,"Hello World%") - printf(clk,p,"Hello World%d %s %h %x",x,x,x) - -;CHECK: Bad printf format: "%!" -;CHECK: Bad printf format: trailing "%" -;CHECK: Bad printf format: incorrect number of arguments -;CHECK: Bad printf format: "%h" -;CHECK: Bad printf format: incorrect number of arguments diff --git a/test/errors/high-form/RemoveChar.fir b/test/errors/high-form/RemoveChar.fir deleted file mode 100644 index aa5e8227..00000000 --- a/test/errors/high-form/RemoveChar.fir +++ /dev/null @@ -1,12 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; CHECK: Done! - -circuit Top : - module Top : - wire x_1 : UInt<1> - x_1 <= UInt(1) - wire x : UInt<1> - x <= add(add(UInt(1),UInt(1)),UInt(1)) - - - diff --git a/test/errors/high-form/RemoveScope.fir b/test/errors/high-form/RemoveScope.fir deleted file mode 100644 index 63dfb4de..00000000 --- a/test/errors/high-form/RemoveScope.fir +++ /dev/null @@ -1,18 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; XFAIL: * -; CHECK: Done! - -circuit Top : - module Top : - wire x : UInt<1> - node p = UInt(1) - when p : - wire x : UInt<1> - x <= UInt(1) - node y = add(x,UInt(1)) - else : - wire x : UInt<1> - x <= UInt(1) - node z = add(x,UInt(1)) - x <= UInt(1) - node w = add(x,UInt(1)) diff --git a/test/errors/high-form/SpecialChars.fir b/test/errors/high-form/SpecialChars.fir deleted file mode 100644 index 85911c06..00000000 --- a/test/errors/high-form/SpecialChars.fir +++ /dev/null @@ -1,35 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; CHECK: Done! - -circuit Top : - module Top : - wire x : UInt<1> - x <= UInt(1) - wire x~y : UInt<2> - x~y <= UInt(1) - wire x!y : UInt<2> - x!y <= UInt(1) - wire x@y : UInt<2> - x@y <= UInt(1) - wire x#y : UInt<2> - x#y <= UInt(1) - wire x%y : UInt<2> - x%y <= UInt(1) - wire x^y : UInt<2> - x^y <= UInt(1) - wire x*y : UInt<2> - x*y <= UInt(1) - wire x-y : UInt<2> - x-y <= UInt(1) - wire x_y : UInt<2> - x_y <= UInt(1) - wire x+y : UInt<2> - x+y <= UInt(1) - wire x=y : UInt<2> - x=y <= UInt(1) - wire x?y : UInt<2> - x?y <= UInt(1) - wire x/y : UInt<2> - x/y <= UInt(1) - - diff --git a/test/errors/high-form/Top.fir b/test/errors/high-form/Top.fir deleted file mode 100644 index ddeb9c3b..00000000 --- a/test/errors/high-form/Top.fir +++ /dev/null @@ -1,9 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s - -; CHECK: A single module must be named Top. - -circuit Top : - module Top1 : - wire x : UInt<1> - module Top2 : - wire x : UInt<1> diff --git a/test/errors/high-form/Unique.fir b/test/errors/high-form/Unique.fir deleted file mode 100644 index 60201b92..00000000 --- a/test/errors/high-form/Unique.fir +++ /dev/null @@ -1,16 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s - -; CHECK: Reference x does not have a unique name. -; CHECK: Reference p does not have a unique name. -; CHECK-NOT: Reference q does not have a unique name. - -circuit Top : - module Top : - wire x : UInt<1> - wire x : UInt<2> - wire p : UInt<3> - wire q : UInt<3> - when p : - wire p : UInt<4> - module Other : - wire q : UInt<3> diff --git a/test/errors/init/Output.fir b/test/errors/init/Output.fir deleted file mode 100644 index 0b7a7f80..00000000 --- a/test/errors/init/Output.fir +++ /dev/null @@ -1,10 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; CHECK: Reference y is not fully initialized. - -circuit Top : - module Top : - input clk : Clock - wire y : UInt<1> - - when UInt(0) : - y <= UInt(1) diff --git a/test/errors/parser/InstanceNotRef.fir b/test/errors/parser/InstanceNotRef.fir deleted file mode 100644 index 0760f168..00000000 --- a/test/errors/parser/InstanceNotRef.fir +++ /dev/null @@ -1,8 +0,0 @@ -; RUN: firrtl -i %s -o %s.flo -x X -p c | tee %s.out | FileCheck %s -; CHECK: FIRRTL Parsing Error: Expected a statement here. - -circuit Top : - module Top : - wire x : UInt<1> - inst t of add(UInt(1),UInt(1)) - diff --git a/test/errors/parser/Nested-Module.fir b/test/errors/parser/Nested-Module.fir deleted file mode 100644 index 3f06db76..00000000 --- a/test/errors/parser/Nested-Module.fir +++ /dev/null @@ -1,6 +0,0 @@ -; RUN: firrtl -i %s -o %s.flo -x X -p c | tee %s.out | FileCheck %s -; CHECK: FIRRTL Parsing Error: Expected a statement here. - -circuit Nested-Module : - module Top : - module Child : diff --git a/test/errors/parser/Statements-in-Circuit.fir b/test/errors/parser/Statements-in-Circuit.fir deleted file mode 100644 index 5f675e82..00000000 --- a/test/errors/parser/Statements-in-Circuit.fir +++ /dev/null @@ -1,5 +0,0 @@ -; RUN: firrtl -i %s -o %s.flo -x X -p c | tee %s.out | FileCheck %s -; CHECK: FIRRTL Parsing Error: Expected a module declaration here. - -circuit Statement-in-Circuit : - node x : UInt(1) diff --git a/test/errors/type/AccessIndexUInt.fir b/test/errors/type/AccessIndexUInt.fir deleted file mode 100644 index d47bb7c6..00000000 --- a/test/errors/type/AccessIndexUInt.fir +++ /dev/null @@ -1,8 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: AccessIndexUInt.fir@8.4: [module Top] Access index must be a UInt type. -circuit Top : - module Top : - input b : UInt<32>[62] - input a : SInt<8> - output c : UInt<32> - c <= b[a] diff --git a/test/errors/type/BulkConnect.fir b/test/errors/type/BulkConnect.fir deleted file mode 100644 index 26f5c156..00000000 --- a/test/errors/type/BulkConnect.fir +++ /dev/null @@ -1,32 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: BulkConnect.fir@10.4: [module Top] Type mismatch. -;CHECK: BulkConnect.fir@14.4: [module Top] Type mismatch. -;CHECK: BulkConnect.fir@26.4: [module Top] Type mismatch. -;CHECK: BulkConnect.fir@30.4: [module Top] Type mismatch. -circuit Top : - module Top : - wire a : { w : UInt<42>} - wire b : { w : SInt<42>} - a <- b - - wire c : { w : UInt<10>} - wire d : { flip w : UInt<12> } - c <- d - - wire e : { w : UInt<10>} - wire f : { x : UInt<12> } - e <- f - - wire g : { w : { y : UInt<10> }} - wire h : { w : { x : UInt<12> }} - g <- h - - wire i : { w : { flip y : UInt<10> }} - wire j : { w : { y : UInt<12> }} - i <- j - - wire k : { w : { y : SInt<10> }} - wire l : { w : { y : UInt<12> }} - k <- l - - diff --git a/test/errors/type/MuxWithFlips.fir b/test/errors/type/MuxWithFlips.fir deleted file mode 100644 index 9a8b2170..00000000 --- a/test/errors/type/MuxWithFlips.fir +++ /dev/null @@ -1,12 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; CHECK: [module Top] Must mux between passive types. -; CHECK: [module Top] A mux condition must be of type UInt. - -circuit Top : - module Top : - input c : SInt<1> - input x : {x : UInt, flip y : UInt} - input y : {x : UInt, flip y : UInt} - output z : {x : UInt, flip y : UInt} - z <= mux(c,x,y) - diff --git a/test/errors/type/NodeWithFlips.fir b/test/errors/type/NodeWithFlips.fir deleted file mode 100644 index 2030955f..00000000 --- a/test/errors/type/NodeWithFlips.fir +++ /dev/null @@ -1,8 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; CHECK: Node must be a passive type. - -circuit Top : - module Top : - wire x : {x : UInt, flip y : UInt} - node z = x - diff --git a/test/errors/type/Primop.fir b/test/errors/type/Primop.fir deleted file mode 100644 index dcf19935..00000000 --- a/test/errors/type/Primop.fir +++ /dev/null @@ -1,13 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; CHECK: Must mux between equivalent types. -; CHECK: Primop add cannot operate on non-ground types. -; CHECK: A mux condition must be of type UInt. - -circuit Top : - module Top : - node x = mux(UInt(1),SInt(1),UInt(1)) - wire a : { q : UInt<1> } - node y = add(a,a) - node z = bits(SInt<10>(-1),1,2) - node zz = mux(SInt(1),UInt(1),UInt(1)) - diff --git a/test/errors/width/Conservative.fir b/test/errors/width/Conservative.fir deleted file mode 100644 index 43aa648f..00000000 --- a/test/errors/width/Conservative.fir +++ /dev/null @@ -1,6 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p ciwT 2>&1 | tee %s.out | FileCheck %s -; CHECK: Width too small for UIntValue. - -circuit Top : - module Top : - node bar = UInt<1>("h1111") diff --git a/test/errors/width/NegWidth.fir b/test/errors/width/NegWidth.fir deleted file mode 100644 index e02884a8..00000000 --- a/test/errors/width/NegWidth.fir +++ /dev/null @@ -1,9 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p ciwT 2>&1 | tee %s.out | FileCheck %s -; CHECK: Width cannot be negative or zero. - -circuit Top : - module Top : - output y : UInt - - wire x : UInt<2> - y <= shr(x,4) diff --git a/test/errors/width/SmallWidth.fir b/test/errors/width/SmallWidth.fir deleted file mode 100644 index 0885ba52..00000000 --- a/test/errors/width/SmallWidth.fir +++ /dev/null @@ -1,12 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p ciwT 2>&1 | tee %s.out | FileCheck %s -; CHECK: Width too small for UIntValue. - -circuit Top : - module Top : - output z : UInt - - z <= add(UInt<4>("h121"),UInt<3>("h13333")) - - - - diff --git a/test/errors/width/UninferredWidth.fir b/test/errors/width/UninferredWidth.fir deleted file mode 100644 index d4cff841..00000000 --- a/test/errors/width/UninferredWidth.fir +++ /dev/null @@ -1,12 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p ciwTd 2>&1 | tee %s.out | FileCheck %s -; CHECK: Uninferred width. - -circuit Top : - module Top : - input z : UInt - - - - - - diff --git a/test/features/BigInt.fir b/test/features/BigInt.fir deleted file mode 100644 index 9060d705..00000000 --- a/test/features/BigInt.fir +++ /dev/null @@ -1,10 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p cT 2>&1 | tee %s.out | FileCheck %s -circuit Top : - module Top : - node x = UInt("h2") - node y = UInt("h100000") - node z = UInt("h00") - -;CHECK: node x = UInt<2>("h2") -;CHECK: node z = UInt<1>("h0") -;CHECK: Done! diff --git a/test/features/BulkConnect.fir b/test/features/BulkConnect.fir deleted file mode 100644 index 1b68bbdc..00000000 --- a/test/features/BulkConnect.fir +++ /dev/null @@ -1,39 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: Expand Connects -circuit Top : - module Top : - wire a : { w : UInt} - a.w <= UInt(1) - wire b : { w : UInt<42>, x : UInt<20>} - b.w <= UInt(1) - b.x <= UInt(1) - a <- b - ; CHECK: a.w <= b.w - ; CHECK-NOT: a.x <= b.x - ; CHECK-NOT: a.y <= b.y - ; CHECK-NOT: b.y <= a.y - ; CHECK-NOT: a.z <= b.z - - - wire c : { x : { y : UInt<1>, z : UInt<1>}}[4] - c[0].x.z <= UInt(1) - c[1].x.z <= UInt(1) - c[2].x.y <= UInt(1) - c[2].x.z <= UInt(1) - c[3].x.y <= UInt(1) - c[3].x.z <= UInt(1) - wire d : { x : { y : UInt<1>}}[2] - d[0].x.y <= UInt(1) - d[1].x.y <= UInt(1) - c <- d - ; CHECK: c[0].x.y <= d[0].x.y - ; CHECK: c[1].x.y <= d[1].x.y - ; CHECK-NOT: c[2].x.y <= d[2].x.y - ; CHECK-NOT: c[3].x.y <= d[3].x.y - ; CHECK-NOT: c[0].x.z <= d[0].x.z - ; CHECK-NOT: c[1].x.z <= d[1].x.z - ; CHECK-NOT: c[2].x.z <= d[2].x.z - ; CHECK-NOT: c[3].x.z <= d[3].x.z - -;CHECK: Finished Expand Connects -;CHECK: Done! diff --git a/test/features/DeadCodeElimination.fir b/test/features/DeadCodeElimination.fir deleted file mode 100644 index e67deebf..00000000 --- a/test/features/DeadCodeElimination.fir +++ /dev/null @@ -1,10 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; XFAIL: * - -circuit top : - module top : - input clk : Clock - input reset : UInt<1> - wire x : UInt<1> - -; CHECK: Done! diff --git a/test/features/EmptyStmt.fir b/test/features/EmptyStmt.fir deleted file mode 100644 index 5fb265c0..00000000 --- a/test/features/EmptyStmt.fir +++ /dev/null @@ -1,11 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: Done! -circuit Top : - module Top : - skip - when UInt(1) : - skip - else : - skip - skip - diff --git a/test/features/ExModule.fir b/test/features/ExModule.fir deleted file mode 100644 index b31c77c9..00000000 --- a/test/features/ExModule.fir +++ /dev/null @@ -1,14 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -circuit Top : - module Top : - output z : UInt<4> - inst i of BlackBox - i.x <= UInt(1) - i.y <= UInt(2) - z <= i.z - extmodule BlackBox : - input x : UInt<4> - input y : UInt<4> - output z : UInt<4> - -;CHECK: Done! diff --git a/test/features/InitAccessor.fir b/test/features/InitAccessor.fir deleted file mode 100644 index 6261ec01..00000000 --- a/test/features/InitAccessor.fir +++ /dev/null @@ -1,13 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p cT 2>&1 | tee %s.out | FileCheck %s - -;CHECK: Done! -circuit Top : - module Top : - input in : UInt<1> - wire b : UInt<1>[3] - b[0] <= UInt(1) - b[1] <= UInt(1) - b[2] <= UInt(1) - node c = UInt(1) - when in : - b[c] <= UInt(1) diff --git a/test/features/InitializeVec.fir b/test/features/InitializeVec.fir deleted file mode 100644 index 1cc44daf..00000000 --- a/test/features/InitializeVec.fir +++ /dev/null @@ -1,21 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s - -;CHECK: Done! -circuit Tst : - module Tst : - input in : {valid : UInt<1>, flip ready : UInt<1>, bits : UInt<8>} - output outs : {valid : UInt<1>, flip ready : UInt<1>, bits : UInt<8>}[4] - - in.ready <= UInt<1>(1) - outs[0].valid <= UInt<1>(0) - outs[0].bits <= UInt<1>(0) - outs[1].valid <= UInt<1>(0) - outs[1].bits <= UInt<1>(0) - outs[2].valid <= UInt<1>(0) - outs[2].bits <= UInt<1>(0) - outs[3].valid <= UInt<1>(0) - outs[3].bits <= UInt<1>(0) - in.ready <= UInt<1>(1) - when outs[in.bits].ready : - outs[in.bits].bits <= UInt<7>(99) - outs[in.bits].valid <= UInt<1>(1) diff --git a/test/features/IsInvalid.fir b/test/features/IsInvalid.fir deleted file mode 100644 index dc7c56b4..00000000 --- a/test/features/IsInvalid.fir +++ /dev/null @@ -1,74 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -circuit Top : - module Top : - input clk : Clock - input reset : UInt<1> - input a : { w : UInt<42>, flip x : UInt<30>}[2] - output b : { w : UInt<42>, flip x : UInt<30>}[2] - mem m : - depth => 10 - data-type => UInt<32>[4] - read-latency => 0 - write-latency => 1 - reader => r - writer => w - readwriter => rw - wire x : { w : UInt<42>, x : UInt<20>} - reg c : { w : UInt<42>, x : UInt<20>},clk with : - reset => (reset,x) - inst other of Other - - clk is invalid - reset is invalid - a is invalid - b is invalid - m is invalid - x is invalid - c is invalid - other is invalid - module Other : - input a : { w : UInt<42>, flip x : UInt<30>} - output b : { w : UInt<42>, flip x : UInt<30>} - b <= a - - -;CHECK: Expand Connects -;CHECK: skip -;CHECK: skip -;CHECK: a[0].x is invalid -;CHECK: a[1].x is invalid -;CHECK: b[0].w is invalid -;CHECK: b[1].w is invalid -;CHECK: m.r.addr is invalid -;CHECK: m.r.en is invalid -;CHECK: m.r.clk is invalid -;CHECK: m.w.data[0] is invalid -;CHECK: m.w.data[1] is invalid -;CHECK: m.w.data[2] is invalid -;CHECK: m.w.data[3] is invalid -;CHECK: m.w.mask[0] is invalid -;CHECK: m.w.mask[1] is invalid -;CHECK: m.w.mask[2] is invalid -;CHECK: m.w.mask[3] is invalid -;CHECK: m.w.addr is invalid -;CHECK: m.w.en is invalid -;CHECK: m.w.clk is invalid -;CHECK: m.rw.wmode is invalid -;CHECK: m.rw.data[0] is invalid -;CHECK: m.rw.data[1] is invalid -;CHECK: m.rw.data[2] is invalid -;CHECK: m.rw.data[3] is invalid -;CHECK: m.rw.mask[0] is invalid -;CHECK: m.rw.mask[1] is invalid -;CHECK: m.rw.mask[2] is invalid -;CHECK: m.rw.mask[3] is invalid -;CHECK: m.rw.addr is invalid -;CHECK: m.rw.en is invalid -;CHECK: m.rw.clk is invalid -;CHECK: x.w is invalid -;CHECK: x.x is invalid -;CHECK: c.w is invalid -;CHECK: c.x is invalid -;CHECK: other.a.w is invalid -;CHECK: other.b.x is invalid -;CHECK: Done! diff --git a/test/features/Link.fir b/test/features/Link.fir deleted file mode 100644 index 57fb8605..00000000 --- a/test/features/Link.fir +++ /dev/null @@ -1,14 +0,0 @@ -; RUN: firrtl -i %s -m %S/Queue.fir -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: Done! -circuit Top : - module Top : - input clk : Clock - input reset : UInt<1> - output out : UInt<10> - - inst q of Queue - q.clk <= clk - q.reset <= reset - q.in <= UInt(1) - out <= q.out - diff --git a/test/features/Long.fir b/test/features/Long.fir deleted file mode 100644 index 7ac5ad6c..00000000 --- a/test/features/Long.fir +++ /dev/null @@ -1,6 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: Done -circuit Top : - module Top : - wire a : UInt - a <= UInt("h4261441663") diff --git a/test/features/MemSize1.fir b/test/features/MemSize1.fir deleted file mode 100644 index a29d3fc5..00000000 --- a/test/features/MemSize1.fir +++ /dev/null @@ -1,11 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: Done! -circuit Top : - module Top : - input clk : Clock - output out : UInt<32> - input i : UInt<1> - cmem m : UInt<32>[1] - read mport r = m[i],clk - out <= r - diff --git a/test/features/MuxBundle.fir b/test/features/MuxBundle.fir deleted file mode 100644 index 764078d5..00000000 --- a/test/features/MuxBundle.fir +++ /dev/null @@ -1,16 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: Expand Connects -circuit Top : - module Top : - input a: {w:UInt<42>,x:UInt<20>} - input b: {w:UInt<42>,x:UInt<20>} - input c: {w:UInt<42>,x:UInt<20>} - input p : UInt<1> - output d: {w:UInt<42>,x:UInt<20>} - d <= mux(p,mux(p,a,b),c) -;CHECK: d.w <= mux(p, mux(p, a.w, b.w), c.w) -;CHECK: d.x <= mux(p, mux(p, a.x, b.x), c.x) - -;CHECK: Finished Expand Connects -;CHECK: Done! - diff --git a/test/features/MuxNodeExamples.fir b/test/features/MuxNodeExamples.fir deleted file mode 100644 index 07fa16b4..00000000 --- a/test/features/MuxNodeExamples.fir +++ /dev/null @@ -1,28 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: Expand Connects -circuit Top : - module Top : - input a : {f:UInt<3>[3], flip g:UInt<3>[3]}[2] - input b : {f:UInt<3>[3], flip g:UInt<3>[3]}[2] - input p : UInt<1> - input i : UInt<1> - b[0].g[0] <= UInt(0) - b[0].g[1] <= UInt(0) - b[0].g[2] <= UInt(0) - b[1].g[0] <= UInt(0) - b[1].g[1] <= UInt(0) - b[1].g[2] <= UInt(0) - a[0].g[0] <= UInt(0) - a[0].g[1] <= UInt(0) - a[0].g[2] <= UInt(0) - a[1].g[0] <= UInt(0) - a[1].g[1] <= UInt(0) - a[1].g[2] <= UInt(0) - node x = mux(p,a[i].f,b[i].f) - - - -;CHECK: Finished Expand Connects -;CHECK: Done! - - diff --git a/test/features/MuxType.fir b/test/features/MuxType.fir deleted file mode 100644 index b0e7e7ef..00000000 --- a/test/features/MuxType.fir +++ /dev/null @@ -1,12 +0,0 @@ - -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: Expand Connects -circuit Top : - module Top : - input a: UInt<1> - input b: UInt<32> - input p : UInt<1> - output d: UInt - node y = mux(p, a, b) - d <= y -;CHECK:Done! diff --git a/test/features/NestedAccess.fir b/test/features/NestedAccess.fir deleted file mode 100644 index bd3c436d..00000000 --- a/test/features/NestedAccess.fir +++ /dev/null @@ -1,31 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p cw 2>&1 | tee %s.out | FileCheck %s -;CHECK: Expand Connects -circuit Top : - module Top : - input i : UInt<1> - input j : UInt<1> - wire a : { x : UInt<42> flip y : UInt<42>[2]}[2][3] - wire b : { x : UInt<42> flip y : UInt<42>[2]} - a[0][0].x <= UInt(0) - a[0][0].y[0] <= UInt(0) - a[0][0].y[1] <= UInt(0) - a[0][1].x <= UInt(0) - a[0][1].y[0] <= UInt(0) - a[0][1].y[1] <= UInt(0) - a[1][0].x <= UInt(0) - a[1][0].y[0] <= UInt(0) - a[1][0].y[1] <= UInt(0) - a[1][1].x <= UInt(0) - a[1][1].y[0] <= UInt(0) - a[1][1].y[1] <= UInt(0) - a[2][0].x <= UInt(0) - a[2][0].y[0] <= UInt(0) - a[2][0].y[1] <= UInt(0) - a[2][1].x <= UInt(0) - a[2][1].y[0] <= UInt(0) - a[2][1].y[1] <= UInt(0) - b.x <= UInt(0) - a[i][j] <= b -;CHECK: Finished Expand Connects -;CHECK: Done! - diff --git a/test/features/NestedSubAccessTester.fir b/test/features/NestedSubAccessTester.fir deleted file mode 100644 index 36465012..00000000 --- a/test/features/NestedSubAccessTester.fir +++ /dev/null @@ -1,27 +0,0 @@ -circuit NestedSubAccessTester : - module NestedSubAccess : - input foo : UInt<1>[4] - input index : UInt<2> - output out : UInt<4> - - wire vec : UInt<4>[2] - vec[0] <= UInt(3) - vec[1] <= UInt(4) - - out <= vec[foo[index]] - - module NestedSubAccessTester : - input clk : Clock - input reset : UInt<1> - - inst dut of NestedSubAccess - - dut.foo is invalid - dut.index <= UInt(2) - dut.foo[2] <= UInt(1) - - when neq(dut.out, UInt(4)) : - printf(clk, not(reset), "Assertion failed\nTest Failed!\n") - stop(clk, not(reset), 1) - else : - stop(clk, not(reset), 0) diff --git a/test/features/NodeBundle.fir b/test/features/NodeBundle.fir deleted file mode 100644 index c4c33107..00000000 --- a/test/features/NodeBundle.fir +++ /dev/null @@ -1,12 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: Lower Types -circuit Top : - module Top : - input a: {w:UInt<42>,x:UInt<20>} - node d = a -;CHECK: node d_w = a_w -;CHECK: node d_x = a_x - -;CHECK: Finished Lower Types -;CHECK: Done! - diff --git a/test/features/OptionalRegisterReset.fir b/test/features/OptionalRegisterReset.fir deleted file mode 100644 index 54a90b67..00000000 --- a/test/features/OptionalRegisterReset.fir +++ /dev/null @@ -1,17 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -circuit Top : - module Top : - input clk : Clock - input reset : UInt<1> - input a : UInt<32> - input p : UInt<1> - output b : UInt<32> - reg r1:UInt<32> clk with : - reset => (reset, a) - when p : - b <= r1 - else : - b <= r1 - - -;CHECK: Done! diff --git a/test/features/Poison.fir b/test/features/Poison.fir deleted file mode 100644 index 9aafe63f..00000000 --- a/test/features/Poison.fir +++ /dev/null @@ -1,39 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; CHECK: Done! -circuit Poison : - module Poison : - input clk : Clock - input reset : UInt<1> - input index : UInt<7> - input wmask : {x:UInt<1>, y:UInt<1>} - input p : UInt<1> - output out : {x : UInt<10>, y : UInt<10>} - poison q : {x : UInt<10>, y : UInt<10>} - mem m : - data-type => {x : UInt<10>, y : UInt<10>} - depth => 128 - read-latency => 1 - write-latency => 2 - reader => r - writer => w - readwriter => rw - m.r.addr <= index - m.r.en <= UInt(1) - m.r.clk <= clk - m.w.addr <= index - m.w.en <= UInt(1) - m.w.mask <= wmask - m.w.clk <= clk - m.w.data <= q - - m.rw.clk <= clk - m.rw.addr <= index - m.rw.en <= UInt(1) - m.rw.wmode <= UInt(1) - m.rw.mask <= wmask - m.rw.data <= q - when p : - out <= m.r.data - else : - out <= q - diff --git a/test/features/Printf.fir b/test/features/Printf.fir deleted file mode 100644 index 912023af..00000000 --- a/test/features/Printf.fir +++ /dev/null @@ -1,21 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s - -;CHECK: Expand Whens -circuit Top : - module Top : - input x : {y : UInt<1>} - input p : UInt<1> - input clk : Clock - input en : UInt<1> - printf(clk,en,"Hello World!\n") - printf(clk,en,"Hello World! %x\n", x.y) - when p : - printf(clk,en,"In consequence\n") - else : - printf(clk,en,"In alternate\n") - -;CHECK: printf(clk, en, "Hello World!\n") -;CHECK: printf(clk, en, "Hello World! %x\n", x.y) -;CHECK: printf(clk, and(p, en), "In consequence\n") -;CHECK: printf(clk, and(eq(p, UInt<1>("h0")), en), "In alternate\n") -;CHECK: Done! diff --git a/test/features/Queue.fir b/test/features/Queue.fir deleted file mode 100644 index 3ce58e31..00000000 --- a/test/features/Queue.fir +++ /dev/null @@ -1,13 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; CHECK: Done! -circuit Queue : - module Queue : - input in : UInt<10> - output out : UInt<10> - input clk : Clock - input reset : UInt<1> - - reg r : UInt<10>,clk with : - reset => (reset,in) - r <= in - out <= r diff --git a/test/features/SeqMem.fir b/test/features/SeqMem.fir deleted file mode 100644 index d97435af..00000000 --- a/test/features/SeqMem.fir +++ /dev/null @@ -1,46 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: Done! -circuit Top : - module Top : - input clk : Clock - wire i : UInt<5> - i <= UInt(1) - wire i0 : UInt<5> - wire j : UInt<128> - - i0 <= UInt(10) - - mem m-com : - data-type => UInt<128> - depth => 32 - reader => r - writer => w - read-latency => 0 - write-latency => 1 - m-com.r.addr <= i - m-com.r.en <= UInt(1) - m-com.r.clk <= clk - m-com.w.addr <= i - m-com.w.mask <= UInt(1) - m-com.w.en <= UInt(1) - m-com.w.clk <= clk - j <= m-com.r.data - m-com.w.data <= j - - - mem m-seq : - data-type => UInt<128> - depth => 32 - reader => r - writer => w - read-latency => 1 - write-latency => 1 - m-seq.r.addr <= i - m-seq.r.en <= UInt(1) - m-seq.r.clk <= clk - m-seq.w.addr <= i - m-seq.w.mask <= UInt(1) - m-seq.w.en <= UInt(1) - m-seq.w.clk <= clk - j <= m-seq.r.data - m-seq.w.data <= j diff --git a/test/features/Stop.fir b/test/features/Stop.fir deleted file mode 100644 index 888da3d7..00000000 --- a/test/features/Stop.fir +++ /dev/null @@ -1,20 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s - -;CHECK: Expand Whens - -circuit Top : - module Top : - input p : UInt<1> - input q : UInt<1> - input clk : Clock - when p : - stop(clk,UInt(1),0) - when q : - stop(clk,UInt(1),1) - stop(clk,UInt(1),3) - -;CHECK: stop(clk, p, 0) -;CHECK: stop(clk, q, 1) -;CHECK: stop(clk, UInt<1>("h1"), 3) -;CHECK: Done! - diff --git a/test/features/TwoClocks.fir b/test/features/TwoClocks.fir deleted file mode 100644 index 3753ee8d..00000000 --- a/test/features/TwoClocks.fir +++ /dev/null @@ -1,24 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -circuit Top : - module Top : - input clk1 : Clock - input clk2 : Clock - input reset1 : UInt<1> - input reset2 : UInt<1> - reg src : UInt<10>, clk1 with : - reset => ( reset1, UInt(0)) - reg sink : UInt<10>, clk2 with : - reset => ( reset2, UInt(0)) - - src <= add(src,UInt(1)) - - reg sync_A : UInt<10>, clk2 with : - reset => ( reset2, UInt(0)) - sync_A <= src - reg sync_B : UInt<10>, clk2 with : - reset => ( reset2, UInt(0)) - sync_B <= sync_A - - sink <= sync_B - -;CHECK: Done! diff --git a/test/features/ValidIf.fir b/test/features/ValidIf.fir deleted file mode 100644 index 70c69313..00000000 --- a/test/features/ValidIf.fir +++ /dev/null @@ -1,21 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -circuit Top : - module Top : - input clk : Clock - input reset : UInt<1> - input a : { w : UInt<42>, x : UInt<30>}[2] - input b : { w : UInt<42>, x : UInt<30>}[2] - input p: UInt<1> - input q: UInt<1> - output c : { w : UInt<42>, x : UInt<30>}[2] - output d : { w : UInt<42>, x : UInt<30>}[2] - - c is invalid - when p : - when q : - c <= a - else : - c <= b - d <= validif(p,b) - -;CHECK: Done! diff --git a/test/features/VerilogReg.fir b/test/features/VerilogReg.fir deleted file mode 100644 index 96022933..00000000 --- a/test/features/VerilogReg.fir +++ /dev/null @@ -1,18 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; CHECK: Done! -circuit Poison : - module Poison : - input clk : Clock - input reset : UInt<1> - input p1 : UInt<1> - input p2 : UInt<1> - input p3 : UInt<1> - reg r : UInt<32>,clk with : - reset => (reset,r) - when p1 : - r <= UInt(1) - when p2 : - r <= UInt(2) - when p3 : - r <= UInt(3) - diff --git a/test/features/VerilogRename.fir b/test/features/VerilogRename.fir deleted file mode 100644 index f8fceaa9..00000000 --- a/test/features/VerilogRename.fir +++ /dev/null @@ -1,18 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -circuit Top : - module Top : - input with : Clock - output unsigned : Clock - wire trireg : Clock - unsigned <= with - trireg <= with - -;CHECK: Verilog Rename - -;CHECK: input with$ : Clock -;CHECK: output unsigned$ : Clock -;CHECK: wire trireg$ : Clock -;CHECK: trireg$ <= with$ -;CHECK: unsigned$ <= with$ - -;CHECK: Done! diff --git a/test/lit.cfg b/test/lit.cfg deleted file mode 100644 index 71928a43..00000000 --- a/test/lit.cfg +++ /dev/null @@ -1,4 +0,0 @@ -import lit.formats - -config.test_format = lit.formats.ShTest() -config.suffixes = ['.fir'] diff --git a/test/parser/bundle.fir b/test/parser/bundle.fir deleted file mode 100644 index 16a72a1b..00000000 --- a/test/parser/bundle.fir +++ /dev/null @@ -1,44 +0,0 @@ -; RUN: firrtl -i %s -o %s.out -X firrtl && cat %s.out | FileCheck %s - -circuit top : - module top : - wire z : { x : UInt, flip y: SInt} - z.x <= UInt(1) - z.y <= SInt(1) - node x = z.x - node y = z.y - wire a : UInt<3>[10] - a[0] <= UInt(1) - a[1] <= UInt(1) - a[2] <= UInt(1) - a[3] <= UInt(1) - a[4] <= UInt(1) - a[5] <= UInt(1) - a[6] <= UInt(1) - a[7] <= UInt(1) - a[8] <= UInt(1) - a[9] <= UInt(1) - node b = a[2] - node c = a[UInt(3)] - -; CHECK: circuit top : -; CHECK: module top : -; CHECK: wire z : { x : UInt, flip y : SInt} -; CHECK: z.x <= UInt<1>("h1") -; CHECK: z.y <= SInt<2>("h1") -; CHECK: node x = z.x -; CHECK: node y = z.y -; CHECK: wire a : UInt<3>[10] -; CHECK: a[0] <= UInt<1>("h1") -; CHECK: a[1] <= UInt<1>("h1") -; CHECK: a[2] <= UInt<1>("h1") -; CHECK: a[3] <= UInt<1>("h1") -; CHECK: a[4] <= UInt<1>("h1") -; CHECK: a[5] <= UInt<1>("h1") -; CHECK: a[6] <= UInt<1>("h1") -; CHECK: a[7] <= UInt<1>("h1") -; CHECK: a[8] <= UInt<1>("h1") -; CHECK: a[9] <= UInt<1>("h1") -; CHECK: node b = a[2] -; CHECK: node c = a[UInt<2>("h3")] - diff --git a/test/parser/dshl.fir b/test/parser/dshl.fir deleted file mode 100644 index 99a6ec7d..00000000 --- a/test/parser/dshl.fir +++ /dev/null @@ -1,14 +0,0 @@ -; RUN: firrtl -i %s -o %s.out -X firrtl && cat %s.out | FileCheck %s -circuit GCD : - module GCD : - input a : UInt<63> - input b : UInt<63> - input sign : UInt<1> - output d : UInt - ;wire T_205 : UInt - node T_203 = UInt<6>("h3f") - node normCount = not(T_203) - node absIn = mux(sign, a, b) - node T_205 = dshl(absIn, normCount) - d <= T_205 - diff --git a/test/parser/gcd.fir b/test/parser/gcd.fir deleted file mode 100644 index 45a048f2..00000000 --- a/test/parser/gcd.fir +++ /dev/null @@ -1,54 +0,0 @@ -; RUN: firrtl -i %s -o %s.out -X firrtl && cat %s.out | FileCheck %s -circuit GCD : - module GCD : - input e : UInt<1> - input clk : Clock - input reset : UInt<1> - output z : UInt - output v : UInt<1> - input a : UInt<16> - input b : UInt<16> - - reg x : UInt<16>,clk - reg y : UInt<16>,clk - node T_17 = gt(x, y) - when T_17 : - node T_18 = tail(sub(x, y), 1) - x <= T_18 - else : - node T_19 = tail(sub(y, x), 1) - y <= T_19 - when e : - x <= a - y <= b - z <= x - node T_20 = eq(y, UInt<1>(0)) - v <= T_20 - -; CHECK: circuit GCD : -; CHECK: module GCD : -; CHECK: input e : UInt<1> -; CHECK: input clk : Clock -; CHECK: input reset : UInt<1> -; CHECK: output z : UInt<16> -; CHECK: output v : UInt<1> -; CHECK: input a : UInt<16> -; CHECK: input b : UInt<16> -; CHECK: reg x : UInt<16>, clk with : -; CHECK: reset => (UInt<1>("h0"), x) -; CHECK: reg y : UInt<16>, clk with : -; CHECK: reset => (UInt<1>("h0"), y) -; CHECK: node T_17 = gt(x, y) -; CHECK: when T_17 : -; CHECK: node T_18 = tail(sub(x, y), 1) -; CHECK: x <= T_18 -; CHECK: else : -; CHECK: node T_19 = tail(sub(y, x), 1) -; CHECK: y <= T_19 -; CHECK: when e : -; CHECK: x <= a -; CHECK: y <= b -; CHECK: z <= x -; CHECK: node T_20 = eq(y, UInt<1>("h0")) -; CHECK: v <= T_20 - diff --git a/test/parser/ints.fir b/test/parser/ints.fir deleted file mode 100644 index 0c79276b..00000000 --- a/test/parser/ints.fir +++ /dev/null @@ -1,20 +0,0 @@ -; RUN: firrtl -i %s -o %s.out -X firrtl 2>&1 | tee %s.out | FileCheck %s -: XFAIL: * - -circuit top : - module top : - output a : UInt - output b : SInt - output c : SInt - a <= UInt(8) - b <= SInt(8) - c <= SInt(-8) - -; CHECK: circuit top : -; CHECK: module top : -; CHECK: output a : UInt -; CHECK: output b : SInt -; CHECK: output c : SInt -; CHECK: a <= UInt<4>("h8") -; CHECK: b <= SInt<5>("h08") -; CHECK: c <= SInt<4>("h8") diff --git a/test/parser/invalids.fir b/test/parser/invalids.fir deleted file mode 100644 index 65051832..00000000 --- a/test/parser/invalids.fir +++ /dev/null @@ -1,13 +0,0 @@ -; RUN: firrtl -i %s -o %s.out -X firrtl && cat %s.out | FileCheck %s -; CHECK: Done! -circuit GCD : - module GCD : - input x : UInt<128> - input p : UInt<1> - input q : UInt<1> - input clk : Clock - wire w : UInt[3] - w is invalid - w[0] <= UInt(0) - w[1] <= UInt(0) - w[2] <= UInt(0) diff --git a/test/parser/mux.fir b/test/parser/mux.fir deleted file mode 100644 index 4705aa75..00000000 --- a/test/parser/mux.fir +++ /dev/null @@ -1,14 +0,0 @@ -; RUN: firrtl -i %s -o %s.out -X firrtl && cat %s.out | FileCheck %s -circuit GCD : - module GCD : - input e : UInt<1> - input f : UInt<1> - input g : UInt<1> - output o : UInt<1> - node y = f - node z = f - node x = mux(UInt<1>(0),y,z) - o <= x - - - diff --git a/test/parser/node.fir b/test/parser/node.fir deleted file mode 100644 index 193aed88..00000000 --- a/test/parser/node.fir +++ /dev/null @@ -1,16 +0,0 @@ -; RUN: firrtl -i %s -o %s.out -X firrtl && cat %s.out | FileCheck %s -; CHECK: Done! -circuit GCD : - module GCD : - input x : UInt<128> - input p : UInt<1> - input q : UInt<1> - input clk : Clock - reg addr : UInt, clk with : - reset => (UInt<1>("h0"), addr) - when p : - node T_1234 = bits(x, 63, 24) - addr <= T_1234 - when q : - node T_1380 = tail(x, 1) - addr <= T_1380 diff --git a/test/passes/const-prop/bits.fir b/test/passes/const-prop/bits.fir deleted file mode 100644 index 74aa19de..00000000 --- a/test/passes/const-prop/bits.fir +++ /dev/null @@ -1,11 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p cT 2>&1 | tee %s.out | FileCheck %s - -;CHECK: Constant Propagation -;CHECK: node x = UInt<3>("h7") -;CHECK: Finished Constant Propagation - -circuit top : - module top : - output out : UInt - node x = bits(UInt(127),2,0) - out <= x diff --git a/test/passes/const-prop/rsh.fir b/test/passes/const-prop/rsh.fir deleted file mode 100644 index 5ed8b1be..00000000 --- a/test/passes/const-prop/rsh.fir +++ /dev/null @@ -1,14 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s - -;CHECK: Constant Propagation -;CHECK: x <= UInt<5>("h1f") -;CHECK: y <= SInt<6>("h20") -;CHECK: Finished Constant Propagation - -circuit top : - module top : - output x : UInt - output y : SInt - x <= shr(UInt(127),2) - y <= shr(SInt(-128),2) - diff --git a/test/passes/expand-accessors/accessor-mem.fir b/test/passes/expand-accessors/accessor-mem.fir deleted file mode 100644 index ce1d8da3..00000000 --- a/test/passes/expand-accessors/accessor-mem.fir +++ /dev/null @@ -1,36 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s - -circuit top : - module top : - input clk : Clock - wire i : UInt<4> - wire j : UInt<32> - wire z : UInt<32> - i <= UInt(1) - mem m : - data-type => UInt<32>[2] - depth => 2 - reader => a - writer => x - read-latency => 0 - write-latency => 1 - m.a.addr <= i - m.a.clk <= clk - m.a.en <= UInt(1) - m.x.addr <= i - m.x.clk <= clk - m.x.en <= UInt(1) - m.x.mask[0] <= UInt(1) - m.x.mask[1] <= UInt(1) - wire b : UInt<32>[2] - b <= m.a.data - node c = b[i] - z <= j - j <= c - wire y : UInt<32>[2] - y[0] <= UInt(1) - y[1] <= UInt(1) - m.x.data <= y - y[i] <= z - -; CHECK: Done! diff --git a/test/passes/expand-accessors/accessor-vec.fir b/test/passes/expand-accessors/accessor-vec.fir deleted file mode 100644 index 8b4b7eb8..00000000 --- a/test/passes/expand-accessors/accessor-vec.fir +++ /dev/null @@ -1,53 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s - -circuit top : - module top : - wire m : UInt<32>[2][2][2] - wire a : UInt<32>[2][2] - wire b : UInt<32>[2] - wire c : UInt<32> - wire i : UInt - wire j : UInt - m[0][0][0] <= UInt(1) - m[1][0][0] <= UInt(1) - m[0][1][0] <= UInt(1) - m[1][1][0] <= UInt(1) - m[0][0][1] <= UInt(1) - m[1][0][1] <= UInt(1) - m[0][1][1] <= UInt(1) - m[1][1][1] <= UInt(1) - i <= UInt(1) - a <= m[i] - b <= a[i] - c <= b[i] - j <= c - - wire x : UInt<32>[2][2] - wire y : UInt<32>[2] - wire z : UInt<32> - x[0][0] <= UInt(1) - x[1][0] <= UInt(1) - x[0][1] <= UInt(1) - x[1][1] <= UInt(1) - y[0] <= UInt(1) - y[1] <= UInt(1) - m[i] <= x - x[i] <= y - y[i] <= z - z <= j - - wire p : {n : UInt<32>[2]} - p.n[0] <= UInt(1) - p.n[1] <= UInt(1) - wire q : UInt<32> - p.n[i] <= q - q <= j - - wire r : {m : UInt<32>}[2] - r[0].m <= UInt(1) - r[1].m <= UInt(1) - wire s : { m : UInt<32>} - s <= r[i] - j <= s.m - -; CHECK: Done! diff --git a/test/passes/expand-accessors/simple.fir b/test/passes/expand-accessors/simple.fir deleted file mode 100644 index b595fc4c..00000000 --- a/test/passes/expand-accessors/simple.fir +++ /dev/null @@ -1,16 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s - -;CHECK: Done! -circuit top : - module top : - output o : UInt - wire m : UInt<32>[2] - wire i : UInt - m[0] <= UInt("h1") - m[1] <= UInt("h1") - i <= UInt("h1") - wire a : UInt<32> - a <= m[i] - o <= a - - diff --git a/test/passes/expand-accessors/simple2.fir b/test/passes/expand-accessors/simple2.fir deleted file mode 100644 index a7d8258d..00000000 --- a/test/passes/expand-accessors/simple2.fir +++ /dev/null @@ -1,18 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s - -;CHECK: Done! -circuit top : - module top : - output o1 : UInt - output o2 : UInt - wire m : UInt<32>[2] - wire i : UInt - m[0] <= UInt("h1") - m[1] <= UInt("h1") - i <= UInt("h1") - wire a : UInt<32> - a <= m[i] - o1 <= a - o2 <= a - - diff --git a/test/passes/expand-whens/bundle-init.fir b/test/passes/expand-whens/bundle-init.fir deleted file mode 100644 index 333619d9..00000000 --- a/test/passes/expand-whens/bundle-init.fir +++ /dev/null @@ -1,27 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p cd 2>&1 | tee %s.out | FileCheck %s -; CHECK: Expand Whens -circuit top : - module top : - input clk : Clock - input reset : UInt<1> - wire w : { x : UInt, y : UInt} - reg r : { x : UInt, y : UInt},clk with : - reset => (reset,w) - wire a : UInt - wire b : UInt - a <= UInt(1) - b <= UInt(2) - - w.x <= b - w.y <= a - r.x <= a - r.y <= b - -; CHECK: w.x <= b -; CHECK: w.y <= a -; CHECK: r.x <= a -; CHECK: r.y <= b -; CHECK: a <= UInt<1>("h1") -; CHECK: b <= UInt<2>("h2") - -; CHECK: Finished Expand Whens diff --git a/test/passes/expand-whens/nested-whens.fir b/test/passes/expand-whens/nested-whens.fir deleted file mode 100644 index 68409931..00000000 --- a/test/passes/expand-whens/nested-whens.fir +++ /dev/null @@ -1,33 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; CHECK: Expand Whens -circuit top : - module top : - input clk : Clock - input reset : UInt<1> - wire p : UInt - wire q : UInt - wire a : UInt - wire b : UInt - wire x : UInt - wire y : UInt - wire z : UInt - wire w : UInt - reg r : UInt, clk with : - reset => (reset, w) - p <= UInt(1) - q <= UInt(1) - a <= UInt(1) - b <= UInt(1) - x <= UInt(1) - y <= UInt(1) - z <= UInt(1) - w <= UInt(1) - - when p : - r <= a - when q : - r <= b - r <= z -; CHECK: r <= z -; CHECK: Finished Expand Whens -; CHECK: Done! diff --git a/test/passes/expand-whens/partial-init.fir b/test/passes/expand-whens/partial-init.fir deleted file mode 100644 index 2fb54717..00000000 --- a/test/passes/expand-whens/partial-init.fir +++ /dev/null @@ -1,34 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s - -; CHECK: Expand Whens -circuit top : - module top : - input clk : Clock - input reset : UInt<1> - poison x : UInt<1> - wire init : UInt<1>[10] - init[0] <= x - init[1] <= x - init[2] <= x - init[3] <= UInt(3) - init[4] <= x - init[5] <= x - init[6] <= x - init[7] <= x - init[8] <= x - init[9] <= x - reg r : UInt<1>[10],clk with : - reset => (reset,init) - r[0] <= UInt(1) - r[1] <= UInt(1) - r[2] <= UInt(1) - r[3] <= UInt(1) - r[4] <= UInt(1) - r[5] <= UInt(1) - r[6] <= UInt(1) - r[7] <= UInt(1) - r[8] <= UInt(1) - r[9] <= UInt(1) - -; CHECK: Finished Expand Whens -; CHECK: Done! diff --git a/test/passes/expand-whens/reg-and-when.fir b/test/passes/expand-whens/reg-and-when.fir deleted file mode 100644 index 97b96735..00000000 --- a/test/passes/expand-whens/reg-and-when.fir +++ /dev/null @@ -1,160 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p cd 2>&1 | tee %s.out ; cat %s.v | FileCheck %s -; CHECK: out__slow__bits <= fromhost__q$deq$valid ? fromhost__q$deq$bits : tohost__q$deq$bits; -circuit Top : - module Top : - input clock : Clock - input reset : UInt<1> - input out_fast : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>} - output out_slow : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>} - output in_fast : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>} - input in_slow : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>} - output clk_slow : UInt<1> - input set_divisor : {valid : UInt<1>, bits : UInt<32>} - output divisor : UInt<32> - - out_fast.ready <= UInt<1>("h00") - out_slow.bits <= UInt<1>("h00") - out_slow.valid <= UInt<1>("h00") - in_fast.bits <= UInt<1>("h00") - in_fast.valid <= UInt<1>("h00") - in_slow.ready <= UInt<1>("h00") - clk_slow <= UInt<1>("h00") - divisor <= UInt<1>("h00") - - inst fromhost_q of Queue_50 - fromhost_q.reset <= UInt<1>("h00") - fromhost_q.enq.bits <= UInt<1>("h00") - fromhost_q.enq.valid <= UInt<1>("h00") - fromhost_q.deq.ready <= UInt<1>("h00") - fromhost_q.clock <= clock - fromhost_q.reset <= reset - - inst tohost_q of Queue_51 - tohost_q.reset <= UInt<1>("h00") - tohost_q.enq.bits <= UInt<1>("h00") - tohost_q.enq.valid <= UInt<1>("h00") - tohost_q.deq.ready <= UInt<1>("h00") - tohost_q.clock <= clock - tohost_q.reset <= reset - - reg out_slow_bits : UInt<17>, clock, reset - out_slow_bits <= tohost_q.deq.bits - when fromhost_q.deq.valid : - out_slow_bits <= fromhost_q.deq.bits - - module Queue_50 : - input clock : Clock - input reset : UInt<1> - input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>} - output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>} - output count : UInt<1> - - enq.ready <= UInt<1>("h00") - deq.bits <= UInt<1>("h00") - deq.valid <= UInt<1>("h00") - count <= UInt<1>("h00") - - cmem ram : UInt<17>[1], clock - reg maybe_full : UInt<1>, clock, reset - onreset maybe_full <= UInt<1>("h00") - node ptr_match = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_115167 = eq(maybe_full, UInt<1>("h00")) - node empty = and(ptr_match, T_115167) - node full = and(ptr_match, maybe_full) - node maybe_flow = and(UInt<1>("h00"), empty) - node do_flow = and(maybe_flow, deq.ready) - node T_115173 = and(enq.ready, enq.valid) - node T_115175 = eq(do_flow, UInt<1>("h00")) - node do_enq = and(T_115173, T_115175) - node T_115177 = and(deq.ready, deq.valid) - node T_115179 = eq(do_flow, UInt<1>("h00")) - node do_deq = and(T_115177, T_115179) - when do_enq : - infer accessor T_115181 = ram[UInt<1>("h00")] - T_115181 <= enq.bits - skip - when do_deq : - skip - node T_115184 = neq(do_enq, do_deq) - when T_115184 : - maybe_full <= do_enq - skip - node T_115186 = eq(empty, UInt<1>("h00")) - node T_115188 = and(UInt<1>("h00"), enq.valid) - node T_115189 = or(T_115186, T_115188) - deq.valid <= T_115189 - node T_115191 = eq(full, UInt<1>("h00")) - node T_115193 = and(UInt<1>("h00"), deq.ready) - node T_115194 = or(T_115191, T_115193) - enq.ready <= T_115194 - infer accessor T_115195 = ram[UInt<1>("h00")] - wire T_115197 : UInt<17> - T_115197 <= T_115195 - when maybe_flow : - T_115197 <= enq.bits - skip - deq.bits <= T_115197 - node ptr_diff = subw(UInt<1>("h00"), UInt<1>("h00")) - node T_115199 = and(maybe_full, ptr_match) - node T_115200 = T_115199 - node T_115201 = cat(T_115200, ptr_diff) - count <= T_115201 - - module Queue_51 : - input clock : Clock - input reset : UInt<1> - input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>} - output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>} - output count : UInt<1> - - enq.ready <= UInt<1>("h00") - deq.bits <= UInt<1>("h00") - deq.valid <= UInt<1>("h00") - count <= UInt<1>("h00") - - cmem ram : UInt<17>[1], clock - reg maybe_full : UInt<1>, clock, reset - onreset maybe_full <= UInt<1>("h00") - node ptr_match = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_115235 = eq(maybe_full, UInt<1>("h00")) - node empty = and(ptr_match, T_115235) - node full = and(ptr_match, maybe_full) - node maybe_flow = and(UInt<1>("h00"), empty) - node do_flow = and(maybe_flow, deq.ready) - node T_115241 = and(enq.ready, enq.valid) - node T_115243 = eq(do_flow, UInt<1>("h00")) - node do_enq = and(T_115241, T_115243) - node T_115245 = and(deq.ready, deq.valid) - node T_115247 = eq(do_flow, UInt<1>("h00")) - node do_deq = and(T_115245, T_115247) - when do_enq : - infer accessor T_115249 = ram[UInt<1>("h00")] - T_115249 <= enq.bits - skip - when do_deq : - skip - node T_115252 = neq(do_enq, do_deq) - when T_115252 : - maybe_full <= do_enq - skip - node T_115254 = eq(empty, UInt<1>("h00")) - node T_115256 = and(UInt<1>("h00"), enq.valid) - node T_115257 = or(T_115254, T_115256) - deq.valid <= T_115257 - node T_115259 = eq(full, UInt<1>("h00")) - node T_115261 = and(UInt<1>("h00"), deq.ready) - node T_115262 = or(T_115259, T_115261) - enq.ready <= T_115262 - infer accessor T_115263 = ram[UInt<1>("h00")] - wire T_115265 : UInt<17> - T_115265 <= T_115263 - when maybe_flow : - T_115265 <= enq.bits - skip - deq.bits <= T_115265 - node ptr_diff = subw(UInt<1>("h00"), UInt<1>("h00")) - node T_115267 = and(maybe_full, ptr_match) - node T_115268 = T_115267 - node T_115269 = cat(T_115268, ptr_diff) - count <= T_115269 - diff --git a/test/passes/expand-whens/reg-dwc.fir b/test/passes/expand-whens/reg-dwc.fir deleted file mode 100644 index 6713b1f2..00000000 --- a/test/passes/expand-whens/reg-dwc.fir +++ /dev/null @@ -1,25 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -circuit top : - module top : - input clk : Clock - input reset : UInt<1> - wire p : UInt - p <= UInt(1) - reg r : UInt,clk with : - reset => (reset,r) - when p : - r <= UInt(2) - -; CHECK: Expand Whens - -; CHECK: circuit top : -; CHECK: module top : -; CHECK: wire p : UInt -; CHECK: reg r : UInt -; CHECK: p <= UInt<1>("h1") -; CHECK: r <= mux(p, UInt<2>("h2"), r) - -; CHECK: Finished Expand Whens - -; CHECK: Done! - diff --git a/test/passes/expand-whens/reg-wdc.fir b/test/passes/expand-whens/reg-wdc.fir deleted file mode 100644 index 6e8e7c04..00000000 --- a/test/passes/expand-whens/reg-wdc.fir +++ /dev/null @@ -1,26 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -circuit top : - module top : - input clk : Clock - input reset : UInt<1> - wire p : UInt - p <= UInt(1) - when p : - reg r : UInt,clk with : - reset => (reset,r) - r <= UInt(2) - -; CHECK: Expand Whens - -; CHECK: circuit top : -; CHECK: module top : -; CHECK: wire p : UInt -; CHECK: reg r : UInt<2>, clk with : -; CHECK: reset => (reset, r) -; CHECK: p <= UInt<1>("h1") -; CHECK-NOT: r <= mux(p, UInt<2>("h2"), r) -; CHECK: r <= UInt<2>("h2") - -; CHECK: Finished Expand Whens - -; CHECK: Done! diff --git a/test/passes/infer-types/bundle.fir b/test/passes/infer-types/bundle.fir deleted file mode 100644 index 0a2d2e4f..00000000 --- a/test/passes/infer-types/bundle.fir +++ /dev/null @@ -1,32 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p ct 2>&1 | tee %s.out | FileCheck %s - -circuit top : - module top : - wire z : { x : UInt, flip y: SInt} - z.x <= UInt(1) - z.y <= SInt(1) - node x = z.x - node y = z.y - wire a : UInt<3>[10] - a[0] <= UInt(1) - a[1] <= UInt(1) - a[2] <= UInt(1) - a[3] <= UInt(1) - a[4] <= UInt(1) - a[5] <= UInt(1) - a[6] <= UInt(1) - a[7] <= UInt(1) - a[8] <= UInt(1) - a[9] <= UInt(1) - node b = a[2] - node c = a[UInt(3)] - -;CHECK: Infer Types -;CHECK: node x = z@<t:{ x : UInt, flip y : SInt}>.x@<t:UInt> -;CHECK: node y = z@<t:{ x : UInt, flip y : SInt}>.y@<t:SInt> -;CHECK: wire a : UInt<3>[10]@<t:UInt>@<t:UInt[10]@<t:UInt>> -;CHECK: node b = a@<t:UInt[10]@<t:UInt>>[2]@<t:UInt> -;CHECK: node c = a@<t:UInt[10]@<t:UInt>>[UInt<2>("h3")@<t:UInt>] -;CHECK: Finished Infer Types - - diff --git a/test/passes/infer-types/gcd.fir b/test/passes/infer-types/gcd.fir deleted file mode 100644 index 398a4944..00000000 --- a/test/passes/infer-types/gcd.fir +++ /dev/null @@ -1,57 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p ct 2>&1 | tee %s.out | FileCheck %s - -;CHECK: Infer Types -circuit top : - module subtracter : - input x : UInt - input y : UInt - output z : UInt - z <= tail(sub(x, y),1) - ;CHECK: z@<t:UInt> <= tail(sub(x@<t:UInt>, y@<t:UInt>)@<t:SInt>, 1)@<t:UInt> - module gcd : - input a : UInt<16> - input b : UInt<16> - input e : UInt<1> - input clk : Clock - input reset : UInt<1> - output z : UInt<16> - reg x : UInt,clk with : - reset => (reset,UInt(0)) - reg y : UInt,clk with : - reset => (reset,UInt(42)) - ; CHECK: reg x : UInt, clk@<t:Clock> with : - ;CHECK:reset => (reset@<t:UInt>, UInt<1>("h0")@<t:UInt>) - when gt(x, y) : - ;CHECK: when gt(x@<t:UInt>, y@<t:UInt>)@<t:UInt> : - inst s of subtracter - ;CHECK: inst s of subtracter : {flip x : UInt, flip y : UInt, z : UInt} - s.x <= x - s.y <= y - x <= s.z - ;CHECK: s@<t:{flip x : UInt, flip y : UInt, z : UInt}>.x@<t:UInt> <= x@<t:UInt> - ;CHECK: s@<t:{flip x : UInt, flip y : UInt, z : UInt}>.y@<t:UInt> <= y@<t:UInt> - ;CHECK: x@<t:UInt> <= s@<t:{flip x : UInt, flip y : UInt, z : UInt}>.z@<t:UInt> - else : - inst s2 of subtracter - s2.x <= x - s2.y <= y - y <= s2.z - when e : - x <= a - y <= b - z <= x - module top : - input a : UInt<16> - input b : UInt<16> - input clk : Clock - input reset : UInt<1> - output z : UInt - inst i of gcd - i.a <= a - i.b <= b - i.clk <= clk - i.reset <= reset - i.e <= UInt(1) - z <= i.z - -; CHECK: Finished Infer Types diff --git a/test/passes/infer-types/primops.fir b/test/passes/infer-types/primops.fir deleted file mode 100644 index de0f9f1d..00000000 --- a/test/passes/infer-types/primops.fir +++ /dev/null @@ -1,152 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p ct 2>&1 | tee %s.out | FileCheck %s - -;CHECK: Infer Types -circuit top : - module top : - input clk : Clock - wire a : UInt<16> - wire b : UInt<8> - wire c : SInt<16> - wire d : SInt<8> - wire e : UInt<1> - - a <= UInt(1) - b <= UInt(1) - c <= SInt(1) - d <= SInt(1) - e <= UInt(1) - - node vadd = add(a, c) ;CHECK: node vadd = add(a@<t:UInt>, c@<t:SInt>)@<t:SInt> - node wadd = add(a, b) ;CHECK: node wadd = add(a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node xadd = add(a, d) ;CHECK: node xadd = add(a@<t:UInt>, d@<t:SInt>)@<t:SInt> - node yadd = add(c, b) ;CHECK: node yadd = add(c@<t:SInt>, b@<t:UInt>)@<t:SInt> - node zadd = add(c, d) ;CHECK: node zadd = add(c@<t:SInt>, d@<t:SInt>)@<t:SInt> - - node vsub = sub(a, c) ;CHECK: node vsub = sub(a@<t:UInt>, c@<t:SInt>)@<t:SInt> - node wsub = sub(a, b) ;CHECK: node wsub = sub(a@<t:UInt>, b@<t:UInt>)@<t:SInt> - node xsub = sub(a, d) ;CHECK: node xsub = sub(a@<t:UInt>, d@<t:SInt>)@<t:SInt> - node ysub = sub(c, b) ;CHECK: node ysub = sub(c@<t:SInt>, b@<t:UInt>)@<t:SInt> - node zsub = sub(c, d) ;CHECK: node zsub = sub(c@<t:SInt>, d@<t:SInt>)@<t:SInt> - - node vmul = mul(a, c) ;CHECK: node vmul = mul(a@<t:UInt>, c@<t:SInt>)@<t:SInt> - node wmul = mul(a, b) ;CHECK: node wmul = mul(a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node xmul = mul(a, d) ;CHECK: node xmul = mul(a@<t:UInt>, d@<t:SInt>)@<t:SInt> - node ymul = mul(c, b) ;CHECK: node ymul = mul(c@<t:SInt>, b@<t:UInt>)@<t:SInt> - node zmul = mul(c, d) ;CHECK: node zmul = mul(c@<t:SInt>, d@<t:SInt>)@<t:SInt> - - node vdiv = div(a, c) ;CHECK: node vdiv = div(a@<t:UInt>, c@<t:SInt>)@<t:SInt> - node wdiv = div(a, b) ;CHECK: node wdiv = div(a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node xdiv = div(a, d) ;CHECK: node xdiv = div(a@<t:UInt>, d@<t:SInt>)@<t:SInt> - node ydiv = div(c, b) ;CHECK: node ydiv = div(c@<t:SInt>, b@<t:UInt>)@<t:SInt> - node zdiv = div(c, d) ;CHECK: node zdiv = div(c@<t:SInt>, d@<t:SInt>)@<t:SInt> - - node vrem = rem(a, c) ;CHECK: node vrem = rem(a@<t:UInt>, c@<t:SInt>)@<t:UInt> - node wrem = rem(a, b) ;CHECK: node wrem = rem(a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node xrem = rem(a, d) ;CHECK: node xrem = rem(a@<t:UInt>, d@<t:SInt>)@<t:UInt> - node yrem = rem(c, b) ;CHECK: node yrem = rem(c@<t:SInt>, b@<t:UInt>)@<t:SInt> - node zrem = rem(c, d) ;CHECK: node zrem = rem(c@<t:SInt>, d@<t:SInt>)@<t:SInt> - - node vlt = lt(a, c) ;CHECK: node vlt = lt(a@<t:UInt>, c@<t:SInt>)@<t:UInt> - node wlt = lt(a, b) ;CHECK: node wlt = lt(a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node xlt = lt(a, d) ;CHECK: node xlt = lt(a@<t:UInt>, d@<t:SInt>)@<t:UInt> - node ylt = lt(c, b) ;CHECK: node ylt = lt(c@<t:SInt>, b@<t:UInt>)@<t:UInt> - node zlt = lt(c, d) ;CHECK: node zlt = lt(c@<t:SInt>, d@<t:SInt>)@<t:UInt> - - node vleq = leq(a, c) ;CHECK: node vleq = leq(a@<t:UInt>, c@<t:SInt>)@<t:UInt> - node wleq = leq(a, b) ;CHECK: node wleq = leq(a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node xleq = leq(a, d) ;CHECK: node xleq = leq(a@<t:UInt>, d@<t:SInt>)@<t:UInt> - node yleq = leq(c, b) ;CHECK: node yleq = leq(c@<t:SInt>, b@<t:UInt>)@<t:UInt> - node zleq = leq(c, d) ;CHECK: node zleq = leq(c@<t:SInt>, d@<t:SInt>)@<t:UInt> - - node vgt = gt(a, c) ;CHECK: node vgt = gt(a@<t:UInt>, c@<t:SInt>)@<t:UInt> - node wgt = gt(a, b) ;CHECK: node wgt = gt(a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node xgt = gt(a, d) ;CHECK: node xgt = gt(a@<t:UInt>, d@<t:SInt>)@<t:UInt> - node ygt = gt(c, b) ;CHECK: node ygt = gt(c@<t:SInt>, b@<t:UInt>)@<t:UInt> - node zgt = gt(c, d) ;CHECK: node zgt = gt(c@<t:SInt>, d@<t:SInt>)@<t:UInt> - - node vgeq = geq(a, c) ;CHECK: node vgeq = geq(a@<t:UInt>, c@<t:SInt>)@<t:UInt> - node wgeq = geq(a, b) ;CHECK: node wgeq = geq(a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node xgeq = geq(a, d) ;CHECK: node xgeq = geq(a@<t:UInt>, d@<t:SInt>)@<t:UInt> - node ygeq = geq(c, b) ;CHECK: node ygeq = geq(c@<t:SInt>, b@<t:UInt>)@<t:UInt> - node zgeq = geq(c, d) ;CHECK: node zgeq = geq(c@<t:SInt>, d@<t:SInt>)@<t:UInt> - - node veq = eq(a, c) ;CHECK: node veq = eq(a@<t:UInt>, c@<t:SInt>)@<t:UInt> - node weq = eq(a, b) ;CHECK: node weq = eq(a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node xeq = eq(a, d) ;CHECK: node xeq = eq(a@<t:UInt>, d@<t:SInt>)@<t:UInt> - node yeq = eq(c, b) ;CHECK: node yeq = eq(c@<t:SInt>, b@<t:UInt>)@<t:UInt> - node zeq = eq(c, d) ;CHECK: node zeq = eq(c@<t:SInt>, d@<t:SInt>)@<t:UInt> - - node vneq = neq(a, c) ;CHECK: node vneq = neq(a@<t:UInt>, c@<t:SInt>)@<t:UInt> - node wneq = neq(a, b) ;CHECK: node wneq = neq(a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node xneq = neq(a, d) ;CHECK: node xneq = neq(a@<t:UInt>, d@<t:SInt>)@<t:UInt> - node yneq = neq(c, b) ;CHECK: node yneq = neq(c@<t:SInt>, b@<t:UInt>)@<t:UInt> - node zneq = neq(c, d) ;CHECK: node zneq = neq(c@<t:SInt>, d@<t:SInt>)@<t:UInt> - - node vpad = pad(a, 10) ;CHECK: node vpad = pad(a@<t:UInt>, 10)@<t:UInt> - node wpad = pad(a, 10) ;CHECK: node wpad = pad(a@<t:UInt>, 10)@<t:UInt> - node zpad = pad(c, 10) ;CHECK: node zpad = pad(c@<t:SInt>, 10)@<t:SInt> - - node vasUInt = asUInt(d) ;CHECK: node vasUInt = asUInt(d@<t:SInt>)@<t:UInt> - node wasUInt = asUInt(a) ;CHECK: node wasUInt = asUInt(a@<t:UInt>)@<t:UInt> - node zasUInt = asUInt(clk) ;CHECK: node zasUInt = asUInt(clk@<t:Clock>)@<t:UInt> - - node vasSInt = asSInt(a) ;CHECK: node vasSInt = asSInt(a@<t:UInt>)@<t:SInt> - node wasSInt = asSInt(c) ;CHECK: node wasSInt = asSInt(c@<t:SInt>)@<t:SInt> - node zasSInt = asSInt(clk) ;CHECK: node zasSInt = asSInt(clk@<t:Clock>)@<t:SInt> - - node vasClock = asClock(a) ;CHECK: node vasClock = asClock(a@<t:UInt>)@<t:Clock> - node wasClock = asClock(c) ;CHECK: node wasClock = asClock(c@<t:SInt>)@<t:Clock> - node zasClock = asClock(clk) ;CHECK: node zasClock = asClock(clk@<t:Clock>)@<t:Clock> - - node vshl = shl(a, 10) ;CHECK: node vshl = shl(a@<t:UInt>, 10)@<t:UInt> - node wshl = shl(a, 10) ;CHECK: node wshl = shl(a@<t:UInt>, 10)@<t:UInt> - node zshl = shl(c, 10) ;CHECK: node zshl = shl(c@<t:SInt>, 10)@<t:SInt> - - node vdshl = dshl(a, a) ;CHECK: node vdshl = dshl(a@<t:UInt>, a@<t:UInt>)@<t:UInt> - node wdshl = dshl(a, a) ;CHECK: node wdshl = dshl(a@<t:UInt>, a@<t:UInt>)@<t:UInt> - node zdshl = dshl(c, a) ;CHECK: node zdshl = dshl(c@<t:SInt>, a@<t:UInt>)@<t:SInt> - - node vdshr = dshr(a, a) ;CHECK: node vdshr = dshr(a@<t:UInt>, a@<t:UInt>)@<t:UInt> - node wdshr = dshr(a, a) ;CHECK: node wdshr = dshr(a@<t:UInt>, a@<t:UInt>)@<t:UInt> - node zdshr = dshr(c, a) ;CHECK: node zdshr = dshr(c@<t:SInt>, a@<t:UInt>)@<t:SInt> - - node vshr = shr(a, 10) ;CHECK: node vshr = shr(a@<t:UInt>, 10)@<t:UInt> - node wshr = shr(a, 10) ;CHECK: node wshr = shr(a@<t:UInt>, 10)@<t:UInt> - node zshr = shr(c, 10) ;CHECK: node zshr = shr(c@<t:SInt>, 10)@<t:SInt> - - node vcvt = cvt(a) ;CHECK: node vcvt = cvt(a@<t:UInt>)@<t:SInt> - node wcvt = cvt(a) ;CHECK: node wcvt = cvt(a@<t:UInt>)@<t:SInt> - node zcvt = cvt(c) ;CHECK: node zcvt = cvt(c@<t:SInt>)@<t:SInt> - - node vneg = neg(a) ;CHECK: node vneg = neg(a@<t:UInt>)@<t:SInt> - node wneg = neg(a) ;CHECK: node wneg = neg(a@<t:UInt>)@<t:SInt> - node zneg = neg(c) ;CHECK: node zneg = neg(c@<t:SInt>)@<t:SInt> - - node wnot = not(a) ;CHECK: node wnot = not(a@<t:UInt>)@<t:UInt> - node unot = not(c) ;CHECK: node unot = not(c@<t:SInt>)@<t:UInt> - - node WAND = and(a, b) ;CHECK: node WAND = and(a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node uand = and(c, d) ;CHECK: node uand = and(c@<t:SInt>, d@<t:SInt>)@<t:UInt> - - node WOR = or(a, b) ;CHECK: node WOR = or(a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node uor = or(c, d) ;CHECK: node uor = or(c@<t:SInt>, d@<t:SInt>)@<t:UInt> - - node wxor = xor(a, b) ;CHECK: node wxor = xor(a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node uxor = xor(c, d) ;CHECK: node uxor = xor(c@<t:SInt>, d@<t:SInt>)@<t:UInt> - - node wbits = bits(a, 2, 0) ;CHECK: node wbits = bits(a@<t:UInt>, 2, 0)@<t:UInt> - node ubits = bits(c, 2, 0) ;CHECK: node ubits = bits(c@<t:SInt>, 2, 0)@<t:UInt> - - node xcat = cat(a, b) ;CHECK: node xcat = cat(a@<t:UInt>, b@<t:UInt>)@<t:UInt> - - node uandr = andr(a, b, a) ;CHECK: node uandr = andr(a@<t:UInt>, b@<t:UInt>, a@<t:UInt>)@<t:UInt> - node uorr = orr(a, b, a) ;CHECK: node uorr = orr(a@<t:UInt>, b@<t:UInt>, a@<t:UInt>)@<t:UInt> - node uxorr = xorr(a, b, a) ;CHECK: node uxorr = xorr(a@<t:UInt>, b@<t:UInt>, a@<t:UInt>)@<t:UInt> - - node whead = head(a, 2) ;CHECK: node whead = head(a@<t:UInt>, 2)@<t:UInt> - node uhead = head(c, 2) ;CHECK: node uhead = head(c@<t:SInt>, 2)@<t:UInt> - - node wtail = tail(a, 2) ;CHECK: node wtail = tail(a@<t:UInt>, 2)@<t:UInt> - node utail = tail(c, 2) ;CHECK: node utail = tail(c@<t:SInt>, 2)@<t:UInt> - -;CHECK: Finished Infer Types diff --git a/test/passes/infer-widths/dsh.fir b/test/passes/infer-widths/dsh.fir deleted file mode 100644 index f36b8ad4..00000000 --- a/test/passes/infer-widths/dsh.fir +++ /dev/null @@ -1,28 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p cd 2>&1 | tee %s.out | FileCheck %s - -;CHECK: Infer Widths - -circuit top : - module top : - wire x : UInt<16> - wire z : SInt<16> - wire y : UInt<3> - wire a : UInt - wire b : SInt - wire c : UInt - wire d : SInt - x <= UInt(1) - y <= UInt(1) - z <= SInt(1) - - a <= dshl(x,y) - b <= dshl(z,y) - c <= dshr(x,y) - d <= dshr(z,y) - - -; CHECK: wire a : UInt<23> -; CHECK: wire b : SInt<23> -; CHECK: wire c : UInt<16> -; CHECK: wire d : SInt<16> -; CHECK: Finished Infer Widths diff --git a/test/passes/infer-widths/gcd.fir b/test/passes/infer-widths/gcd.fir deleted file mode 100644 index 1333fbda..00000000 --- a/test/passes/infer-widths/gcd.fir +++ /dev/null @@ -1,49 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p ctd 2>&1 | tee %s.out | FileCheck %s - -;CHECK: Infer Widths -circuit top : - module subtracter : - input x : UInt - input y : UInt - output q : UInt - q <= tail(sub(x, y),1) - module gcd : - input a : UInt<16> - input b : UInt<16> - input e : UInt<1> - input clk : Clock - input reset : UInt<1> - output z : UInt<16> - reg x : UInt,clk with : - reset => (reset,UInt(0)) - reg y : UInt,clk with : - reset => (reset,UInt(42)) - when gt(x, y) : - inst s of subtracter - s.x <= x - s.y <= y - x <= s.q - else : - inst s2 of subtracter - s2.x <= x - s2.y <= y - y <= s2.q - when e : - x <= a - y <= b - z <= x - module top : - input a : UInt<16> - input b : UInt<16> - input clk : Clock - input reset : UInt<1> - output z : UInt - inst i of gcd - i.a <= a - i.b <= b - i.clk <= clk - i.reset <= reset - i.e <= UInt(1) - z <= i.z - -; CHECK: Finished Infer Widths diff --git a/test/passes/infer-widths/shr.fir b/test/passes/infer-widths/shr.fir deleted file mode 100644 index 6a918ba9..00000000 --- a/test/passes/infer-widths/shr.fir +++ /dev/null @@ -1,129 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s - -;CHECK: Infer Widths -; CHECK: Finished Infer Widths - -circuit MemSerdes : - module MemSerdes : - input clock : Clock - input reset : UInt<1> - input wide : {req_cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<26>, tag : UInt<7>, rw : UInt<1>}}, req_data : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, tag : UInt<7>}}} - output narrow : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, flip resp : {valid : UInt<1>, bits : UInt<16>}} - - wide.resp.bits.tag <= UInt<1>("h00") - wide.resp.bits.data <= UInt<1>("h00") - wide.resp.valid <= UInt<1>("h00") - wide.req_data.ready <= UInt<1>("h00") - wide.req_cmd.ready <= UInt<1>("h00") - narrow.req.bits <= UInt<1>("h00") - narrow.req.valid <= UInt<1>("h00") - - node T_218961 = cat(wide.req_cmd.bits.tag, wide.req_cmd.bits.rw) - node T_218962 = cat(wide.req_cmd.bits.addr, T_218961) - reg out_buf : UInt, clock with : - reset => ( reset, out_buf) - reg in_buf : UInt, clock with : - reset => ( reset, in_buf) - reg state : UInt<3>, clock with : - reset => ( reset,UInt<3>("h00")) - reg send_cnt : UInt<3>, clock with : - reset => ( reset, UInt<3>("h00")) - reg data_send_cnt : UInt<2>, clock with : - reset => ( reset, UInt<2>("h00")) - node T_218984 = eq(send_cnt, UInt<2>("h02")) - node adone = and(narrow.req.ready, T_218984) - node T_218987 = eq(send_cnt, UInt<3>("h07")) - node ddone = and(narrow.req.ready, T_218987) - - node T_218989 = and(narrow.req.valid, narrow.req.ready) - when T_218989 : - node T_218991 = tail(add(send_cnt, UInt<1>("h01")),1) - send_cnt <= T_218991 - node T_218992 = shr(out_buf, 16) - out_buf <= T_218992 - - node T_218993 = and(wide.req_cmd.valid, wide.req_cmd.ready) - when T_218993 : - node T_218994 = cat(wide.req_cmd.bits.tag, wide.req_cmd.bits.rw) - node T_218995 = cat(wide.req_cmd.bits.addr, T_218994) - out_buf <= T_218995 - - node T_218996 = and(wide.req_data.valid, wide.req_data.ready) - when T_218996 : out_buf <= wide.req_data.bits.data - node T_218997 = eq(state, UInt<3>("h00")) - wide.req_cmd.ready <= T_218997 - node T_218998 = eq(state, UInt<3>("h03")) - wide.req_data.ready <= T_218998 - node T_218999 = eq(state, UInt<3>("h01")) - node T_219000 = eq(state, UInt<3>("h02")) - node T_219001 = or(T_218999, T_219000) - node T_219002 = eq(state, UInt<3>("h04")) - node T_219003 = or(T_219001, T_219002) - narrow.req.valid <= T_219003 - narrow.req.bits <= out_buf - - - node T_219004 = eq(state, UInt<3>("h00")) - node T_219005 = and(T_219004, wide.req_cmd.valid) - when T_219005 : - node T_219006 = mux(wide.req_cmd.bits.rw, UInt<3>("h02"), UInt<3>("h01")) - state <= T_219006 - - - node T_219007 = eq(state, UInt<3>("h01")) - node T_219008 = and(T_219007, adone) - when T_219008 : - state <= UInt<3>("h00") - send_cnt <= UInt<1>("h00") - - - node T_219010 = eq(state, UInt<3>("h02")) - node T_219011 = and(T_219010, adone) - when T_219011 : - state <= UInt<3>("h03") - send_cnt <= UInt<1>("h00") - - - node T_219013 = eq(state, UInt<3>("h03")) - node T_219014 = and(T_219013, wide.req_data.valid) - when T_219014 : state <= UInt<3>("h04") - - - node T_219015 = eq(state, UInt<3>("h04")) - node T_219016 = and(T_219015, ddone) - when T_219016 : - node T_219018 = tail(add(data_send_cnt, UInt<1>("h01")),1) - data_send_cnt <= T_219018 - node T_219020 = eq(data_send_cnt, UInt<2>("h03")) - node T_219021 = mux(T_219020, UInt<3>("h00"), UInt<3>("h03")) - state <= T_219021 - send_cnt <= UInt<1>("h00") - reg recv_cnt : UInt<4>, clock with : - reset => ( reset, UInt<4>("h00")) - reg data_recv_cnt : UInt<2>, clock with : - reset => ( reset, UInt<2>("h00")) - reg resp_val : UInt<1>, clock with : - reset => ( reset, UInt<1>("h00")) - resp_val <= UInt<1>("h00") - when narrow.resp.valid : - node T_219031 = tail(add(recv_cnt, UInt<1>("h01")),1) - recv_cnt <= T_219031 - - node T_219033 = eq(recv_cnt, UInt<4>("h08")) - when T_219033 : - recv_cnt <= UInt<1>("h00") - node T_219036 = tail(add(data_recv_cnt, UInt<1>("h01")),1) - data_recv_cnt <= T_219036 - resp_val <= UInt<1>("h01") - node T_219038 = bits(in_buf, 143, 16) - node T_219039 = cat(narrow.resp.bits, T_219038) - in_buf <= T_219039 - wide.resp.valid <= resp_val - wire T_219043 : {data : UInt<128>, tag : UInt<7>} - T_219043.tag <= UInt<1>("h00") - T_219043.data <= UInt<1>("h00") - node T_219048 = bits(in_buf, 6, 0) - T_219043.tag <= T_219048 - node T_219049 = bits(in_buf, 134, 7) - T_219043.data <= T_219049 - wide.resp.bits <- T_219043 diff --git a/test/passes/infer-widths/simple.fir b/test/passes/infer-widths/simple.fir deleted file mode 100644 index 63b31a32..00000000 --- a/test/passes/infer-widths/simple.fir +++ /dev/null @@ -1,28 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p cTwd 2>&1 | tee %s.out | FileCheck %s - -;CHECK: Infer Widths -circuit top : - module top : - input clk : Clock - input reset : UInt<1> - wire e : UInt<30> - e <= UInt(1) - reg y : UInt,clk with : - reset => (reset,y) - y <= e - - wire a : UInt<20> - a <= UInt(1) - wire b : UInt<10> - b <= UInt(1) - wire c : UInt - c <= UInt(1) - wire z : UInt - - z <= mux(c,a,b) - - - -; CHECK: Finished Infer Widths -; CHECK: Done! - diff --git a/test/passes/inline/gcd.fir b/test/passes/inline/gcd.fir deleted file mode 100644 index 781b949c..00000000 --- a/test/passes/inline/gcd.fir +++ /dev/null @@ -1,50 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; XFAIL: * - -;CHECK: Inline Instances -circuit top : - module subtracter : - input x : UInt - input y : UInt - output q : UInt - q <= subw(x, y) - module gcd : - input a : UInt<16> - input b : UInt<16> - input e : UInt<1> - input clk : Clock - input reset : UInt<1> - output z : UInt<16> - reg x : UInt,clk,reset - reg y : UInt,clk,reset - onreset x <= UInt(0) - onreset y <= UInt(42) - when gt(x, y) : - inst s of subtracter - s.x <= x - s.y <= y - x <= s.q - else : - inst s2 of subtracter - s2.x <= x - s2.y <= y - y <= s2.q - when e : - x <= a - y <= b - z <= x - module top : - input a : UInt<16> - input b : UInt<16> - input clk : Clock - input reset : UInt<1> - output z : UInt - inst i of gcd - i.a <= a - i.b <= b - i.clk <= clk - i.reset <= reset - i.e <= UInt(1) - z <= i.z - -; CHECK: Finished Inline Instances diff --git a/test/passes/jacktest/ALUTop.fir b/test/passes/jacktest/ALUTop.fir deleted file mode 100644 index a0aadb11..00000000 --- a/test/passes/jacktest/ALUTop.fir +++ /dev/null @@ -1,117 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: Done! -circuit ALUTop : - module ALU : - input B : UInt<32> - output out : UInt<32> - output sum : UInt<32> - input A : UInt<32> - input alu_op : UInt<4> - - node shamt = bits(B, 4, 0) - node T_157 = tail(add(A, B),1) - node T_158 = tail(sub(A, B),1) - node T_159 = cvt(A) - node T_160 = dshr(T_159, shamt) - node T_161 = asUInt(T_160) - node T_162 = dshr(A, shamt) - node T_163 = dshl(A, shamt) - node T_164 = bits(T_163, 31, 0) - node T_165 = cvt(A) - node T_166 = cvt(B) - node T_167 = lt(T_165, T_166) - node T_168 = asUInt(T_167) - node T_169 = lt(A, B) - node T_170 = asUInt(T_169) - node T_171 = and(A, B) - node T_172 = or(A, B) - node T_173 = xor(A, B) - node T_174 = eq(UInt<4>(10), alu_op) - node T_175 = mux(T_174, A, B) - node T_176 = eq(UInt<4>(4), alu_op) - node T_177 = mux(T_176, T_173, T_175) - node T_178 = eq(UInt<4>(3), alu_op) - node T_179 = mux(T_178, T_172, T_177) - node T_180 = eq(UInt<4>(2), alu_op) - node T_181 = mux(T_180, T_171, T_179) - node T_182 = eq(UInt<4>(7), alu_op) - node T_183 = mux(T_182, T_170, T_181) - node T_184 = eq(UInt<4>(5), alu_op) - node T_185 = mux(T_184, T_168, T_183) - node T_186 = eq(UInt<4>(6), alu_op) - node T_187 = mux(T_186, T_164, T_185) - node T_188 = eq(UInt<4>(8), alu_op) - node T_189 = mux(T_188, T_162, T_187) - node T_190 = eq(UInt<4>(9), alu_op) - node T_191 = mux(T_190, T_161, T_189) - node T_192 = eq(UInt<4>(1), alu_op) - node T_193 = mux(T_192, T_158, T_191) - node T_194 = eq(UInt<4>(0), alu_op) - node oot = mux(T_194, T_157, T_193) - node T_195 = bits(oot, 31, 0) - out <= T_195 - node T_196 = bits(alu_op, 0, 0) - node T_197 = tail(sub(UInt<1>(0), B),1) - node T_198 = mux(T_196, T_197, B) - node T_199 = tail(add(A, T_198),1) - sum <= T_199 - module ALUdec : - input opcode : UInt<7> - input funct : UInt<3> - input add_rshift_type : UInt<1> - output alu_op : UInt<4> - - node T_200 = mux(add_rshift_type, UInt<4>(1), UInt<4>(0)) - node T_201 = mux(add_rshift_type, UInt<4>(9), UInt<4>(8)) - node T_202 = eq(UInt<3>(5), funct) - node T_203 = mux(T_202, T_201, UInt<4>(15)) - node T_204 = eq(UInt<3>(7), funct) - node T_205 = mux(T_204, UInt<4>(2), T_203) - node T_206 = eq(UInt<3>(6), funct) - node T_207 = mux(T_206, UInt<4>(3), T_205) - node T_208 = eq(UInt<3>(4), funct) - node T_209 = mux(T_208, UInt<4>(4), T_207) - node T_210 = eq(UInt<3>(3), funct) - node T_211 = mux(T_210, UInt<4>(7), T_209) - node T_212 = eq(UInt<3>(2), funct) - node T_213 = mux(T_212, UInt<4>(5), T_211) - node T_214 = eq(UInt<3>(1), funct) - node T_215 = mux(T_214, UInt<4>(6), T_213) - node T_216 = eq(UInt<3>(0), funct) - node alu_op1 = mux(T_216, T_200, T_215) - node T_217 = eq(UInt<7>(19), opcode) - node T_218 = mux(T_217, alu_op1, UInt<4>(15)) - node T_219 = eq(UInt<7>(51), opcode) - node T_220 = mux(T_219, alu_op1, T_218) - node T_221 = eq(UInt<7>(3), opcode) - node T_222 = mux(T_221, UInt<4>(0), T_220) - node T_223 = eq(UInt<7>(35), opcode) - node T_224 = mux(T_223, UInt<4>(0), T_222) - node T_225 = eq(UInt<7>(99), opcode) - node T_226 = mux(T_225, UInt<4>(0), T_224) - node T_227 = eq(UInt<7>(103), opcode) - node T_228 = mux(T_227, UInt<4>(0), T_226) - node T_229 = eq(UInt<7>(111), opcode) - node T_230 = mux(T_229, UInt<4>(0), T_228) - node T_231 = eq(UInt<7>(23), opcode) - node T_232 = mux(T_231, UInt<4>(0), T_230) - node T_233 = eq(UInt<7>(55), opcode) - node alu_op2 = mux(T_233, UInt<4>(11), T_232) - alu_op <= alu_op2 - module ALUTop : - input B : UInt<32> - output out : UInt<32> - input A : UInt<32> - input opcode : UInt<7> - input funct : UInt<3> - input add_rshift_type : UInt<1> - - inst alu of ALU - inst alu_dec of ALUdec - alu_dec.opcode <= opcode - alu_dec.funct <= funct - alu_dec.add_rshift_type <= add_rshift_type - alu.A <= A - alu.B <= B - out <= alu.out - alu.alu_op <= alu_dec.alu_op diff --git a/test/passes/jacktest/ComplexAssign.fir b/test/passes/jacktest/ComplexAssign.fir deleted file mode 100644 index 9ce51652..00000000 --- a/test/passes/jacktest/ComplexAssign.fir +++ /dev/null @@ -1,15 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: Done! -circuit ComplexAssign : - module ComplexAssign : - input in : {re : UInt<10>, im : UInt<10>} - output out : {re : UInt<10>, im : UInt<10>} - input e : UInt<1> - when e : - wire T_18 : {re : UInt<10>, im : UInt<10>} - T_18 <= in - out.re <= T_18.re - out.im <= T_18.im - else : - out.re <= UInt<1>(0) - out.im <= UInt<1>(0) diff --git a/test/passes/jacktest/Counter.fir b/test/passes/jacktest/Counter.fir deleted file mode 100644 index 266c1849..00000000 --- a/test/passes/jacktest/Counter.fir +++ /dev/null @@ -1,18 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: Done! -circuit Counter : - module Counter : - input inc : UInt<1> - input clk : Clock - input reset : UInt<1> - output tot : UInt<8> - input amt : UInt<4> - - reg T_13 : UInt<8>,clk with : - reset => (reset,UInt<8>(0)) - when inc : - node T_14 = tail(add(T_13, amt),1) - node T_15 = gt(T_14, UInt<8>(255)) - node T_16 = mux(T_15, UInt<1>(0), T_14) - T_13 <= T_16 - tot <= T_13 diff --git a/test/passes/jacktest/EnableShiftRegister.fir b/test/passes/jacktest/EnableShiftRegister.fir deleted file mode 100644 index 9927e83f..00000000 --- a/test/passes/jacktest/EnableShiftRegister.fir +++ /dev/null @@ -1,24 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: Done! -circuit EnableShiftRegister : - module EnableShiftRegister : - input in : UInt<4> - input clk : Clock - input reset : UInt<1> - output out : UInt<4> - input shift : UInt<1> - - reg r0 : UInt<4>,clk with : - reset => (reset,UInt<4>(0)) - reg r1 : UInt<4>,clk with : - reset => (reset,UInt<4>(0)) - reg r2 : UInt<4>,clk with : - reset => (reset,UInt<4>(0)) - reg r3 : UInt<4>,clk with : - reset => (reset,UInt<4>(0)) - when shift : - r0 <= in - r1 <= r0 - r2 <= r1 - r3 <= r2 - out <= r3 diff --git a/test/passes/jacktest/LFSR16.fir b/test/passes/jacktest/LFSR16.fir deleted file mode 100644 index b3fb05cc..00000000 --- a/test/passes/jacktest/LFSR16.fir +++ /dev/null @@ -1,23 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: Done! -circuit LFSR16 : - module LFSR16 : - output out : UInt<16> - input inc : UInt<1> - input clk : Clock - input reset : UInt<1> - - reg res : UInt<16>,clk with : - reset => (reset,UInt<16>(1)) - when inc : - node T_16 = bits(res, 0, 0) - node T_17 = bits(res, 2, 2) - node T_18 = xor(T_16, T_17) - node T_19 = bits(res, 3, 3) - node T_20 = xor(T_18, T_19) - node T_21 = bits(res, 5, 5) - node T_22 = xor(T_20, T_21) - node T_23 = bits(res, 15, 1) - node T_24 = cat(T_22, T_23) - res <= T_24 - out <= res diff --git a/test/passes/jacktest/MemorySearch.fir b/test/passes/jacktest/MemorySearch.fir deleted file mode 100644 index 39c19dda..00000000 --- a/test/passes/jacktest/MemorySearch.fir +++ /dev/null @@ -1,35 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: Done! -circuit MemorySearch : - module MemorySearch : - input target : UInt<4> - output address : UInt<3> - input en : UInt<1> - input clk : Clock - input reset : UInt<1> - output done : UInt<1> - - reg index : UInt<3>,clk with : - reset => (reset,UInt<3>(0)) - wire elts : UInt<4>[7] - elts[0] <= UInt<4>(0) - elts[1] <= UInt<4>(4) - elts[2] <= UInt<4>(15) - elts[3] <= UInt<4>(14) - elts[4] <= UInt<4>(2) - elts[5] <= UInt<4>(5) - elts[6] <= UInt<4>(13) - node elt = elts[index] - node T_35 = not(en) - node T_36 = eq(elt, target) - node T_37 = eq(index, UInt<3>(7)) - node T_38 = or(T_36, T_37) - node end = and(T_35, T_38) - when en : index <= UInt<1>(0) - else : - node T_39 = not(end) - when T_39 : - node T_40 = tail(add(index, UInt<1>(1)),1) - index <= T_40 - done <= end - address <= index diff --git a/test/passes/jacktest/ModuleVec.fir b/test/passes/jacktest/ModuleVec.fir deleted file mode 100644 index 6f9b699b..00000000 --- a/test/passes/jacktest/ModuleVec.fir +++ /dev/null @@ -1,28 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: Done! -circuit ModuleVec : - module PlusOne : - input in : UInt<32> - output out : UInt<32> - - node T_33 = tail(add(in, UInt<1>(1)),1) - out <= T_33 - module PlusOne_25 : - input in : UInt<32> - output out : UInt<32> - - node T_34 = tail(add(in, UInt<1>(1)),1) - out <= T_34 - module ModuleVec : - input ins : UInt<32>[2] - output outs : UInt<32>[2] - - inst T_35 of PlusOne - inst T_36 of PlusOne_25 - wire pluses : {flip in : UInt<32>, out : UInt<32>}[2] - pluses[0] <= T_35 - pluses[1] <= T_36 - pluses[0].in <= ins[0] - outs[0] <= pluses[0].out - pluses[1].in <= ins[1] - outs[1] <= pluses[1].out diff --git a/test/passes/jacktest/Mul.fir b/test/passes/jacktest/Mul.fir deleted file mode 100644 index 370c84a7..00000000 --- a/test/passes/jacktest/Mul.fir +++ /dev/null @@ -1,29 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: Done! -circuit Mul : - module Mul : - input x : UInt<2> - input y : UInt<2> - output z : UInt<4> - - wire tbl : UInt<4>[16] - tbl[0] <= UInt<4>(0) - tbl[1] <= UInt<4>(0) - tbl[2] <= UInt<4>(0) - tbl[3] <= UInt<4>(0) - tbl[4] <= UInt<4>(0) - tbl[5] <= UInt<4>(1) - tbl[6] <= UInt<4>(2) - tbl[7] <= UInt<4>(3) - tbl[8] <= UInt<4>(0) - tbl[9] <= UInt<4>(2) - tbl[10] <= UInt<4>(4) - tbl[11] <= UInt<4>(6) - tbl[12] <= UInt<4>(0) - tbl[13] <= UInt<4>(3) - tbl[14] <= UInt<4>(6) - tbl[15] <= UInt<4>(9) - node T_42 = shl(x, 2) - node T_43 = or(T_42, y) - node T_44 = tbl[T_43] - z <= T_44 diff --git a/test/passes/jacktest/RegisterVecShift.fir b/test/passes/jacktest/RegisterVecShift.fir deleted file mode 100644 index f138d00a..00000000 --- a/test/passes/jacktest/RegisterVecShift.fir +++ /dev/null @@ -1,31 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: Done! -circuit RegisterVecShift : - module RegisterVecShift : - input load : UInt<1> - input clk : Clock - input reset : UInt<1> - output out : UInt<4> - input shift : UInt<1> - input ins : UInt<4>[4] - - reg delays : UInt<4>[4],clk with : - reset => (reset,delays) - when reset : - wire T_33 : UInt<4>[4] - T_33[0] <= UInt<4>(0) - T_33[1] <= UInt<4>(0) - T_33[2] <= UInt<4>(0) - T_33[3] <= UInt<4>(0) - delays <= T_33 - when load : - delays[0] <= ins[0] - delays[1] <= ins[1] - delays[2] <= ins[2] - delays[3] <= ins[3] - else : when shift : - delays[0] <= ins[0] - delays[1] <= delays[0] - delays[2] <= delays[1] - delays[3] <= delays[2] - out <= delays[3] diff --git a/test/passes/jacktest/Rom.fir b/test/passes/jacktest/Rom.fir deleted file mode 100644 index db76b9c7..00000000 --- a/test/passes/jacktest/Rom.fir +++ /dev/null @@ -1,26 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: Done! -circuit Rom : - module Rom : - output out : UInt<5> - input addr : UInt<4> - - wire r : UInt<5>[16] - r[0] <= UInt<5>(0) - r[1] <= UInt<5>(2) - r[2] <= UInt<5>(4) - r[3] <= UInt<5>(6) - r[4] <= UInt<5>(8) - r[5] <= UInt<5>(10) - r[6] <= UInt<5>(12) - r[7] <= UInt<5>(14) - r[8] <= UInt<5>(16) - r[9] <= UInt<5>(18) - r[10] <= UInt<5>(20) - r[11] <= UInt<5>(22) - r[12] <= UInt<5>(24) - r[13] <= UInt<5>(26) - r[14] <= UInt<5>(28) - r[15] <= UInt<5>(30) - node T_39 = r[addr] - out <= T_39 diff --git a/test/passes/jacktest/RouterUnitTest.fir b/test/passes/jacktest/RouterUnitTest.fir deleted file mode 100644 index dec4083e..00000000 --- a/test/passes/jacktest/RouterUnitTest.fir +++ /dev/null @@ -1,1076 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; CHECK: Done! - -circuit RouterUnitTester : - module Router : - input clk : Clock - input reset : UInt<1> - output io : {read_routing_table_request : {ready : UInt<1>, flip valid : UInt<1>, flip bits : {addr : UInt<32>}}, read_routing_table_response : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<8>}, load_routing_table_request : {ready : UInt<1>, flip valid : UInt<1>, flip bits : {addr : UInt<32>, data : UInt<32>}}, in : {ready : UInt<1>, flip valid : UInt<1>, flip bits : {header : UInt<8>, body : UInt<64>}}, outs : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : UInt<8>, body : UInt<64>}}[4]} - - io.outs[0].bits.body <= UInt<1>("h00") - io.outs[0].bits.header <= UInt<1>("h00") - io.outs[0].valid <= UInt<1>("h00") - io.outs[1].bits.body <= UInt<1>("h00") - io.outs[1].bits.header <= UInt<1>("h00") - io.outs[1].valid <= UInt<1>("h00") - io.outs[2].bits.body <= UInt<1>("h00") - io.outs[2].bits.header <= UInt<1>("h00") - io.outs[2].valid <= UInt<1>("h00") - io.outs[3].bits.body <= UInt<1>("h00") - io.outs[3].bits.header <= UInt<1>("h00") - io.outs[3].valid <= UInt<1>("h00") - io.in.ready <= UInt<1>("h00") - io.load_routing_table_request.ready <= UInt<1>("h00") - io.read_routing_table_response.bits <= UInt<1>("h00") - io.read_routing_table_response.valid <= UInt<1>("h00") - io.read_routing_table_request.ready <= UInt<1>("h00") - cmem tbl : UInt<3>[15] - when reset : - infer mport T_115 = tbl[UInt<1>("h00")], clk - T_115 <= UInt<32>("h00") - infer mport T_118 = tbl[UInt<1>("h01")], clk - T_118 <= UInt<32>("h00") - infer mport T_121 = tbl[UInt<2>("h02")], clk - T_121 <= UInt<32>("h00") - infer mport T_124 = tbl[UInt<2>("h03")], clk - T_124 <= UInt<32>("h00") - infer mport T_127 = tbl[UInt<3>("h04")], clk - T_127 <= UInt<32>("h00") - infer mport T_130 = tbl[UInt<3>("h05")], clk - T_130 <= UInt<32>("h00") - infer mport T_133 = tbl[UInt<3>("h06")], clk - T_133 <= UInt<32>("h00") - infer mport T_136 = tbl[UInt<3>("h07")], clk - T_136 <= UInt<32>("h00") - infer mport T_139 = tbl[UInt<4>("h08")], clk - T_139 <= UInt<32>("h00") - infer mport T_142 = tbl[UInt<4>("h09")], clk - T_142 <= UInt<32>("h00") - infer mport T_145 = tbl[UInt<4>("h0a")], clk - T_145 <= UInt<32>("h00") - infer mport T_148 = tbl[UInt<4>("h0b")], clk - T_148 <= UInt<32>("h00") - infer mport T_151 = tbl[UInt<4>("h0c")], clk - T_151 <= UInt<32>("h00") - infer mport T_154 = tbl[UInt<4>("h0d")], clk - T_154 <= UInt<32>("h00") - infer mport T_157 = tbl[UInt<4>("h0e")], clk - T_157 <= UInt<32>("h00") - skip - io.read_routing_table_request.ready <= UInt<1>("h01") - io.load_routing_table_request.ready <= UInt<1>("h01") - io.read_routing_table_response.valid <= UInt<1>("h00") - io.read_routing_table_response.bits <= UInt<1>("h00") - io.in.ready <= UInt<1>("h01") - io.outs[0].valid <= UInt<1>("h00") - io.outs[0].bits.body <= UInt<1>("h00") - io.outs[0].bits.header <= UInt<1>("h00") - io.outs[1].valid <= UInt<1>("h00") - io.outs[1].bits.body <= UInt<1>("h00") - io.outs[1].bits.header <= UInt<1>("h00") - io.outs[2].valid <= UInt<1>("h00") - io.outs[2].bits.body <= UInt<1>("h00") - io.outs[2].bits.header <= UInt<1>("h00") - io.outs[3].valid <= UInt<1>("h00") - io.outs[3].bits.body <= UInt<1>("h00") - io.outs[3].bits.header <= UInt<1>("h00") - node T_176 = and(io.read_routing_table_request.valid, io.read_routing_table_response.ready) - when T_176 : - io.read_routing_table_request.ready <= UInt<1>("h01") - infer mport T_178 = tbl[io.read_routing_table_request.bits.addr], clk - io.read_routing_table_response.valid <= UInt<1>("h01") - io.read_routing_table_response.bits <= T_178 - skip - node T_181 = eq(T_176, UInt<1>("h00")) - node T_182 = and(T_181, io.load_routing_table_request.valid) - when T_182 : - io.load_routing_table_request.ready <= UInt<1>("h01") - infer mport T_184 = tbl[io.load_routing_table_request.bits.addr], clk - T_184 <= io.load_routing_table_request.bits.data - node T_186 = eq(reset, UInt<1>("h00")) - when T_186 : - printf(clk, UInt<1>(1), "setting tbl(%d) to %d", io.load_routing_table_request.bits.addr, io.load_routing_table_request.bits.data) - skip - skip - node T_188 = eq(T_176, UInt<1>("h00")) - node T_190 = eq(io.load_routing_table_request.valid, UInt<1>("h00")) - node T_191 = and(T_188, T_190) - node T_192 = and(T_191, io.in.valid) - when T_192 : - node T_193 = bits(io.in.bits.header, 4, 0) - infer mport T_194 = tbl[T_193], clk - when io.outs[T_194].ready : - io.in.ready <= UInt<1>("h01") - io.outs[T_194].valid <= UInt<1>("h01") - io.outs[T_194].bits <- io.in.bits - infer mport T_215 = tbl[io.in.bits.header], clk - node T_217 = eq(reset, UInt<1>("h00")) - when T_217 : - printf(clk, UInt<1>(1), "got packet to route header %d, data %d, being routed to out(%d) ", io.in.bits.header, io.in.bits.body, T_215) - skip - skip - skip - - module RouterUnitTester : - input clk : Clock - input reset : UInt<1> - output io : {} - - inst device_under_test of Router - device_under_test.io.outs[0].ready <= UInt<1>("h00") - device_under_test.io.outs[1].ready <= UInt<1>("h00") - device_under_test.io.outs[2].ready <= UInt<1>("h00") - device_under_test.io.outs[3].ready <= UInt<1>("h00") - device_under_test.io.in.bits.body <= UInt<1>("h00") - device_under_test.io.in.bits.header <= UInt<1>("h00") - device_under_test.io.in.valid <= UInt<1>("h00") - device_under_test.io.load_routing_table_request.bits.data <= UInt<1>("h00") - device_under_test.io.load_routing_table_request.bits.addr <= UInt<1>("h00") - device_under_test.io.load_routing_table_request.valid <= UInt<1>("h00") - device_under_test.io.read_routing_table_response.ready <= UInt<1>("h00") - device_under_test.io.read_routing_table_request.bits.addr <= UInt<1>("h00") - device_under_test.io.read_routing_table_request.valid <= UInt<1>("h00") - device_under_test.clk <= clk - device_under_test.reset <= reset - reg T_19 : UInt<8>, clk with : - reset => (reset, UInt<8>("h00")) - reg T_21 : UInt<1>, clk with : - reset => (reset, UInt<1>("h00")) - reg T_23 : UInt<8>, clk with : - reset => (reset, UInt<8>("h00")) - reg T_25 : UInt<1>, clk with : - reset => (reset, UInt<1>("h00")) - node T_26 = and(T_21, T_25) - when T_26 : - node T_28 = eq(reset, UInt<1>("h00")) - when T_28 : - printf(clk, UInt<1>(1), "All input and output events completed -") - skip - node T_30 = eq(reset, UInt<1>("h00")) - when T_30 : - stop(clk, UInt<1>(1), 0) - skip - skip - reg T_32 : UInt<10>, clk with : - reset => (reset, UInt<10>("h00")) - node T_34 = tail(add(T_32, UInt<1>("h01")),1) - T_32 <= T_34 - node T_36 = gt(T_32, UInt<10>("h03e8")) - when T_36 : - node T_39 = eq(reset, UInt<1>("h00")) - when T_39 : - printf(clk, UInt<1>(1), "Exceeded maximum allowed %d ticks in OrderedDecoupledHWIOTester, If you think code is correct use: -DecoupleTester.max_tick_count = <some-higher-value> -in the OrderedDecoupledHWIOTester subclass -", UInt<10>("h03e8")) - skip - node T_41 = eq(reset, UInt<1>("h00")) - when T_41 : - stop(clk, UInt<1>(1), 0) - skip - skip - wire T_97 : UInt<1>[54] - T_97[0] <= UInt<1>("h00") - T_97[1] <= UInt<1>("h00") - T_97[2] <= UInt<1>("h00") - T_97[3] <= UInt<1>("h00") - T_97[4] <= UInt<1>("h00") - T_97[5] <= UInt<1>("h00") - T_97[6] <= UInt<1>("h00") - T_97[7] <= UInt<1>("h00") - T_97[8] <= UInt<1>("h00") - T_97[9] <= UInt<1>("h00") - T_97[10] <= UInt<1>("h00") - T_97[11] <= UInt<1>("h00") - T_97[12] <= UInt<1>("h00") - T_97[13] <= UInt<1>("h01") - T_97[14] <= UInt<1>("h01") - T_97[15] <= UInt<1>("h01") - T_97[16] <= UInt<1>("h01") - T_97[17] <= UInt<1>("h00") - T_97[18] <= UInt<1>("h00") - T_97[19] <= UInt<1>("h00") - T_97[20] <= UInt<1>("h00") - T_97[21] <= UInt<1>("h00") - T_97[22] <= UInt<1>("h00") - T_97[23] <= UInt<1>("h00") - T_97[24] <= UInt<1>("h00") - T_97[25] <= UInt<1>("h00") - T_97[26] <= UInt<1>("h00") - T_97[27] <= UInt<1>("h00") - T_97[28] <= UInt<1>("h00") - T_97[29] <= UInt<1>("h00") - T_97[30] <= UInt<1>("h00") - T_97[31] <= UInt<1>("h00") - T_97[32] <= UInt<1>("h01") - T_97[33] <= UInt<1>("h01") - T_97[34] <= UInt<1>("h01") - T_97[35] <= UInt<1>("h01") - T_97[36] <= UInt<1>("h01") - T_97[37] <= UInt<1>("h01") - T_97[38] <= UInt<1>("h01") - T_97[39] <= UInt<1>("h01") - T_97[40] <= UInt<1>("h01") - T_97[41] <= UInt<1>("h01") - T_97[42] <= UInt<1>("h01") - T_97[43] <= UInt<1>("h01") - T_97[44] <= UInt<1>("h01") - T_97[45] <= UInt<1>("h01") - T_97[46] <= UInt<1>("h01") - T_97[47] <= UInt<1>("h01") - T_97[48] <= UInt<1>("h01") - T_97[49] <= UInt<1>("h01") - T_97[50] <= UInt<1>("h01") - T_97[51] <= UInt<1>("h01") - T_97[52] <= UInt<1>("h01") - T_97[53] <= UInt<1>("h00") - reg T_154 : UInt<5>, clk with : - reset => (reset, UInt<5>("h00")) - wire T_182 : UInt<4>[26] - T_182[0] <= UInt<1>("h00") - T_182[1] <= UInt<1>("h01") - T_182[2] <= UInt<2>("h02") - T_182[3] <= UInt<2>("h03") - T_182[4] <= UInt<1>("h00") - T_182[5] <= UInt<1>("h01") - T_182[6] <= UInt<2>("h02") - T_182[7] <= UInt<2>("h03") - T_182[8] <= UInt<3>("h04") - T_182[9] <= UInt<3>("h05") - T_182[10] <= UInt<3>("h06") - T_182[11] <= UInt<3>("h07") - T_182[12] <= UInt<4>("h08") - T_182[13] <= UInt<4>("h09") - T_182[14] <= UInt<4>("h0a") - T_182[15] <= UInt<4>("h0b") - T_182[16] <= UInt<4>("h0c") - T_182[17] <= UInt<4>("h0d") - T_182[18] <= UInt<4>("h0e") - T_182[19] <= UInt<1>("h00") - T_182[20] <= UInt<1>("h01") - T_182[21] <= UInt<2>("h02") - T_182[22] <= UInt<2>("h03") - T_182[23] <= UInt<3>("h04") - T_182[24] <= UInt<3>("h05") - T_182[25] <= UInt<1>("h00") - wire T_237 : UInt<31>[26] - T_237[0] <= UInt<1>("h00") - T_237[1] <= UInt<2>("h03") - T_237[2] <= UInt<3>("h06") - T_237[3] <= UInt<4>("h09") - T_237[4] <= UInt<31>("h07dcd07ac") - T_237[5] <= UInt<31>("h070890d84") - T_237[6] <= UInt<26>("h02f45883") - T_237[7] <= UInt<31>("h0787ada79") - T_237[8] <= UInt<29>("h016866878") - T_237[9] <= UInt<30>("h02331b107") - T_237[10] <= UInt<30>("h0280e4938") - T_237[11] <= UInt<29>("h0107fb3ac") - T_237[12] <= UInt<30>("h02f19d47b") - T_237[13] <= UInt<29>("h012c3d7cc") - T_237[14] <= UInt<31>("h05a432a9c") - T_237[15] <= UInt<26>("h02f9778f") - T_237[16] <= UInt<22>("h02d705a") - T_237[17] <= UInt<31>("h045fb9184") - T_237[18] <= UInt<25>("h012e47af") - T_237[19] <= UInt<31>("h07b744e21") - T_237[20] <= UInt<31>("h0480ebc3d") - T_237[21] <= UInt<28>("h0d5ff365") - T_237[22] <= UInt<30>("h0205e7973") - T_237[23] <= UInt<31>("h05004cbd2") - T_237[24] <= UInt<30>("h024988736") - T_237[25] <= UInt<1>("h00") - device_under_test.io.in.bits.header <= T_182[T_154] - device_under_test.io.in.bits.body <= T_237[T_154] - device_under_test.io.in.valid <= T_97[T_19] - node T_268 = and(device_under_test.io.in.valid, device_under_test.io.in.ready) - when T_268 : - node T_270 = eq(T_154, UInt<5>("h018")) - node T_272 = and(UInt<1>("h01"), T_270) - node T_275 = tail(add(T_154, UInt<1>("h01")),1) - node T_276 = mux(T_272, UInt<1>("h00"), T_275) - T_154 <= T_276 - node T_278 = eq(T_21, UInt<1>("h00")) - when T_278 : - node T_280 = eq(T_19, UInt<6>("h034")) - when T_280 : - T_21 <= UInt<1>("h01") - skip - node T_283 = tail(add(T_19, UInt<1>("h01")),1) - T_19 <= T_283 - skip - skip - wire T_339 : UInt<1>[54] - T_339[0] <= UInt<1>("h00") - T_339[1] <= UInt<1>("h01") - T_339[2] <= UInt<1>("h00") - T_339[3] <= UInt<1>("h01") - T_339[4] <= UInt<1>("h00") - T_339[5] <= UInt<1>("h01") - T_339[6] <= UInt<1>("h00") - T_339[7] <= UInt<1>("h01") - T_339[8] <= UInt<1>("h00") - T_339[9] <= UInt<1>("h00") - T_339[10] <= UInt<1>("h00") - T_339[11] <= UInt<1>("h00") - T_339[12] <= UInt<1>("h00") - T_339[13] <= UInt<1>("h00") - T_339[14] <= UInt<1>("h00") - T_339[15] <= UInt<1>("h00") - T_339[16] <= UInt<1>("h00") - T_339[17] <= UInt<1>("h01") - T_339[18] <= UInt<1>("h01") - T_339[19] <= UInt<1>("h01") - T_339[20] <= UInt<1>("h01") - T_339[21] <= UInt<1>("h01") - T_339[22] <= UInt<1>("h01") - T_339[23] <= UInt<1>("h01") - T_339[24] <= UInt<1>("h01") - T_339[25] <= UInt<1>("h01") - T_339[26] <= UInt<1>("h01") - T_339[27] <= UInt<1>("h01") - T_339[28] <= UInt<1>("h01") - T_339[29] <= UInt<1>("h01") - T_339[30] <= UInt<1>("h01") - T_339[31] <= UInt<1>("h01") - T_339[32] <= UInt<1>("h00") - T_339[33] <= UInt<1>("h00") - T_339[34] <= UInt<1>("h00") - T_339[35] <= UInt<1>("h00") - T_339[36] <= UInt<1>("h00") - T_339[37] <= UInt<1>("h00") - T_339[38] <= UInt<1>("h00") - T_339[39] <= UInt<1>("h00") - T_339[40] <= UInt<1>("h00") - T_339[41] <= UInt<1>("h00") - T_339[42] <= UInt<1>("h00") - T_339[43] <= UInt<1>("h00") - T_339[44] <= UInt<1>("h00") - T_339[45] <= UInt<1>("h00") - T_339[46] <= UInt<1>("h00") - T_339[47] <= UInt<1>("h00") - T_339[48] <= UInt<1>("h00") - T_339[49] <= UInt<1>("h00") - T_339[50] <= UInt<1>("h00") - T_339[51] <= UInt<1>("h00") - T_339[52] <= UInt<1>("h00") - T_339[53] <= UInt<1>("h00") - reg T_396 : UInt<5>, clk with : - reset => (reset, UInt<5>("h00")) - wire T_418 : UInt<2>[20] - T_418[0] <= UInt<1>("h01") - T_418[1] <= UInt<2>("h02") - T_418[2] <= UInt<2>("h03") - T_418[3] <= UInt<1>("h00") - T_418[4] <= UInt<2>("h02") - T_418[5] <= UInt<2>("h03") - T_418[6] <= UInt<1>("h00") - T_418[7] <= UInt<2>("h02") - T_418[8] <= UInt<2>("h02") - T_418[9] <= UInt<1>("h01") - T_418[10] <= UInt<2>("h02") - T_418[11] <= UInt<1>("h00") - T_418[12] <= UInt<2>("h02") - T_418[13] <= UInt<2>("h03") - T_418[14] <= UInt<1>("h01") - T_418[15] <= UInt<1>("h01") - T_418[16] <= UInt<1>("h01") - T_418[17] <= UInt<2>("h02") - T_418[18] <= UInt<2>("h03") - T_418[19] <= UInt<1>("h00") - wire T_461 : UInt<4>[20] - T_461[0] <= UInt<1>("h00") - T_461[1] <= UInt<1>("h01") - T_461[2] <= UInt<2>("h02") - T_461[3] <= UInt<2>("h03") - T_461[4] <= UInt<1>("h00") - T_461[5] <= UInt<1>("h01") - T_461[6] <= UInt<2>("h02") - T_461[7] <= UInt<2>("h03") - T_461[8] <= UInt<3>("h04") - T_461[9] <= UInt<3>("h05") - T_461[10] <= UInt<3>("h06") - T_461[11] <= UInt<3>("h07") - T_461[12] <= UInt<4>("h08") - T_461[13] <= UInt<4>("h09") - T_461[14] <= UInt<4>("h0a") - T_461[15] <= UInt<4>("h0b") - T_461[16] <= UInt<4>("h0c") - T_461[17] <= UInt<4>("h0d") - T_461[18] <= UInt<4>("h0e") - T_461[19] <= UInt<1>("h00") - device_under_test.io.load_routing_table_request.bits.data <= T_418[T_396] - device_under_test.io.load_routing_table_request.bits.addr <= T_461[T_396] - device_under_test.io.load_routing_table_request.valid <= T_339[T_19] - node T_486 = and(device_under_test.io.load_routing_table_request.valid, device_under_test.io.load_routing_table_request.ready) - when T_486 : - node T_488 = eq(T_396, UInt<5>("h012")) - node T_490 = and(UInt<1>("h01"), T_488) - node T_493 = tail(add(T_396, UInt<1>("h01")),1) - node T_494 = mux(T_490, UInt<1>("h00"), T_493) - T_396 <= T_494 - node T_496 = eq(T_21, UInt<1>("h00")) - when T_496 : - node T_498 = eq(T_19, UInt<6>("h034")) - when T_498 : - T_21 <= UInt<1>("h01") - skip - node T_501 = tail(add(T_19, UInt<1>("h01")),1) - T_19 <= T_501 - skip - skip - wire T_557 : UInt<1>[54] - T_557[0] <= UInt<1>("h01") - T_557[1] <= UInt<1>("h00") - T_557[2] <= UInt<1>("h01") - T_557[3] <= UInt<1>("h00") - T_557[4] <= UInt<1>("h01") - T_557[5] <= UInt<1>("h00") - T_557[6] <= UInt<1>("h01") - T_557[7] <= UInt<1>("h00") - T_557[8] <= UInt<1>("h01") - T_557[9] <= UInt<1>("h01") - T_557[10] <= UInt<1>("h01") - T_557[11] <= UInt<1>("h01") - T_557[12] <= UInt<1>("h01") - T_557[13] <= UInt<1>("h00") - T_557[14] <= UInt<1>("h00") - T_557[15] <= UInt<1>("h00") - T_557[16] <= UInt<1>("h00") - T_557[17] <= UInt<1>("h00") - T_557[18] <= UInt<1>("h00") - T_557[19] <= UInt<1>("h00") - T_557[20] <= UInt<1>("h00") - T_557[21] <= UInt<1>("h00") - T_557[22] <= UInt<1>("h00") - T_557[23] <= UInt<1>("h00") - T_557[24] <= UInt<1>("h00") - T_557[25] <= UInt<1>("h00") - T_557[26] <= UInt<1>("h00") - T_557[27] <= UInt<1>("h00") - T_557[28] <= UInt<1>("h00") - T_557[29] <= UInt<1>("h00") - T_557[30] <= UInt<1>("h00") - T_557[31] <= UInt<1>("h00") - T_557[32] <= UInt<1>("h00") - T_557[33] <= UInt<1>("h00") - T_557[34] <= UInt<1>("h00") - T_557[35] <= UInt<1>("h00") - T_557[36] <= UInt<1>("h00") - T_557[37] <= UInt<1>("h00") - T_557[38] <= UInt<1>("h00") - T_557[39] <= UInt<1>("h00") - T_557[40] <= UInt<1>("h00") - T_557[41] <= UInt<1>("h00") - T_557[42] <= UInt<1>("h00") - T_557[43] <= UInt<1>("h00") - T_557[44] <= UInt<1>("h00") - T_557[45] <= UInt<1>("h00") - T_557[46] <= UInt<1>("h00") - T_557[47] <= UInt<1>("h00") - T_557[48] <= UInt<1>("h00") - T_557[49] <= UInt<1>("h00") - T_557[50] <= UInt<1>("h00") - T_557[51] <= UInt<1>("h00") - T_557[52] <= UInt<1>("h00") - T_557[53] <= UInt<1>("h00") - reg T_614 : UInt<4>, clk with : - reset => (reset, UInt<4>("h00")) - wire T_626 : UInt<2>[10] - T_626[0] <= UInt<1>("h00") - T_626[1] <= UInt<1>("h00") - T_626[2] <= UInt<1>("h01") - T_626[3] <= UInt<2>("h02") - T_626[4] <= UInt<2>("h03") - T_626[5] <= UInt<2>("h03") - T_626[6] <= UInt<2>("h02") - T_626[7] <= UInt<1>("h01") - T_626[8] <= UInt<1>("h00") - T_626[9] <= UInt<1>("h00") - device_under_test.io.read_routing_table_request.bits.addr <= T_626[T_614] - device_under_test.io.read_routing_table_request.valid <= T_557[T_19] - node T_640 = and(device_under_test.io.read_routing_table_request.valid, device_under_test.io.read_routing_table_request.ready) - when T_640 : - node T_642 = eq(T_614, UInt<4>("h08")) - node T_644 = and(UInt<1>("h01"), T_642) - node T_647 = tail(add(T_614, UInt<1>("h01")),1) - node T_648 = mux(T_644, UInt<1>("h00"), T_647) - T_614 <= T_648 - node T_650 = eq(T_21, UInt<1>("h00")) - when T_650 : - node T_652 = eq(T_19, UInt<6>("h034")) - when T_652 : - T_21 <= UInt<1>("h01") - skip - node T_655 = tail(add(T_19, UInt<1>("h01")),1) - T_19 <= T_655 - skip - skip - wire T_711 : UInt<1>[54] - T_711[0] <= UInt<1>("h00") - T_711[1] <= UInt<1>("h00") - T_711[2] <= UInt<1>("h00") - T_711[3] <= UInt<1>("h00") - T_711[4] <= UInt<1>("h00") - T_711[5] <= UInt<1>("h00") - T_711[6] <= UInt<1>("h00") - T_711[7] <= UInt<1>("h00") - T_711[8] <= UInt<1>("h00") - T_711[9] <= UInt<1>("h00") - T_711[10] <= UInt<1>("h00") - T_711[11] <= UInt<1>("h00") - T_711[12] <= UInt<1>("h01") - T_711[13] <= UInt<1>("h00") - T_711[14] <= UInt<1>("h00") - T_711[15] <= UInt<1>("h01") - T_711[16] <= UInt<1>("h00") - T_711[17] <= UInt<1>("h00") - T_711[18] <= UInt<1>("h00") - T_711[19] <= UInt<1>("h00") - T_711[20] <= UInt<1>("h01") - T_711[21] <= UInt<1>("h00") - T_711[22] <= UInt<1>("h00") - T_711[23] <= UInt<1>("h00") - T_711[24] <= UInt<1>("h00") - T_711[25] <= UInt<1>("h00") - T_711[26] <= UInt<1>("h00") - T_711[27] <= UInt<1>("h00") - T_711[28] <= UInt<1>("h00") - T_711[29] <= UInt<1>("h00") - T_711[30] <= UInt<1>("h01") - T_711[31] <= UInt<1>("h00") - T_711[32] <= UInt<1>("h00") - T_711[33] <= UInt<1>("h00") - T_711[34] <= UInt<1>("h00") - T_711[35] <= UInt<1>("h00") - T_711[36] <= UInt<1>("h00") - T_711[37] <= UInt<1>("h00") - T_711[38] <= UInt<1>("h00") - T_711[39] <= UInt<1>("h00") - T_711[40] <= UInt<1>("h00") - T_711[41] <= UInt<1>("h00") - T_711[42] <= UInt<1>("h00") - T_711[43] <= UInt<1>("h00") - T_711[44] <= UInt<1>("h00") - T_711[45] <= UInt<1>("h00") - T_711[46] <= UInt<1>("h00") - T_711[47] <= UInt<1>("h00") - T_711[48] <= UInt<1>("h00") - T_711[49] <= UInt<1>("h00") - T_711[50] <= UInt<1>("h00") - T_711[51] <= UInt<1>("h00") - T_711[52] <= UInt<1>("h00") - T_711[53] <= UInt<1>("h00") - reg T_768 : UInt<6>, clk with : - reset => (reset, UInt<6>("h00")) - wire T_775 : UInt<29>[5] - T_775[0] <= UInt<4>("h09") - T_775[1] <= UInt<26>("h02f45883") - T_775[2] <= UInt<29>("h0107fb3ac") - T_775[3] <= UInt<28>("h0d5ff365") - T_775[4] <= UInt<1>("h00") - device_under_test.io.outs[0].ready <= T_711[T_23] - node T_783 = and(device_under_test.io.outs[0].ready, device_under_test.io.outs[0].valid) - when T_783 : - node T_786 = eq(reset, UInt<1>("h00")) - when T_786 : - printf(clk, UInt<1>(1), "output test event %d testing outs(0).bits.body = %d, should be %d -", T_23, device_under_test.io.outs[0].bits.body, T_775[T_768]) - skip - node T_788 = neq(device_under_test.io.outs[0].bits.body, T_775[T_768]) - when T_788 : - node T_791 = eq(reset, UInt<1>("h00")) - when T_791 : - printf(clk, UInt<1>(1), "Error: event %d outs(0).bits.body was %d should be %d -", T_23, device_under_test.io.outs[0].bits.body, T_775[T_768]) - skip - node T_794 = eq(reset, UInt<1>("h00")) - when T_794 : - node T_796 = eq(UInt<1>("h00"), UInt<1>("h00")) - when T_796 : - node T_798 = eq(reset, UInt<1>("h00")) - when T_798 : - printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno)") - skip - stop(clk, UInt<1>(1), 1) - skip - skip - node T_800 = eq(reset, UInt<1>("h00")) - when T_800 : - stop(clk, UInt<1>(1), 0) - skip - skip - node T_802 = eq(T_768, UInt<6>("h021")) - node T_804 = and(UInt<1>("h01"), T_802) - node T_807 = tail(add(T_768, UInt<1>("h01")),1) - node T_808 = mux(T_804, UInt<1>("h00"), T_807) - T_768 <= T_808 - node T_810 = eq(T_25, UInt<1>("h00")) - when T_810 : - node T_812 = eq(T_23, UInt<6>("h021")) - when T_812 : - T_25 <= UInt<1>("h01") - skip - node T_815 = tail(add(T_23, UInt<1>("h01")),1) - T_23 <= T_815 - skip - skip - wire T_871 : UInt<1>[54] - T_871[0] <= UInt<1>("h00") - T_871[1] <= UInt<1>("h00") - T_871[2] <= UInt<1>("h00") - T_871[3] <= UInt<1>("h00") - T_871[4] <= UInt<1>("h00") - T_871[5] <= UInt<1>("h00") - T_871[6] <= UInt<1>("h00") - T_871[7] <= UInt<1>("h00") - T_871[8] <= UInt<1>("h00") - T_871[9] <= UInt<1>("h00") - T_871[10] <= UInt<1>("h00") - T_871[11] <= UInt<1>("h01") - T_871[12] <= UInt<1>("h00") - T_871[13] <= UInt<1>("h00") - T_871[14] <= UInt<1>("h01") - T_871[15] <= UInt<1>("h00") - T_871[16] <= UInt<1>("h00") - T_871[17] <= UInt<1>("h00") - T_871[18] <= UInt<1>("h00") - T_871[19] <= UInt<1>("h00") - T_871[20] <= UInt<1>("h00") - T_871[21] <= UInt<1>("h00") - T_871[22] <= UInt<1>("h01") - T_871[23] <= UInt<1>("h00") - T_871[24] <= UInt<1>("h00") - T_871[25] <= UInt<1>("h00") - T_871[26] <= UInt<1>("h00") - T_871[27] <= UInt<1>("h01") - T_871[28] <= UInt<1>("h00") - T_871[29] <= UInt<1>("h01") - T_871[30] <= UInt<1>("h00") - T_871[31] <= UInt<1>("h00") - T_871[32] <= UInt<1>("h00") - T_871[33] <= UInt<1>("h00") - T_871[34] <= UInt<1>("h00") - T_871[35] <= UInt<1>("h00") - T_871[36] <= UInt<1>("h00") - T_871[37] <= UInt<1>("h00") - T_871[38] <= UInt<1>("h00") - T_871[39] <= UInt<1>("h00") - T_871[40] <= UInt<1>("h00") - T_871[41] <= UInt<1>("h00") - T_871[42] <= UInt<1>("h00") - T_871[43] <= UInt<1>("h00") - T_871[44] <= UInt<1>("h00") - T_871[45] <= UInt<1>("h00") - T_871[46] <= UInt<1>("h00") - T_871[47] <= UInt<1>("h00") - T_871[48] <= UInt<1>("h00") - T_871[49] <= UInt<1>("h00") - T_871[50] <= UInt<1>("h00") - T_871[51] <= UInt<1>("h00") - T_871[52] <= UInt<1>("h00") - T_871[53] <= UInt<1>("h00") - reg T_928 : UInt<6>, clk with : - reset => (reset, UInt<6>("h00")) - wire T_936 : UInt<31>[6] - T_936[0] <= UInt<3>("h06") - T_936[1] <= UInt<31>("h070890d84") - T_936[2] <= UInt<29>("h012c3d7cc") - T_936[3] <= UInt<25>("h012e47af") - T_936[4] <= UInt<31>("h0480ebc3d") - T_936[5] <= UInt<1>("h00") - device_under_test.io.outs[3].ready <= T_871[T_23] - node T_945 = and(device_under_test.io.outs[3].ready, device_under_test.io.outs[3].valid) - when T_945 : - node T_948 = eq(reset, UInt<1>("h00")) - when T_948 : - printf(clk, UInt<1>(1), "output test event %d testing outs(3).bits.body = %d, should be %d -", T_23, device_under_test.io.outs[3].bits.body, T_936[T_928]) - skip - node T_950 = neq(device_under_test.io.outs[3].bits.body, T_936[T_928]) - when T_950 : - node T_953 = eq(reset, UInt<1>("h00")) - when T_953 : - printf(clk, UInt<1>(1), "Error: event %d outs(3).bits.body was %d should be %d -", T_23, device_under_test.io.outs[3].bits.body, T_936[T_928]) - skip - node T_956 = eq(reset, UInt<1>("h00")) - when T_956 : - node T_958 = eq(UInt<1>("h00"), UInt<1>("h00")) - when T_958 : - node T_960 = eq(reset, UInt<1>("h00")) - when T_960 : - printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno)") - skip - stop(clk, UInt<1>(1), 1) - skip - skip - node T_962 = eq(reset, UInt<1>("h00")) - when T_962 : - stop(clk, UInt<1>(1), 0) - skip - skip - node T_964 = eq(T_928, UInt<6>("h021")) - node T_966 = and(UInt<1>("h01"), T_964) - node T_969 = tail(add(T_928, UInt<1>("h01")),1) - node T_970 = mux(T_966, UInt<1>("h00"), T_969) - T_928 <= T_970 - node T_972 = eq(T_25, UInt<1>("h00")) - when T_972 : - node T_974 = eq(T_23, UInt<6>("h021")) - when T_974 : - T_25 <= UInt<1>("h01") - skip - node T_977 = tail(add(T_23, UInt<1>("h01")),1) - T_23 <= T_977 - skip - skip - wire T_1033 : UInt<1>[54] - T_1033[0] <= UInt<1>("h00") - T_1033[1] <= UInt<1>("h00") - T_1033[2] <= UInt<1>("h00") - T_1033[3] <= UInt<1>("h00") - T_1033[4] <= UInt<1>("h00") - T_1033[5] <= UInt<1>("h00") - T_1033[6] <= UInt<1>("h00") - T_1033[7] <= UInt<1>("h00") - T_1033[8] <= UInt<1>("h00") - T_1033[9] <= UInt<1>("h01") - T_1033[10] <= UInt<1>("h00") - T_1033[11] <= UInt<1>("h00") - T_1033[12] <= UInt<1>("h00") - T_1033[13] <= UInt<1>("h00") - T_1033[14] <= UInt<1>("h00") - T_1033[15] <= UInt<1>("h00") - T_1033[16] <= UInt<1>("h00") - T_1033[17] <= UInt<1>("h00") - T_1033[18] <= UInt<1>("h01") - T_1033[19] <= UInt<1>("h00") - T_1033[20] <= UInt<1>("h00") - T_1033[21] <= UInt<1>("h00") - T_1033[22] <= UInt<1>("h00") - T_1033[23] <= UInt<1>("h01") - T_1033[24] <= UInt<1>("h01") - T_1033[25] <= UInt<1>("h01") - T_1033[26] <= UInt<1>("h00") - T_1033[27] <= UInt<1>("h00") - T_1033[28] <= UInt<1>("h00") - T_1033[29] <= UInt<1>("h00") - T_1033[30] <= UInt<1>("h00") - T_1033[31] <= UInt<1>("h00") - T_1033[32] <= UInt<1>("h00") - T_1033[33] <= UInt<1>("h01") - T_1033[34] <= UInt<1>("h00") - T_1033[35] <= UInt<1>("h00") - T_1033[36] <= UInt<1>("h00") - T_1033[37] <= UInt<1>("h00") - T_1033[38] <= UInt<1>("h00") - T_1033[39] <= UInt<1>("h00") - T_1033[40] <= UInt<1>("h00") - T_1033[41] <= UInt<1>("h00") - T_1033[42] <= UInt<1>("h00") - T_1033[43] <= UInt<1>("h00") - T_1033[44] <= UInt<1>("h00") - T_1033[45] <= UInt<1>("h00") - T_1033[46] <= UInt<1>("h00") - T_1033[47] <= UInt<1>("h00") - T_1033[48] <= UInt<1>("h00") - T_1033[49] <= UInt<1>("h00") - T_1033[50] <= UInt<1>("h00") - T_1033[51] <= UInt<1>("h00") - T_1033[52] <= UInt<1>("h00") - T_1033[53] <= UInt<1>("h00") - reg T_1090 : UInt<6>, clk with : - reset => (reset, UInt<6>("h00")) - wire T_1099 : UInt<31>[7] - T_1099[0] <= UInt<1>("h00") - T_1099[1] <= UInt<30>("h02331b107") - T_1099[2] <= UInt<31>("h05a432a9c") - T_1099[3] <= UInt<26>("h02f9778f") - T_1099[4] <= UInt<22>("h02d705a") - T_1099[5] <= UInt<30>("h024988736") - T_1099[6] <= UInt<1>("h00") - device_under_test.io.outs[1].ready <= T_1033[T_23] - node T_1109 = and(device_under_test.io.outs[1].ready, device_under_test.io.outs[1].valid) - when T_1109 : - node T_1112 = eq(reset, UInt<1>("h00")) - when T_1112 : - printf(clk, UInt<1>(1), "output test event %d testing outs(1).bits.body = %d, should be %d -", T_23, device_under_test.io.outs[1].bits.body, T_1099[T_1090]) - skip - node T_1114 = neq(device_under_test.io.outs[1].bits.body, T_1099[T_1090]) - when T_1114 : - node T_1117 = eq(reset, UInt<1>("h00")) - when T_1117 : - printf(clk, UInt<1>(1), "Error: event %d outs(1).bits.body was %d should be %d -", T_23, device_under_test.io.outs[1].bits.body, T_1099[T_1090]) - skip - node T_1120 = eq(reset, UInt<1>("h00")) - when T_1120 : - node T_1122 = eq(UInt<1>("h00"), UInt<1>("h00")) - when T_1122 : - node T_1124 = eq(reset, UInt<1>("h00")) - when T_1124 : - printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno)") - skip - stop(clk, UInt<1>(1), 1) - skip - skip - node T_1126 = eq(reset, UInt<1>("h00")) - when T_1126 : - stop(clk, UInt<1>(1), 0) - skip - skip - node T_1128 = eq(T_1090, UInt<6>("h021")) - node T_1130 = and(UInt<1>("h01"), T_1128) - node T_1133 = tail(add(T_1090, UInt<1>("h01")),1) - node T_1134 = mux(T_1130, UInt<1>("h00"), T_1133) - T_1090 <= T_1134 - node T_1136 = eq(T_25, UInt<1>("h00")) - when T_1136 : - node T_1138 = eq(T_23, UInt<6>("h021")) - when T_1138 : - T_25 <= UInt<1>("h01") - skip - node T_1141 = tail(add(T_23, UInt<1>("h01")),1) - T_23 <= T_1141 - skip - skip - wire T_1197 : UInt<1>[54] - T_1197[0] <= UInt<1>("h00") - T_1197[1] <= UInt<1>("h00") - T_1197[2] <= UInt<1>("h00") - T_1197[3] <= UInt<1>("h00") - T_1197[4] <= UInt<1>("h00") - T_1197[5] <= UInt<1>("h00") - T_1197[6] <= UInt<1>("h00") - T_1197[7] <= UInt<1>("h00") - T_1197[8] <= UInt<1>("h00") - T_1197[9] <= UInt<1>("h00") - T_1197[10] <= UInt<1>("h01") - T_1197[11] <= UInt<1>("h00") - T_1197[12] <= UInt<1>("h00") - T_1197[13] <= UInt<1>("h01") - T_1197[14] <= UInt<1>("h00") - T_1197[15] <= UInt<1>("h00") - T_1197[16] <= UInt<1>("h01") - T_1197[17] <= UInt<1>("h01") - T_1197[18] <= UInt<1>("h00") - T_1197[19] <= UInt<1>("h01") - T_1197[20] <= UInt<1>("h00") - T_1197[21] <= UInt<1>("h01") - T_1197[22] <= UInt<1>("h00") - T_1197[23] <= UInt<1>("h00") - T_1197[24] <= UInt<1>("h00") - T_1197[25] <= UInt<1>("h00") - T_1197[26] <= UInt<1>("h01") - T_1197[27] <= UInt<1>("h00") - T_1197[28] <= UInt<1>("h01") - T_1197[29] <= UInt<1>("h00") - T_1197[30] <= UInt<1>("h00") - T_1197[31] <= UInt<1>("h01") - T_1197[32] <= UInt<1>("h01") - T_1197[33] <= UInt<1>("h00") - T_1197[34] <= UInt<1>("h00") - T_1197[35] <= UInt<1>("h00") - T_1197[36] <= UInt<1>("h00") - T_1197[37] <= UInt<1>("h00") - T_1197[38] <= UInt<1>("h00") - T_1197[39] <= UInt<1>("h00") - T_1197[40] <= UInt<1>("h00") - T_1197[41] <= UInt<1>("h00") - T_1197[42] <= UInt<1>("h00") - T_1197[43] <= UInt<1>("h00") - T_1197[44] <= UInt<1>("h00") - T_1197[45] <= UInt<1>("h00") - T_1197[46] <= UInt<1>("h00") - T_1197[47] <= UInt<1>("h00") - T_1197[48] <= UInt<1>("h00") - T_1197[49] <= UInt<1>("h00") - T_1197[50] <= UInt<1>("h00") - T_1197[51] <= UInt<1>("h00") - T_1197[52] <= UInt<1>("h00") - T_1197[53] <= UInt<1>("h00") - reg T_1254 : UInt<6>, clk with : - reset => (reset, UInt<6>("h00")) - wire T_1267 : UInt<31>[11] - T_1267[0] <= UInt<2>("h03") - T_1267[1] <= UInt<31>("h07dcd07ac") - T_1267[2] <= UInt<31>("h0787ada79") - T_1267[3] <= UInt<29>("h016866878") - T_1267[4] <= UInt<30>("h0280e4938") - T_1267[5] <= UInt<30>("h02f19d47b") - T_1267[6] <= UInt<31>("h045fb9184") - T_1267[7] <= UInt<31>("h07b744e21") - T_1267[8] <= UInt<30>("h0205e7973") - T_1267[9] <= UInt<31>("h05004cbd2") - T_1267[10] <= UInt<1>("h00") - device_under_test.io.outs[2].ready <= T_1197[T_23] - node T_1281 = and(device_under_test.io.outs[2].ready, device_under_test.io.outs[2].valid) - when T_1281 : - node T_1284 = eq(reset, UInt<1>("h00")) - when T_1284 : - printf(clk, UInt<1>(1), "output test event %d testing outs(2).bits.body = %d, should be %d -", T_23, device_under_test.io.outs[2].bits.body, T_1267[T_1254]) - skip - node T_1286 = neq(device_under_test.io.outs[2].bits.body, T_1267[T_1254]) - when T_1286 : - node T_1289 = eq(reset, UInt<1>("h00")) - when T_1289 : - printf(clk, UInt<1>(1), "Error: event %d outs(2).bits.body was %d should be %d -", T_23, device_under_test.io.outs[2].bits.body, T_1267[T_1254]) - skip - node T_1292 = eq(reset, UInt<1>("h00")) - when T_1292 : - node T_1294 = eq(UInt<1>("h00"), UInt<1>("h00")) - when T_1294 : - node T_1296 = eq(reset, UInt<1>("h00")) - when T_1296 : - printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno)") - skip - stop(clk, UInt<1>(1), 1) - skip - skip - node T_1298 = eq(reset, UInt<1>("h00")) - when T_1298 : - stop(clk, UInt<1>(1), 0) - skip - skip - node T_1300 = eq(T_1254, UInt<6>("h021")) - node T_1302 = and(UInt<1>("h01"), T_1300) - node T_1305 = tail(add(T_1254, UInt<1>("h01")),1) - node T_1306 = mux(T_1302, UInt<1>("h00"), T_1305) - T_1254 <= T_1306 - node T_1308 = eq(T_25, UInt<1>("h00")) - when T_1308 : - node T_1310 = eq(T_23, UInt<6>("h021")) - when T_1310 : - T_25 <= UInt<1>("h01") - skip - node T_1313 = tail(add(T_23, UInt<1>("h01")),1) - T_23 <= T_1313 - skip - skip - wire T_1369 : UInt<1>[54] - T_1369[0] <= UInt<1>("h01") - T_1369[1] <= UInt<1>("h01") - T_1369[2] <= UInt<1>("h01") - T_1369[3] <= UInt<1>("h01") - T_1369[4] <= UInt<1>("h01") - T_1369[5] <= UInt<1>("h01") - T_1369[6] <= UInt<1>("h01") - T_1369[7] <= UInt<1>("h01") - T_1369[8] <= UInt<1>("h01") - T_1369[9] <= UInt<1>("h00") - T_1369[10] <= UInt<1>("h00") - T_1369[11] <= UInt<1>("h00") - T_1369[12] <= UInt<1>("h00") - T_1369[13] <= UInt<1>("h00") - T_1369[14] <= UInt<1>("h00") - T_1369[15] <= UInt<1>("h00") - T_1369[16] <= UInt<1>("h00") - T_1369[17] <= UInt<1>("h00") - T_1369[18] <= UInt<1>("h00") - T_1369[19] <= UInt<1>("h00") - T_1369[20] <= UInt<1>("h00") - T_1369[21] <= UInt<1>("h00") - T_1369[22] <= UInt<1>("h00") - T_1369[23] <= UInt<1>("h00") - T_1369[24] <= UInt<1>("h00") - T_1369[25] <= UInt<1>("h00") - T_1369[26] <= UInt<1>("h00") - T_1369[27] <= UInt<1>("h00") - T_1369[28] <= UInt<1>("h00") - T_1369[29] <= UInt<1>("h00") - T_1369[30] <= UInt<1>("h00") - T_1369[31] <= UInt<1>("h00") - T_1369[32] <= UInt<1>("h00") - T_1369[33] <= UInt<1>("h00") - T_1369[34] <= UInt<1>("h00") - T_1369[35] <= UInt<1>("h00") - T_1369[36] <= UInt<1>("h00") - T_1369[37] <= UInt<1>("h00") - T_1369[38] <= UInt<1>("h00") - T_1369[39] <= UInt<1>("h00") - T_1369[40] <= UInt<1>("h00") - T_1369[41] <= UInt<1>("h00") - T_1369[42] <= UInt<1>("h00") - T_1369[43] <= UInt<1>("h00") - T_1369[44] <= UInt<1>("h00") - T_1369[45] <= UInt<1>("h00") - T_1369[46] <= UInt<1>("h00") - T_1369[47] <= UInt<1>("h00") - T_1369[48] <= UInt<1>("h00") - T_1369[49] <= UInt<1>("h00") - T_1369[50] <= UInt<1>("h00") - T_1369[51] <= UInt<1>("h00") - T_1369[52] <= UInt<1>("h00") - T_1369[53] <= UInt<1>("h00") - reg T_1426 : UInt<6>, clk with : - reset => (reset, UInt<6>("h00")) - wire T_1438 : UInt<2>[10] - T_1438[0] <= UInt<1>("h00") - T_1438[1] <= UInt<1>("h01") - T_1438[2] <= UInt<2>("h02") - T_1438[3] <= UInt<2>("h03") - T_1438[4] <= UInt<1>("h00") - T_1438[5] <= UInt<1>("h00") - T_1438[6] <= UInt<2>("h03") - T_1438[7] <= UInt<2>("h02") - T_1438[8] <= UInt<1>("h01") - T_1438[9] <= UInt<1>("h00") - device_under_test.io.read_routing_table_response.ready <= T_1369[T_23] - node T_1451 = and(device_under_test.io.read_routing_table_response.ready, device_under_test.io.read_routing_table_response.valid) - when T_1451 : - node T_1454 = eq(reset, UInt<1>("h00")) - when T_1454 : - printf(clk, UInt<1>(1), "output test event %d testing read_routing_table_response.bits = %d, should be %d -", T_23, device_under_test.io.read_routing_table_response.bits, T_1438[T_1426]) - skip - node T_1456 = neq(device_under_test.io.read_routing_table_response.bits, T_1438[T_1426]) - when T_1456 : - node T_1459 = eq(reset, UInt<1>("h00")) - when T_1459 : - printf(clk, UInt<1>(1), "Error: event %d read_routing_table_response.bits was %d should be %d -", T_23, device_under_test.io.read_routing_table_response.bits, T_1438[T_1426]) - skip - node T_1462 = eq(reset, UInt<1>("h00")) - when T_1462 : - node T_1464 = eq(UInt<1>("h00"), UInt<1>("h00")) - when T_1464 : - node T_1466 = eq(reset, UInt<1>("h00")) - when T_1466 : - printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno)") - skip - stop(clk, UInt<1>(1), 1) - skip - skip - node T_1468 = eq(reset, UInt<1>("h00")) - when T_1468 : - stop(clk, UInt<1>(1), 0) - skip - skip - node T_1470 = eq(T_1426, UInt<6>("h021")) - node T_1472 = and(UInt<1>("h01"), T_1470) - node T_1475 = tail(add(T_1426, UInt<1>("h01")),1) - node T_1476 = mux(T_1472, UInt<1>("h00"), T_1475) - T_1426 <= T_1476 - node T_1478 = eq(T_25, UInt<1>("h00")) - when T_1478 : - node T_1480 = eq(T_23, UInt<6>("h021")) - when T_1480 : - T_25 <= UInt<1>("h01") - skip - node T_1483 = tail(add(T_23, UInt<1>("h01")),1) - T_23 <= T_1483 - skip - skip - node T_1485 = eq(reset, UInt<1>("h00")) - when T_1485 : - printf(clk, UInt<1>(1), "in_event_counter %d, out_event_counter %d -", T_19, T_23) - skip - - - diff --git a/test/passes/jacktest/Stack.fir b/test/passes/jacktest/Stack.fir deleted file mode 100644 index 3eb9c67c..00000000 --- a/test/passes/jacktest/Stack.fir +++ /dev/null @@ -1,37 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p cT 2>&1 | tee %s.out | FileCheck %s -;CHECK: Done! -circuit Stack : - module Stack : - input push : UInt<1> - input pop : UInt<1> - input en : UInt<1> - input clk : Clock - input reset : UInt<1> - output dataOut : UInt<32> - input dataIn : UInt<32> - - cmem stack_mem : UInt<32>[16] - reg sp : UInt<5>,clk with : - reset => (reset,UInt<5>(0)) - reg out : UInt<32>,clk with : - reset => (reset,UInt<32>(0)) - when en : - node T_30 = lt(sp, UInt<5>(16)) - node T_31 = and(push, T_30) - when T_31 : - write mport T_32 = stack_mem[sp],clk - T_32 <= dataIn - node T_33 = tail(add(sp, UInt<1>(1)),1) - sp <= T_33 - else : - node T_34 = gt(sp, UInt<1>(0)) - node T_35 = and(pop, T_34) - when T_35 : - node T_36 = tail(sub(sp, UInt<1>(1)),1) - sp <= T_36 - node T_37 = gt(sp, UInt<1>(0)) - when T_37 : - node T_38 = tail(sub(sp, UInt<1>(1)),1) - read mport T_39 = stack_mem[T_38],clk - out <= T_39 - dataOut <= out diff --git a/test/passes/jacktest/Tbl.fir b/test/passes/jacktest/Tbl.fir deleted file mode 100644 index 5feb71bb..00000000 --- a/test/passes/jacktest/Tbl.fir +++ /dev/null @@ -1,21 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: Done! - -circuit Tbl : - module Tbl : - input clk : Clock - input reset : UInt<1> - output io : {flip wi : UInt<3>, flip ri : UInt<3>, flip we : UInt<1>, flip d : UInt<3>, o : UInt<3>} - - io.o <= UInt<1>("h00") - cmem m : UInt<3>[8] - infer mport T_12 = m[io.ri], clk - io.o <= T_12 - when io.we : - infer mport T_13 = m[io.wi], clk - T_13 <= io.d - node T_14 = eq(io.ri, io.wi) - when T_14 : - io.o <= io.d - skip - skip diff --git a/test/passes/jacktest/VendingMachine.fir b/test/passes/jacktest/VendingMachine.fir deleted file mode 100644 index d7822a17..00000000 --- a/test/passes/jacktest/VendingMachine.fir +++ /dev/null @@ -1,32 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: Done! -circuit VendingMachine : - module VendingMachine : - output valid : UInt<1> - input nickel : UInt<1> - input dime : UInt<1> - input clk : Clock - input reset : UInt<1> - - reg state : UInt<3>,clk with : - reset => (reset,UInt<3>(0)) - node T_22 = eq(state, UInt<3>(0)) - when T_22 : - when nickel : state <= UInt<3>(1) - when dime : state <= UInt<3>(2) - node T_23 = eq(state, UInt<3>(1)) - when T_23 : - when nickel : state <= UInt<3>(2) - when dime : state <= UInt<3>(3) - node T_24 = eq(state, UInt<3>(2)) - when T_24 : - when nickel : state <= UInt<3>(3) - when dime : state <= UInt<3>(4) - node T_25 = eq(state, UInt<3>(3)) - when T_25 : - when nickel : state <= UInt<3>(4) - when dime : state <= UInt<3>(4) - node T_26 = eq(state, UInt<3>(4)) - when T_26 : state <= UInt<3>(0) - node T_27 = eq(state, UInt<3>(4)) - valid <= T_27 diff --git a/test/passes/jacktest/gcd.fir b/test/passes/jacktest/gcd.fir deleted file mode 100644 index 31ca30b2..00000000 --- a/test/passes/jacktest/gcd.fir +++ /dev/null @@ -1,29 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: Done! -circuit GCD : - module GCD : - input e : UInt<1> - input clk : Clock - input reset : UInt<1> - output z : UInt<16> - output v : UInt<1> - input a : UInt<16> - input b : UInt<16> - - reg x : UInt<16>,clk with : - reset => (reset,x) - reg y : UInt<16>,clk with : - reset => (reset,y) - node T_17 = gt(x, y) - when T_17 : - node T_18 = tail(sub(x, y),1) - x <= T_18 - else : - node T_19 = tail(sub(y, x),1) - y <= T_19 - when e : - x <= a - y <= b - z <= x - node T_20 = eq(y, UInt<1>(0)) - v <= T_20 diff --git a/test/passes/jacktest/risc.fir b/test/passes/jacktest/risc.fir deleted file mode 100644 index f722cf97..00000000 --- a/test/passes/jacktest/risc.fir +++ /dev/null @@ -1,54 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p cT 2>&1 | tee %s.out | FileCheck %s -; CHECK: Done! -circuit Risc : - module Risc : - output out : UInt<32> - output valid : UInt<1> - input boot : UInt<1> - input isWr : UInt<1> - input wrAddr : UInt<8> - input wrData : UInt<32> - input clk : Clock - input reset : UInt<1> - - cmem file : UInt<32>[256] - cmem code : UInt<32>[256] - reg pc : UInt<8>,clk with : - reset => (reset,UInt<8>(0)) - read mport inst = code[pc],clk - node op = bits(inst, 31, 24) - node rci = bits(inst, 23, 16) - node rai = bits(inst, 15, 8) - node rbi = bits(inst, 7, 0) - node T_51 = eq(rai, UInt<1>(0)) - read mport T_52 = file[rai],clk - node ra = mux(T_51, UInt<1>(0), T_52) - node T_53 = eq(rbi, UInt<1>(0)) - read mport T_54 = file[rbi],clk - node rb = mux(T_53, UInt<1>(0), T_54) - wire rc : UInt<32> - valid <= UInt<1>(0) - out <= UInt<1>(0) - rc <= UInt<1>(0) - when isWr : - write mport T_55 = code[wrAddr],clk - T_55 <= wrData - else : when boot : pc <= UInt<1>(0) - else : - node T_56 = eq(UInt<1>(0), op) - when T_56 : - node T_57 = tail(add(ra, rb),1) - rc <= T_57 - node T_58 = eq(UInt<1>(1), op) - when T_58 : - node T_59 = shl(rai, 8) - node T_60 = or(T_59, rbi) - rc <= T_60 - out <= rc - node T_61 = eq(rci, UInt<8>(255)) - when T_61 : valid <= UInt<1>(1) - else : - write mport T_62 = file[rci],clk - T_62 <= rc - node T_63 = tail(add(pc, UInt<1>(1)),1) - pc <= T_63 diff --git a/test/passes/lower-to-ground/bundle-vecs.fir b/test/passes/lower-to-ground/bundle-vecs.fir deleted file mode 100644 index d6af7a82..00000000 --- a/test/passes/lower-to-ground/bundle-vecs.fir +++ /dev/null @@ -1,38 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s - -; CHECK: Lower Types -circuit top : - module top : - input i : UInt<1> - wire j : { x : UInt<32>, flip y : UInt<32> } - - wire a : { x : UInt<32>, flip y : UInt<32> }[2] - ; CHECK: wire a{{[_$]+}}0{{[_$]+}}x : UInt<32> - ; CHECK: wire a{{[_$]+}}0{{[_$]+}}y : UInt<32> - ; CHECK: wire a{{[_$]+}}1{{[_$]+}}x : UInt<32> - ; CHECK: wire a{{[_$]+}}1{{[_$]+}}y : UInt<32> - a[0].x <= UInt(0) - a[0].y <= UInt(0) - a[1].x <= UInt(0) - a[1].y <= UInt(0) - - j <= a[i] - a[i] <= j - -; CHECK: wire GEN_0 : UInt<32> -; CHECK: wire GEN_1 : UInt<32> -; CHECK: wire GEN_2 : UInt<32> -; CHECK: wire GEN_3 : UInt<32> -; CHECK: j_x <= GEN_0 -; CHECK: j_y <= GEN_3 -; CHECK: a_0_x <= mux(eq(UInt<1>("h0"), i), GEN_2, UInt<1>("h0")) -; CHECK: a_0_y <= mux(eq(UInt<1>("h0"), i), GEN_1, UInt<1>("h0")) -; CHECK: a_1_x <= mux(eq(UInt<1>("h1"), i), GEN_2, UInt<1>("h0")) -; CHECK: a_1_y <= mux(eq(UInt<1>("h1"), i), GEN_1, UInt<1>("h0")) -; CHECK: GEN_0 <= mux(eq(UInt<1>("h1"), i), a_1_x, a_0_x) -; CHECK: GEN_1 <= j_y -; CHECK: GEN_2 <= j_x -; CHECK: GEN_3 <= mux(eq(UInt<1>("h1"), i), a_1_y, a_0_y) - -; CHECK: Finished Lower Types - diff --git a/test/passes/lower-to-ground/bundle.fir b/test/passes/lower-to-ground/bundle.fir deleted file mode 100644 index a8f8ad78..00000000 --- a/test/passes/lower-to-ground/bundle.fir +++ /dev/null @@ -1,60 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p cd 2>&1 | tee %s.out | FileCheck %s - -circuit top : - module m : - input a : { x : UInt<5>, flip y: SInt<5>} - output b : { x : UInt<5>, flip y: SInt<5>} - a.y <= SInt(0) - b.x <= UInt(0) - module top : - input c : { x : UInt<5>[5], flip y : { x : UInt<5>[3], flip y : SInt<5> } } - wire a : { x : UInt<5>, flip y : SInt<5>} - wire b : { x : UInt<5>, flip y : SInt<5>} - a <= b - inst i of m - i.a <= a - b <= i.b - wire d : UInt<5>[5] - d[0] <= UInt(0) - d[1] <= UInt(0) - d[2] <= UInt(0) - d[3] <= UInt(0) - d[4] <= UInt(0) - c.y.x[0] <= UInt(0) - c.y.x[1] <= UInt(0) - c.y.x[2] <= UInt(0) - -;CHECK: Lower Types -;CHECK: circuit top : -;CHECK: module m : -;CHECK: input a{{[_$]+}}x : UInt<5> -;CHECK: output a{{[_$]+}}y : SInt<5> -;CHECK: output b{{[_$]+}}x : UInt<5> -;CHECK: input b{{[_$]+}}y : SInt<5> -;CHECK: module top : -;CHECK: input c{{[_$]+}}x{{[_$]+}}0 : UInt<5> -;CHECK: input c{{[_$]+}}x{{[_$]+}}1 : UInt<5> -;CHECK: input c{{[_$]+}}x{{[_$]+}}2 : UInt<5> -;CHECK: input c{{[_$]+}}x{{[_$]+}}3 : UInt<5> -;CHECK: input c{{[_$]+}}x{{[_$]+}}4 : UInt<5> -;CHECK: output c{{[_$]+}}y{{[_$]+}}x{{[_$]+}}0 : UInt<5> -;CHECK: output c{{[_$]+}}y{{[_$]+}}x{{[_$]+}}1 : UInt<5> -;CHECK: output c{{[_$]+}}y{{[_$]+}}x{{[_$]+}}2 : UInt<5> -;CHECK: input c{{[_$]+}}y{{[_$]+}}y : SInt<5> -;CHECK: wire a{{[_$]+}}x : UInt<5> -;CHECK: wire a{{[_$]+}}y : SInt<5> -;CHECK: wire b{{[_$]+}}x : UInt<5> -;CHECK: wire b{{[_$]+}}y : SInt<5> -;CHECK: inst i of m -;CHECK: wire d{{[_$]+}}0 : UInt<5> -;CHECK: wire d{{[_$]+}}1 : UInt<5> -;CHECK: wire d{{[_$]+}}2 : UInt<5> -;CHECK: wire d{{[_$]+}}3 : UInt<5> -;CHECK: wire d{{[_$]+}}4 : UInt<5> -;CHECK: a{{[_$]+}}x <= b{{[_$]+}}x -;CHECK: a{{[_$]+}}y <= i.a{{[_$]+}}y -;CHECK: b{{[_$]+}}x <= i.b{{[_$]+}}x -;CHECK: b{{[_$]+}}y <= a{{[_$]+}}y -;CHECK: i.a{{[_$]+}}x <= a{{[_$]+}}x -;CHECK: i.b{{[_$]+}}y <= b{{[_$]+}}y -;CHECK: Finished Lower Types diff --git a/test/passes/lower-to-ground/instance.fir b/test/passes/lower-to-ground/instance.fir deleted file mode 100644 index e0175f34..00000000 --- a/test/passes/lower-to-ground/instance.fir +++ /dev/null @@ -1,41 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p cdg 2>&1 | tee %s.out | FileCheck %s - -circuit top : - module source : - output data : UInt<16> - input ready : UInt<1> - data <= UInt(16) - module sink : - input data : UInt<16> - output ready : UInt<1> - ready <= UInt(1) - module top: - wire connect : { data : UInt<16>, flip ready: UInt<1> } - connect.ready <= UInt(1) - connect.data <= UInt(1) - wire connect2 : { flip data : UInt<16>, ready: UInt<1> } - connect2.ready <= UInt(1) - connect2.data <= UInt(1) - inst src of source - inst snk of sink - connect <= src - connect2 <= snk - - -; CHECK: Resolve Genders - -; CHECK: connect@<g:f> <= src@<g:m> -; CHECK: connect2@<g:f> <= snk@<g:m> - -; CHECK: Finished Resolve Genders - - -; CHECK: Lower Types - -; CHECK: connect{{[_$]+}}data@<g:f> <= src@<g:m>.data@<g:m> -; CHECK: connect2{{[_$]+}}ready@<g:f> <= snk@<g:m>.ready@<g:m> -; CHECK: src@<g:m>.ready@<g:f> <= connect{{[_$]+}}ready@<g:m> -; CHECK: snk@<g:m>.data@<g:f> <= connect2{{[_$]+}}data@<g:m> - -; CHECK: Finished Lower Types -; CHECK: Done! diff --git a/test/passes/lower-to-ground/nested-vec.fir b/test/passes/lower-to-ground/nested-vec.fir deleted file mode 100644 index 7f9306ce..00000000 --- a/test/passes/lower-to-ground/nested-vec.fir +++ /dev/null @@ -1,68 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s - -; CHECK: Lower Types -circuit top : - module top : - input clk : Clock - input i : UInt<1> - wire j : { x : UInt<32>, flip y : UInt<32> } - wire k : { x : UInt<32>, y : UInt<32> } - - wire a : { x : UInt<32>, flip y : UInt<32> }[2] - ; CHECK: wire a{{[_$]+}}0{{[_$]+}}x : UInt<32> - ; CHECK: wire a{{[_$]+}}0{{[_$]+}}y : UInt<32> - ; CHECK: wire a{{[_$]+}}1{{[_$]+}}x : UInt<32> - ; CHECK: wire a{{[_$]+}}1{{[_$]+}}y : UInt<32> - a[0].x <= UInt(0) - a[0].y <= UInt(0) - a[1].x <= UInt(0) - a[1].y <= UInt(0) - j.x <= UInt(0) - j.y <= UInt(0) - k.x <= UInt(0) - k.y <= UInt(0) - - wire b : { x : UInt<32>, flip y : UInt<32> } - b <= a[i] - j <= b - - mem m : - data-type => { x : UInt<32>, y : UInt<32> } - depth => 2 - read-latency => 0 - write-latency => 1 - writer => c - - m.c.addr <= i - m.c.clk <= clk - m.c.en <= UInt(1) - m.c.mask.x <= UInt(1) - m.c.mask.y <= UInt(1) - m.c.data <= k - -;CHECK: mem m_x : -;CHECK: data-type => UInt<32> -;CHECK: depth => 2 -;CHECK: write-latency => 1 -;CHECK: read-latency => 0 -;CHECK: writer => c -;CHECK: mem m_y : -;CHECK: data-type => UInt<32> -;CHECK: depth => 2 -;CHECK: write-latency => 1 -;CHECK: read-latency => 0 -;CHECK: writer => c -;CHECK: m_x.c.data <= k_x -;CHECK: m_y.c.data <= k_y -;CHECK: m_x.c.mask <= UInt<1>("h1") -;CHECK: m_y.c.mask <= UInt<1>("h1") -;CHECK: m_x.c.addr <= i -;CHECK: m_y.c.addr <= i -;CHECK: m_x.c.en <= UInt<1>("h1") -;CHECK: m_y.c.en <= UInt<1>("h1") -;CHECK: m_x.c.clk <= clk -;CHECK: m_y.c.clk <= clk - -; CHECK: Finished Lower Types -; CHECK: Done! - diff --git a/test/passes/lower-to-ground/register.fir b/test/passes/lower-to-ground/register.fir deleted file mode 100644 index 648964bd..00000000 --- a/test/passes/lower-to-ground/register.fir +++ /dev/null @@ -1,24 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s - -; CHECK: Lower Types - circuit top : - module top : - input a : UInt<16> - input b : UInt<16> - input clk : Clock - input reset : UInt<1> - - wire q : { x : UInt, y : SInt } - q.x <= UInt(0) - q.y <= SInt(0) - reg r1 : { x : UInt, y : SInt } clk with : - reset => (reset,q) - - ; CHECK: wire q{{[_$]+}}x : UInt - ; CHECK: wire q{{[_$]+}}y : SInt - ; CHECK: reg r1{{[_$]+}}x : UInt<1>, clk with : - ;CHECK: reset => (reset, q_x) - ; CHECK: reg r1{{[_$]+}}y : SInt<1>, clk with : - ;CHECK: reset => (reset, q_y) - -; CHECK: Finished Lower Types diff --git a/test/passes/lower-to-ground/test.fir b/test/passes/lower-to-ground/test.fir deleted file mode 100644 index ac3ef21e..00000000 --- a/test/passes/lower-to-ground/test.fir +++ /dev/null @@ -1,16 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; CHECK: Done! - -circuit Top : - module Queue : - output out : {valid : UInt<1>, flip ready : UInt<1>} - out.valid <= UInt(1) - module Top : - output this : {out : {valid : UInt<1>, flip ready : UInt<1>}} - inst queue of Queue - this.out <= queue.out - wire w : { x : UInt<5>, flip y : UInt<5>} - w.x <= UInt(1) - wire a : UInt<5> - a <= UInt(1) - w.y <= a diff --git a/test/passes/pull-muxes/Muxes.fir b/test/passes/pull-muxes/Muxes.fir deleted file mode 100644 index 295e3ca0..00000000 --- a/test/passes/pull-muxes/Muxes.fir +++ /dev/null @@ -1,17 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -circuit Top : - module Top : - input a : {f:UInt<3>[3]}[2] - input b : {f:UInt<3>[3]}[2] - input p : UInt<1> - input i : UInt<1> - node x = mux(p,mux(p,a[i],a[1]).f,b[i].f)[2] - - - -;CHECK: Pull Muxes -;CHECK: node x = mux(p, mux(p, a[i].f[2], a[1].f[2]), b[i].f[2]) -;CHECK: Finished Pull Muxes -;CHECK: Done! - - diff --git a/test/passes/remove-accesses/bundle-vecs.fir b/test/passes/remove-accesses/bundle-vecs.fir deleted file mode 100644 index 6370ace1..00000000 --- a/test/passes/remove-accesses/bundle-vecs.fir +++ /dev/null @@ -1,44 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s - -; CHECK: Remove Accesses -circuit top : - module top : - wire i : UInt - i <= UInt(1) - wire j : UInt - j <= UInt(1) - - wire a : { x : UInt<32>, flip y : UInt<32> }[2] - a[0].x <= UInt(1) - a[0].y <= UInt(1) - a[1].x <= UInt(1) - a[1].y <= UInt(1) - - wire b : { x : UInt<32>, flip y : UInt<32> } - b <= a[i] - j <= b.x - b.y <= UInt(1) - -; CHECK: wire i : UInt<1> -; CHECK: i <= UInt<1>("h1") -; CHECK: wire j : UInt<32> -; CHECK: j <= UInt<1>("h1") -; CHECK: wire a : { x : UInt<32>, flip y : UInt<32>}[2] -; CHECK: a[0].x <= UInt<1>("h1") -; CHECK: a[0].y <= UInt<1>("h1") -; CHECK: a[1].x <= UInt<1>("h1") -; CHECK: a[1].y <= UInt<1>("h1") -; CHECK: wire b : { x : UInt<32>, flip y : UInt<32>} -; CHECK: wire GEN_0 : UInt<32> -; CHECK: GEN_0 <= a[0].x -; CHECK: when eq(UInt<1>("h1"), i) : GEN_0 <= a[1].x -; CHECK: b.x <= GEN_0 -; CHECK: wire GEN_1 : UInt<32> -; CHECK: when eq(UInt<1>("h0"), i) : a[0].y <= GEN_1 -; CHECK: when eq(UInt<1>("h1"), i) : a[1].y <= GEN_1 -; CHECK: GEN_1 <= b.y -; CHECK: j <= b.x -; CHECK: b.y <= UInt<1>("h1") -; CHECK: Finished Remove Access -; CHECK: Done! - diff --git a/test/passes/remove-accesses/init-vecs.fir b/test/passes/remove-accesses/init-vecs.fir deleted file mode 100644 index d8eeec88..00000000 --- a/test/passes/remove-accesses/init-vecs.fir +++ /dev/null @@ -1,15 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s - -circuit top : - module top : - wire outs : UInt<32>[2][1] - outs[0][0] <= UInt(1) - outs[0][1] <= UInt(1) - - wire out : UInt<32>[2] - out <= outs[UInt(0)] - out[0] <= UInt(1) - -; CHECK: Done! - - diff --git a/test/passes/remove-accesses/simple.fir b/test/passes/remove-accesses/simple.fir deleted file mode 100644 index 1a64d321..00000000 --- a/test/passes/remove-accesses/simple.fir +++ /dev/null @@ -1,14 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s - -circuit top : - module top : - output o : UInt - wire m : UInt<32>[2] - wire i : UInt - m[0] <= UInt("h1") - m[1] <= UInt("h1") - i <= UInt("h1") - node a = m[i] - o <= a - -;CHECK: Done! diff --git a/test/passes/remove-accesses/simple10.fir b/test/passes/remove-accesses/simple10.fir deleted file mode 100644 index b213f372..00000000 --- a/test/passes/remove-accesses/simple10.fir +++ /dev/null @@ -1,16 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p cg 2>&1 | tee %s.out | FileCheck %s - -;CHECK: Done! - -circuit DecoupledAdderTests : - module DecoupledAdderTests : - input clock : Clock - input reset : UInt<1> - input T_31 : UInt<1> - input T_68 : UInt<1> - output out : UInt - output io : {} - wire T_43 : {flip ready : UInt<1>}[1] - T_43[0].ready <= UInt(0) - node T_78 = and(T_68, T_43[T_31].ready) - out <= T_78 diff --git a/test/passes/remove-accesses/simple11.fir b/test/passes/remove-accesses/simple11.fir deleted file mode 100644 index b27f1a46..00000000 --- a/test/passes/remove-accesses/simple11.fir +++ /dev/null @@ -1,151 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s - -;CHECK: Done! - -circuit DecoupledAdderTests : - module NewDecoupledAdder : - input clock : Clock - input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {a : UInt<16>, b : UInt<16>}}, out : {flip ready : UInt<1>, valid : UInt<1>, bits : {c : UInt<16>}}} - - io.out.bits.c <= UInt<1>("h00") - io.out.valid <= UInt<1>("h00") - io.in.ready <= UInt<1>("h00") - reg ready : UInt<1>, clock with : - reset => ( reset, ready) - reg busy : UInt<1>, clock with : - reset => ( reset, busy) - reg a_reg : UInt<16>, clock with : - reset => ( reset, a_reg) - reg b_reg : UInt<16>, clock with : - reset => ( reset, b_reg) - io.in.ready <= ready - when io.in.valid : - a_reg <= io.in.bits.a - b_reg <= io.in.bits.b - io.in.ready <= UInt<1>("h00") - ready <= UInt<1>("h00") - busy <= UInt<1>("h01") - skip - node T_45 = and(busy, io.out.ready) - when T_45 : - node T_46 = tail(add(a_reg, b_reg),1) - io.out.bits.c <= T_46 - io.out.valid <= UInt<1>("h01") - io.in.ready <= UInt<1>("h01") - busy <= UInt<1>("h00") - skip - - module DecoupledAdderTests : - input clock : Clock - input reset : UInt<1> - output io : {} - - inst device_under_test of NewDecoupledAdder - device_under_test.io.out.ready <= UInt<1>("h00") - device_under_test.io.in.bits.b <= UInt<1>("h00") - device_under_test.io.in.bits.a <= UInt<1>("h00") - device_under_test.io.in.valid <= UInt<1>("h00") - device_under_test.clock <= clock - device_under_test.reset <= reset - reg T_10 : UInt<33>, clock with : - reset => ( reset, UInt<33>("h00")) - node T_12 = tail(add(T_10, UInt<1>("h01")),1) - T_10 <= T_12 - node T_14 = eq(reset, UInt<1>("h00")) - when T_14 : - printf(clock,UInt(1), "ticker %d", T_10) - skip - node T_16 = gt(T_10, UInt<7>("h064")) - when T_16 : - node T_18 = eq(reset, UInt<1>("h00")) - when T_18 : - stop(clock,UInt(1), 0) - skip - skip - node T_20 = eq(reset, UInt<1>("h00")) - when T_20 : - printf(clock,UInt(1), "device out ready %d, valid %d", device_under_test.io.out.ready, device_under_test.io.out.valid) - skip - node T_22 = eq(reset, UInt<1>("h00")) - when T_22 : - printf(clock,UInt(1), "device in ready %d, valid %d", device_under_test.io.in.ready, device_under_test.io.in.valid) - skip - reg T_24 : UInt<1>, clock with : - reset => ( reset, UInt<1>("h00")) - reg T_26 : UInt<1>, clock with : - reset => ( reset, UInt<1>("h00")) - node T_27 = and(T_24, T_26) - when T_27 : - node T_29 = eq(reset, UInt<1>("h00")) - when T_29 : - stop(clock,UInt(1), 0) - skip - skip - reg T_31 : UInt<1>, clock with : - reset => ( reset, UInt<1>("h00")) - reg T_33 : UInt<1>, clock with : - reset => ( reset, UInt<1>("h00")) - wire T_43 : {flip ready : UInt<1>, valid : UInt<1>, bits : {a : UInt<16>, b : UInt<16>}}[1] - T_43[0].bits.b <= UInt(0) - T_43[0].bits.a <= UInt(1) - T_43[0].valid <= UInt(1) - device_under_test.io.in <- T_43[0] - wire T_64 : UInt<16>[1] - T_64[0] <= UInt<16>("h04") - node T_68 = eq(T_24, UInt<1>("h00")) - node T_78 = and(T_68, T_43[T_31].ready) - when T_78 : - node T_80 = eq(reset, UInt<1>("h00")) - when T_80 : - printf(clock,UInt(1), "input_event_counter %d", T_31) - skip - device_under_test.io.in.bits.a <= T_64[T_31] - skip - wire T_84 : UInt<16>[1] - T_84[0] <= UInt<16>("h07") - node T_88 = eq(T_24, UInt<1>("h00")) - node T_98 = and(T_88, T_43[T_31].ready) - when T_98 : - node T_100 = eq(reset, UInt<1>("h00")) - when T_100 : - printf(clock,UInt(1), "input_event_counter %d", T_31) - skip - device_under_test.io.in.bits.b <= T_84[T_31] - skip - node T_103 = eq(T_24, UInt<1>("h00")) - node T_113 = and(T_103, T_43[T_31].ready) - when T_113 : - T_43[T_31].valid <= UInt<1>("h01") - node T_125 = tail(add(T_31, UInt<1>("h01")),1) - T_31 <= T_125 - node T_127 = geq(T_31, UInt<1>("h00")) - T_24 <= T_127 - skip - node T_129 = eq(T_26, UInt<1>("h00")) - when T_129 : - node T_131 = tail(add(T_33, UInt<1>("h01")),1) - T_33 <= T_131 - node T_133 = geq(T_33, UInt<1>("h00")) - T_26 <= T_133 - skip - wire T_136 : UInt<1>[1] - T_136[0] <= UInt<1>("h01") - wire T_141 : UInt<16>[1] - T_141[0] <= UInt<16>("h03") - node T_145 = eq(T_26, UInt<1>("h00")) - node T_147 = and(T_145, T_136[T_33]) - node T_148 = and(T_147, device_under_test.io.out.valid) - when T_148 : - node T_150 = eq(reset, UInt<1>("h00")) - when T_150 : - printf(clock,UInt(1), "output_event_counter %d", T_33) - skip - node T_152 = neq(device_under_test.io.out.bits.c, T_141[T_33]) - when T_152 : - node T_155 = eq(reset, UInt<1>("h00")) - when T_155 : - printf(clock,UInt(1), "Error: event %d out.bits.c was %x should be %x", T_33, device_under_test.io.out.bits.c, T_141[T_33]) - skip - skip - skip diff --git a/test/passes/remove-accesses/simple2.fir b/test/passes/remove-accesses/simple2.fir deleted file mode 100644 index ee6b5923..00000000 --- a/test/passes/remove-accesses/simple2.fir +++ /dev/null @@ -1,16 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s - -circuit top : - module top : - output o1 : UInt - output o2 : UInt - wire m : UInt<32>[2] - wire i : UInt - m[0] <= UInt("h1") - m[1] <= UInt("h1") - i <= UInt("h1") - node a = m[i] - o1 <= a - o2 <= a - -;CHECK: Done! diff --git a/test/passes/remove-accesses/simple3.fir b/test/passes/remove-accesses/simple3.fir deleted file mode 100644 index 9aa0f34f..00000000 --- a/test/passes/remove-accesses/simple3.fir +++ /dev/null @@ -1,24 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s - -;CHECK: Remove Accesses -circuit top : - module top : - input in : UInt<32> - input i : UInt<1> - wire m : UInt<32>[2] - m[0] <= UInt("h1") - m[1] <= UInt("h1") - wire a : UInt<32> - m[i] <= a - a <= in - -;CHECK: wire GEN_0 : UInt<32> -;CHECK: when eq(UInt<1>("h0"), i) : m[0] <= GEN_0 -;CHECK: when eq(UInt<1>("h1"), i) : m[1] <= GEN_0 -;CHECK: GEN_0 <= a - -;CHECK: Finished Remove Accesses - - - -;CHECK: Done! diff --git a/test/passes/remove-accesses/simple4.fir b/test/passes/remove-accesses/simple4.fir deleted file mode 100644 index f4f3a6a5..00000000 --- a/test/passes/remove-accesses/simple4.fir +++ /dev/null @@ -1,22 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s - -;CHECK: Remove Accesses -circuit top : - module top : - input in : {x : UInt<32>, y : UInt<32>} - input i : UInt<1> - wire m : {x : UInt<32>, y : UInt<32>}[2] - m[0].x <= UInt("h1") - m[0].y <= UInt("h1") - m[1].x <= UInt("h1") - m[1].y <= UInt("h1") - m[i].x <= in.x - -;CHECK: when eq(UInt<1>("h0"), i) : m[0].x <= GEN_0 -;CHECK: when eq(UInt<1>("h1"), i) : m[1].x <= GEN_0 -;CHECK: GEN_0 <= in -;CHECK: Finished Remove Accesses -;CHECK: Done! - - - diff --git a/test/passes/remove-accesses/simple5.fir b/test/passes/remove-accesses/simple5.fir deleted file mode 100644 index e21dcf1a..00000000 --- a/test/passes/remove-accesses/simple5.fir +++ /dev/null @@ -1,21 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s - -;CHECK: Remove Accesses -circuit top : - module top : - output o : UInt - o <= UInt(1) - wire m : UInt<32>[2] - wire i : UInt - m[0] <= UInt("h1") - m[1] <= UInt("h1") - i <= UInt("h1") - when i : - o <= m[i] - -;CHECK: when i : -;CHECK: GEN_0 <= m[0] -;CHECK: when eq(UInt<1>("h1"), i) : GEN_0 <= m[1] -;CHECK: o <= GEN_0 -;CHECK: Finished Remove Accesses -;CHECK: Done! diff --git a/test/passes/remove-accesses/simple6.fir b/test/passes/remove-accesses/simple6.fir deleted file mode 100644 index eee62681..00000000 --- a/test/passes/remove-accesses/simple6.fir +++ /dev/null @@ -1,21 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s - -;CHECK: Remove Accesses -circuit top : - module top : - input value : UInt<32> - input in : {x : UInt<32>, y : UInt<32>} - wire m :{x : UInt<32>, y : UInt<32>}[2][2] - wire i : UInt - wire j : UInt - - m[0][0] <= in - m[1][0] <= in - m[0][1] <= in - m[1][1] <= in - i <= UInt("h1") - j <= UInt("h1") - - m[i][j].x <= value - -;CHECK: Done! diff --git a/test/passes/remove-accesses/simple7.fir b/test/passes/remove-accesses/simple7.fir deleted file mode 100644 index 5dfd5ce3..00000000 --- a/test/passes/remove-accesses/simple7.fir +++ /dev/null @@ -1,11 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s - -circuit top : - module top : - output out : UInt<64> - input index : UInt<1> - wire T_292 : UInt<64>[2] - T_292[0] <= UInt(1) - T_292[1] <= UInt(1) - out <= T_292[index] -;CHECK: Done! diff --git a/test/passes/remove-accesses/simple8.fir b/test/passes/remove-accesses/simple8.fir deleted file mode 100644 index 1d275618..00000000 --- a/test/passes/remove-accesses/simple8.fir +++ /dev/null @@ -1,241 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s - -circuit top : - module top : - output resp : UInt<128>[4] - input write : {flip ready : UInt<1>, valid : UInt<1>, bits : {way_en : UInt<4>, addr : UInt<12>, wmask : UInt<2>, data : UInt<128>}} - input read : {flip ready : UInt<1>, valid : UInt<1>, bits : {way_en : UInt<4>, addr : UInt<12>}} - input clock : Clock - input reset : UInt<1> - - resp[0] <= UInt<1>("h00") - resp[1] <= UInt<1>("h00") - resp[2] <= UInt<1>("h00") - resp[3] <= UInt<1>("h00") - write.ready <= UInt<1>("h00") - read.ready <= UInt<1>("h00") - node waddr = shr(write.bits.addr, 4) - node raddr = shr(read.bits.addr, 4) - node T_65 = bits(write.bits.way_en, 1, 0) - node T_66 = bits(read.bits.way_en, 1, 0) - wire T_75 : UInt<128>[2] - T_75[0] <= UInt<1>("h00") - T_75[1] <= UInt<1>("h00") - reg T_81 : UInt<12>, clock with : - reset => ( reset, T_81) - when read.valid : - T_81 <= read.bits.addr - skip - cmem T_84 : UInt<128>[256] - node T_86 = neq(T_65, UInt<1>("h00")) - node T_87 = and(T_86, write.valid) - node T_88 = bits(write.bits.wmask, 0, 0) - node T_89 = and(T_87, T_88) - when T_89 : - node T_90 = bits(write.bits.data, 63, 0) - node T_91 = cat(T_90, T_90) - node T_92 = bits(T_65, 0, 0) - node T_93 = bits(T_65, 1, 1) - wire T_95 : UInt<1>[2] - T_95[0] <= T_92 - T_95[1] <= T_93 - node T_100 = tail(sub(UInt<64>("h00"), T_95[0]),1) - node T_102 = tail(sub(UInt<64>("h00"), T_95[1]),1) - wire T_104 : UInt<64>[2] - T_104[0] <= T_100 - T_104[1] <= T_102 - node T_108 = cat(T_104[1], T_104[0]) - read mport T_109 = T_84[waddr],clock - node T_110 = not(T_108) - node T_111 = and(T_109, T_110) - node T_112 = and(T_91, T_108) - node T_113 = or(T_111, T_112) - wire T_114 : UInt<128> - T_114 <= UInt<1>("h00") - T_114 <= T_113 - write mport T_116 = T_84[waddr],clock - T_116 <= T_114 - skip - node T_118 = neq(T_66, UInt<1>("h00")) - node T_119 = and(T_118, read.valid) - reg T_120 : UInt<8>, clock with : - reset => ( reset, T_120) - when T_119 : - T_120 <= raddr - skip - read mport T_121 = T_84[T_120],clock - T_75[0] <= T_121 - cmem T_124 : UInt<128>[256] - node T_126 = neq(T_65, UInt<1>("h00")) - node T_127 = and(T_126, write.valid) - node T_128 = bits(write.bits.wmask, 1, 1) - node T_129 = and(T_127, T_128) - when T_129 : - node T_130 = bits(write.bits.data, 127, 64) - node T_131 = cat(T_130, T_130) - node T_132 = bits(T_65, 0, 0) - node T_133 = bits(T_65, 1, 1) - wire T_135 : UInt<1>[2] - T_135[0] <= T_132 - T_135[1] <= T_133 - node T_140 = tail(sub(UInt<64>("h00"), T_135[0]),1) - node T_142 = tail(sub(UInt<64>("h00"), T_135[1]),1) - wire T_144 : UInt<64>[2] - T_144[0] <= T_140 - T_144[1] <= T_142 - node T_148 = cat(T_144[1], T_144[0]) - read mport T_149 = T_124[waddr],clock - node T_150 = not(T_148) - node T_151 = and(T_149, T_150) - node T_152 = and(T_131, T_148) - node T_153 = or(T_151, T_152) - wire T_154 : UInt<128> - T_154 <= UInt<1>("h00") - T_154 <= T_153 - write mport T_156 = T_124[waddr],clock - T_156 <= T_154 - skip - node T_158 = neq(T_66, UInt<1>("h00")) - node T_159 = and(T_158, read.valid) - reg T_160 : UInt<8>, clock with : - reset => ( reset, T_160) - when T_159 : - T_160 <= raddr - skip - read mport T_161 = T_124[T_160],clock - T_75[1] <= T_161 - node T_162 = bits(T_75[0], 63, 0) - node T_163 = bits(T_75[1], 63, 0) - wire T_165 : UInt<64>[2] - T_165[0] <= T_162 - T_165[1] <= T_163 - node T_169 = bits(T_81, 3, 3) - wire T_172 : UInt<64>[2] - T_172[0] <= T_165[T_169] - T_172[1] <= T_165[1] - node T_176 = cat(T_172[1], T_172[0]) - resp[0] <= T_176 - node T_177 = bits(T_75[0], 127, 64) - node T_178 = bits(T_75[1], 127, 64) - wire T_180 : UInt<64>[2] - T_180[0] <= T_177 - T_180[1] <= T_178 - node T_184 = bits(T_81, 3, 3) - wire T_187 : UInt<64>[2] - T_187[0] <= T_180[T_184] - T_187[1] <= T_180[1] - node T_191 = cat(T_187[1], T_187[0]) - resp[1] <= T_191 - node T_192 = bits(write.bits.way_en, 3, 2) - node T_193 = bits(read.bits.way_en, 3, 2) - wire T_202 : UInt<128>[2] - T_202[0] <= UInt<1>("h00") - T_202[1] <= UInt<1>("h00") - reg T_208 : UInt<12>, clock with : - reset => ( reset, T_208) - when read.valid : - T_208 <= read.bits.addr - skip - cmem T_211 : UInt<128>[256] - node T_213 = neq(T_192, UInt<1>("h00")) - node T_214 = and(T_213, write.valid) - node T_215 = bits(write.bits.wmask, 0, 0) - node T_216 = and(T_214, T_215) - when T_216 : - node T_217 = bits(write.bits.data, 63, 0) - node T_218 = cat(T_217, T_217) - node T_219 = bits(T_192, 0, 0) - node T_220 = bits(T_192, 1, 1) - wire T_222 : UInt<1>[2] - T_222[0] <= T_219 - T_222[1] <= T_220 - node T_227 = tail(sub(UInt<64>("h00"), T_222[0]),1) - node T_229 = tail(sub(UInt<64>("h00"), T_222[1]),1) - wire T_231 : UInt<64>[2] - T_231[0] <= T_227 - T_231[1] <= T_229 - node T_235 = cat(T_231[1], T_231[0]) - read mport T_236 = T_211[waddr],clock - node T_237 = not(T_235) - node T_238 = and(T_236, T_237) - node T_239 = and(T_218, T_235) - node T_240 = or(T_238, T_239) - wire T_241 : UInt<128> - T_241 <= UInt<1>("h00") - T_241 <= T_240 - write mport T_243 = T_211[waddr],clock - T_243 <= T_241 - skip - node T_245 = neq(T_193, UInt<1>("h00")) - node T_246 = and(T_245, read.valid) - reg T_247 : UInt<8>, clock with : - reset => ( reset, T_247) - when T_246 : - T_247 <= raddr - skip - read mport T_248 = T_211[T_247],clock - T_202[0] <= T_248 - cmem T_251 : UInt<128>[256] - node T_253 = neq(T_192, UInt<1>("h00")) - node T_254 = and(T_253, write.valid) - node T_255 = bits(write.bits.wmask, 1, 1) - node T_256 = and(T_254, T_255) - when T_256 : - node T_257 = bits(write.bits.data, 127, 64) - node T_258 = cat(T_257, T_257) - node T_259 = bits(T_192, 0, 0) - node T_260 = bits(T_192, 1, 1) - wire T_262 : UInt<1>[2] - T_262[0] <= T_259 - T_262[1] <= T_260 - node T_267 = tail(sub(UInt<64>("h00"), T_262[0]),1) - node T_269 = tail(sub(UInt<64>("h00"), T_262[1]),1) - wire T_271 : UInt<64>[2] - T_271[0] <= T_267 - T_271[1] <= T_269 - node T_275 = cat(T_271[1], T_271[0]) - read mport T_276 = T_251[waddr],clock - node T_277 = not(T_275) - node T_278 = and(T_276, T_277) - node T_279 = and(T_258, T_275) - node T_280 = or(T_278, T_279) - wire T_281 : UInt<128> - T_281 <= UInt<1>("h00") - T_281 <= T_280 - write mport T_283 = T_251[waddr],clock - T_283 <= T_281 - skip - node T_285 = neq(T_193, UInt<1>("h00")) - node T_286 = and(T_285, read.valid) - reg T_287 : UInt<8>, clock with : - reset => ( reset, T_287) - when T_286 : - T_287 <= raddr - skip - read mport T_288 = T_251[T_287],clock - T_202[1] <= T_288 - node T_289 = bits(T_202[0], 63, 0) - node T_290 = bits(T_202[1], 63, 0) - wire T_292 : UInt<64>[2] - T_292[0] <= T_289 - T_292[1] <= T_290 - node T_296 = bits(T_208, 3, 3) - wire T_299 : UInt<64>[2] - T_299[0] <= T_292[T_296] - T_299[1] <= T_292[1] - node T_303 = cat(T_299[1], T_299[0]) - resp[2] <= T_303 - node T_304 = bits(T_202[0], 127, 64) - node T_305 = bits(T_202[1], 127, 64) - wire T_307 : UInt<64>[2] - T_307[0] <= T_304 - T_307[1] <= T_305 - node T_311 = bits(T_208, 3, 3) - wire T_314 : UInt<64>[2] - T_314[0] <= T_307[T_311] - T_314[1] <= T_307[1] - node T_318 = cat(T_314[1], T_314[0]) - resp[3] <= T_318 - read.ready <= UInt<1>("h01") - write.ready <= UInt<1>("h01") -;CHECK: Done! diff --git a/test/passes/remove-accesses/simple9.fir b/test/passes/remove-accesses/simple9.fir deleted file mode 100644 index d1aec9f1..00000000 --- a/test/passes/remove-accesses/simple9.fir +++ /dev/null @@ -1,17 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s - -circuit top : - module top : - input T_4910 : UInt<1> - input T_4581 : UInt<1> - input reset : UInt<1> - input clock : Clock - output out : UInt<1> - reg T_4590 : UInt<1>[2], clock with : - reset => ( reset, T_4590) - T_4590[0] <= UInt(0) - T_4590[1] <= UInt(0) - out <= UInt(0) - when T_4910 : - out <= T_4590[T_4581] -;CHECK: Done! diff --git a/test/passes/resolve-genders/bigenders.fir b/test/passes/resolve-genders/bigenders.fir deleted file mode 100644 index a13390f7..00000000 --- a/test/passes/resolve-genders/bigenders.fir +++ /dev/null @@ -1,13 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s - -;CHECK: Resolve Genders -circuit top : - module top : - input i : UInt<10> - output o : UInt<10> - wire w : {x : UInt<10>, flip y : UInt<10>} - w.x <= i - w.y <= i - o <= w.x - o <= w.y -; CHECK: Finished Resolve Genders diff --git a/test/passes/resolve-genders/bulk.fir b/test/passes/resolve-genders/bulk.fir deleted file mode 100644 index 7e746a37..00000000 --- a/test/passes/resolve-genders/bulk.fir +++ /dev/null @@ -1,14 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s - -;CHECK: Resolve Genders -circuit top : - module source : - output bundle : { data : UInt<16>, flip ready : UInt<1> } - module sink : - input bundle : { data : UInt<16>, flip ready : UInt<1> } - module top : - inst src of source - inst snk of sink - snk.bundle <= src.bundle - -; CHECK: Finished Resolve Genders diff --git a/test/passes/resolve-genders/gcd.fir b/test/passes/resolve-genders/gcd.fir deleted file mode 100644 index c2a0df4a..00000000 --- a/test/passes/resolve-genders/gcd.fir +++ /dev/null @@ -1,57 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p cg 2>&1 | tee %s.out | FileCheck %s - -;CHECK: Resolve Genders -circuit top : - module subtracter : - input x : UInt - input y : UInt - output z : UInt - z <= tail(sub(x, y),1) - ;CHECK: z@<g:f> <= tail(sub(x@<g:m>, y@<g:m>)@<g:m>, 1)@<g:m> - module gcd : - input a : UInt<16> - input b : UInt<16> - input e : UInt<1> - input clk : Clock - input reset : UInt<1> - output z : UInt<16> - output v : UInt<1> - reg x : UInt,clk with : - reset => (reset,UInt(0)) - reg y : UInt,clk with : - reset => (reset,UInt(42)) -; CHECK: reg x : UInt - when gt(x, y) : - ;CHECK: when gt(x@<g:m>, y@<g:m>)@<g:m> : - inst s of subtracter - s.x <= x - s.y <= y - x <= s.z - ;CHECK: s@<g:m>.x@<g:f> <= x@<g:m> - ;CHECK: s@<g:m>.y@<g:f> <= y@<g:m> - ;CHECK: x@<g:f> <= s@<g:m>.z@<g:m> - else : - inst s2 of subtracter - s2.x <= x - s2.y <= y - y <= s2.z - when e : - x <= a - y <= b - v <= eq(v, UInt(0)) - z <= x - module top : - input clk : Clock - input reset : UInt<1> - input a : UInt<16> - input b : UInt<16> - output z : UInt - inst i of gcd - i.a <= a - i.b <= b - i.clk <= clk - i.reset <= reset - i.e <= UInt(1) - z <= i.z - -; CHECK: Finished Resolve Genders diff --git a/test/passes/resolve-genders/ports.fir b/test/passes/resolve-genders/ports.fir deleted file mode 100644 index 246fb9ac..00000000 --- a/test/passes/resolve-genders/ports.fir +++ /dev/null @@ -1,21 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p cg 2>&1 | tee %s.out | FileCheck %s - -;CHECK: Resolve Genders -circuit top : - module source : - output data : UInt<16> - input ready : UInt<1> - data <= UInt(16) - module sink : - input data : UInt<16> - output ready : UInt<1> - module top: - wire connect : { data : UInt<16>, flip ready: UInt<1> } - inst src of source - inst snk of sink - connect.data <= src.data ;CHECK: connect@<g:f>.data@<g:f> <= src@<g:m>.data@<g:m> - src.ready <= connect.ready ;CHECK: src@<g:m>.ready@<g:f> <= connect@<g:f>.ready@<g:m> - snk.data <= connect.data ;CHECK: snk@<g:m>.data@<g:f> <= connect@<g:m>.data@<g:m> - connect.ready <= snk.ready ;CHECK: connect@<g:m>.ready@<g:f> <= snk@<g:m>.ready@<g:m> - -; CHECK: Finished Resolve Genders diff --git a/test/passes/resolve-genders/subbundle.fir b/test/passes/resolve-genders/subbundle.fir deleted file mode 100644 index e91fa52e..00000000 --- a/test/passes/resolve-genders/subbundle.fir +++ /dev/null @@ -1,14 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p cT 2>&1 | tee %s.out | FileCheck %s - -;CHECK: Lower Types -circuit top : - module top : - input clk : Clock - input reset : UInt<1> - wire w : { flip x : UInt<10>} - reg r : { flip x : UInt<10>},clk with : - reset => (reset,w) - w <= r ; CHECK r_x := w_x - w.x <= r.x ; CHECK w_x := r_x -; CHECK: Finished Lower Types - diff --git a/test/passes/resolve-kinds/gcd.fir b/test/passes/resolve-kinds/gcd.fir deleted file mode 100644 index cdc8c337..00000000 --- a/test/passes/resolve-kinds/gcd.fir +++ /dev/null @@ -1,55 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p ck 2>&1 | tee %s.out | FileCheck %s - -; CHECK: Resolve Kinds -circuit top : - module subtracter : - input x : UInt - input y : UInt - output z : UInt - z <= tail(sub(x, y),1) - ;CHECK: z@<k:port> <= tail(sub(x@<k:port>, y@<k:port>)@<k:exp>, 1)@<k:exp> - module gcd : - input clk : Clock - input reset : UInt<1> - input a : UInt<16> - input b : UInt<16> - input e : UInt<1> - output z : UInt<16> - output v : UInt<1> - reg x : UInt,clk with : - reset => (reset,UInt(0)) - reg y : UInt,clk with : - reset => (reset,UInt(42)) - when gt(x, y) : - inst s of subtracter - s.x <= x - ;CHECK: s@<k:inst>.x@<k:inst> <= x@<k:reg> - s.y <= y - x <= s.z - else : - inst s2 of subtracter - s2.x <= x - s2.y <= y - y <= s2.z - when e : - x <= a - y <= b - v <= eq(v, UInt(0)) - z <= x - module top : - input a : UInt<16> - input b : UInt<16> - input clk : Clock - input reset : UInt<1> - output z : UInt - inst i of gcd - i.a <= a - i.b <= b - i.clk <= clk - i.reset <= reset - i.e <= UInt(1) - z <= i.z - ;CHECK: z@<k:port> <= i@<k:inst>.z@<k:inst> -; CHECK: Finished Resolve Kinds - - diff --git a/test/passes/split-exp/gcd.fir b/test/passes/split-exp/gcd.fir deleted file mode 100644 index 4b42d007..00000000 --- a/test/passes/split-exp/gcd.fir +++ /dev/null @@ -1,49 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s - -;CHECK: Split Expressions -circuit top : - module subtracter : - input x : UInt - input y : UInt - output q : UInt - q <= tail(sub(x, y),1) - module gcd : - input clk : Clock - input reset : UInt<1> - input a : UInt<16> - input b : UInt<16> - input e : UInt<1> - output z : UInt<16> - reg x : UInt,clk with : - reset => (reset,UInt(0)) - reg y : UInt,clk with : - reset => (reset,UInt(42)) - when gt(x, y) : - inst s of subtracter - s.x <= x - s.y <= y - x <= s.q - else : - inst s2 of subtracter - s2.x <= x - s2.y <= y - y <= s2.q - when e : - x <= a - y <= b - z <= x - module top : - input clk : Clock - input reset : UInt<1> - input a : UInt<16> - input b : UInt<16> - output z : UInt - inst i of gcd - i.clk <= clk - i.reset <= reset - i.a <= a - i.b <= b - i.e <= UInt(1) - z <= i.z - -; CHECK: Finished Split Expressions diff --git a/test/passes/split-exp/primop.fir b/test/passes/split-exp/primop.fir deleted file mode 100644 index cdbd4e77..00000000 --- a/test/passes/split-exp/primop.fir +++ /dev/null @@ -1,21 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s - -;CHECK: Split Expressions -circuit Top : - module Top : - output out : UInt<1> - - wire m : UInt<1>[3] - m[0] <= UInt(0) - m[1] <= UInt(0) - m[2] <= UInt(0) - - wire x : UInt<1> - x <= not(UInt(1)) - wire a : UInt<1> - a <= m[x] - - out <= a - - - diff --git a/test/passes/split-exp/print-args.fir b/test/passes/split-exp/print-args.fir deleted file mode 100644 index df21949d..00000000 --- a/test/passes/split-exp/print-args.fir +++ /dev/null @@ -1,14 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s - -; CHECK: Split Expressions -; CHECK: node GEN_0 = and(a, b) -; CHECK: printf(clk, UInt<1>("h1"), "%d\n", GEN_0) - -circuit Bug : - module Bug : - input clk : Clock - input a : UInt<1> - input b : UInt<1> - - printf(clk, UInt<1>(1), "%d\n", and(a, b)) - diff --git a/test/passes/split-exp/split-and.fir b/test/passes/split-exp/split-and.fir deleted file mode 100644 index 8eb4bdab..00000000 --- a/test/passes/split-exp/split-and.fir +++ /dev/null @@ -1,8 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p cT 2>&1 | tee %s.out | FileCheck %s - -; CHECK: Done! -circuit Top : - module Top : - input a : SInt<2> - output c : UInt<2> - c <= and(a,asSInt(UInt(2))) diff --git a/test/passes/split-exp/split-in-when.fir b/test/passes/split-exp/split-in-when.fir deleted file mode 100644 index 47caa16b..00000000 --- a/test/passes/split-exp/split-in-when.fir +++ /dev/null @@ -1,25 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s - -;CHECK: Split Expressions -circuit Top : - module Top : - input p : UInt<1> - input clk : Clock - input a : UInt<10> - input b : UInt<10> - input c : UInt<10> - - reg out : UInt<10>,clk with : - reset => (p,a) - - when bits(tail(sub(a,c),1),3,3) : out <= mux(eq(bits(UInt(32),4,0),UInt(13)),tail(add(a,tail(add(b,c),1)),1),tail(sub(c,b),1)) - -;CHECK: node GEN_0 = subw(a, c) -;CHECK: node GEN_1 = bits(GEN_0, 3, 3) -;CHECK: node GEN_2 = eq(UInt<5>("h0"), UInt<4>("hd")) -;CHECK: node GEN_3 = addw(b, c) -;CHECK: node GEN_4 = addw(a, GEN_3) -;CHECK: node GEN_5 = subw(c, b) -;CHECK: out <= mux(GEN_1, mux(GEN_2, GEN_4, GEN_5), out) - -;CHECK: Finished Split Expressions diff --git a/test/passes/to-flo/gcd.fir b/test/passes/to-flo/gcd.fir deleted file mode 100644 index 680c2a9a..00000000 --- a/test/passes/to-flo/gcd.fir +++ /dev/null @@ -1,50 +0,0 @@ -; RUN: firrtl -i %s -o %s.flo -X flo -p c 2>&1 | tee %s.out | FileCheck %s -; XFAIL: * - -;CHECK: Flo -circuit top : - module subtracter : - input x : UInt - input y : UInt - output q : UInt - q <= subw(x, y) - module gcd : - input clk : Clock - input reset : UInt<1> - input a : UInt<16> - input b : UInt<16> - input e : UInt<1> - output z : UInt<16> - reg x : UInt,clk,reset - reg y : UInt,clk,reset - onreset x <= UInt(0) - onreset y <= UInt(42) - when gt(x, y) : - inst s of subtracter - s.x <= x - s.y <= y - x <= s.q - else : - inst s2 of subtracter - s2.x <= x - s2.y <= y - y <= s2.q - when e : - x <= a - y <= b - z <= x - module top : - input a : UInt<16> - input b : UInt<16> - input clk : Clock - input reset : UInt<1> - output z : UInt - inst i of gcd - i.clk <= clk - i.reset <= reset - i.a <= a - i.b <= b - i.e <= UInt(1) - z <= i.z -;CHECK: Done! - diff --git a/test/passes/to-verilog/escape-quote.fir b/test/passes/to-verilog/escape-quote.fir deleted file mode 100644 index 224026a9..00000000 --- a/test/passes/to-verilog/escape-quote.fir +++ /dev/null @@ -1,18 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog ; cat %s.v | FileCheck %s - -;CHECK: module top( -;CHECK: input clk -;CHECK: ); -;CHECK: always @(posedge clk) begin -;CHECK: `ifndef SYNTHESIS -;CHECK: if(1'h1) begin -;CHECK: $fwrite(32'h80000002,"This has an escaped quote (\") in it"); -;CHECK: end -;CHECK: `endif -;CHECK: end -;CHECK: endmodule - -circuit top : - module top : - input clk : Clock - printf(clk, UInt<1>(1), "This has an escaped quote (\") in it") diff --git a/test/passes/to-verilog/gcd.fir b/test/passes/to-verilog/gcd.fir deleted file mode 100644 index 5a50ddd1..00000000 --- a/test/passes/to-verilog/gcd.fir +++ /dev/null @@ -1,51 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p cw 2>&1 | tee %s.out | FileCheck %s - -;CHECK: Verilog -circuit top : - module subtracter : - input x : UInt - input y : UInt - output q : UInt - q <= tail(sub(x, y),1) - module gcd : - input clk : Clock - input reset : UInt<1> - input a : UInt<16> - input b : UInt<16> - input e : UInt<1> - output z : UInt<16> - reg x : UInt,clk with : - reset => (reset,UInt(0)) - reg y : UInt,clk with : - reset => (reset,UInt(42)) - when gt(x, y) : - inst s of subtracter - s.x <= x - s.y <= y - x <= s.q - else : - inst s2 of subtracter - s2.x <= x - s2.y <= y - y <= s2.q - when e : - x <= a - y <= b - z <= x - module top : - input a : UInt<16> - input b : UInt<16> - input clk : Clock - input reset : UInt<1> - output z : UInt - inst i of gcd - i.clk <= clk - i.reset <= reset - i.a <= a - i.b <= b - i.e <= UInt(1) - z <= i.z - - - -;CHECK: Done! diff --git a/test/passes/to-verilog/mem.fir b/test/passes/to-verilog/mem.fir deleted file mode 100644 index 5d1c60f0..00000000 --- a/test/passes/to-verilog/mem.fir +++ /dev/null @@ -1,12 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog ; cat %s.v | FileCheck %s - -;CHECK: reg [29:0] m [0:127]; -circuit top : - module top : - input clk : Clock - output read : UInt<30> - cmem m : UInt<30>[128], clk - read accessor x = m[UInt(0)] - read <= x - - diff --git a/test/passes/to-verilog/print-args.fir b/test/passes/to-verilog/print-args.fir deleted file mode 100644 index f0344366..00000000 --- a/test/passes/to-verilog/print-args.fir +++ /dev/null @@ -1,25 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog ; cat %s.v | FileCheck %s - -;CHECK: module Bug( -;CHECK: input clk, -;CHECK: input a, -;CHECK: input b -;CHECK: ); -;CHECK: wire GEN_0; -;CHECK: assign GEN_0 = a & b; -;CHECK: always @(posedge clk) begin -;CHECK: `ifndef SYNTHESIS -;CHECK: if(1'h1) begin -;CHECK: $fwrite(32'h80000002,"%d\n",GEN_0); -;CHECK: end -;CHECK: `endif -;CHECK: end -;CHECK: endmodule - -circuit Bug : - module Bug : - input clk : Clock - input a : UInt<1> - input b : UInt<1> - - printf(clk, UInt<1>(1), "%d\n", and(a, b)) diff --git a/test/passes/to-verilog/rd-mem.fir b/test/passes/to-verilog/rd-mem.fir deleted file mode 100644 index 59829777..00000000 --- a/test/passes/to-verilog/rd-mem.fir +++ /dev/null @@ -1,51 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c &> %s.out ; cat %s.v | FileCheck %s - -circuit top : - module top : - output rdata : UInt<32> - input index : UInt<2> - input ren : UInt<1> - input clk : Clock - - mem m : - data-type => UInt<32> - depth => 4 - read-latency => 1 - write-latency => 1 - reader => c - m.c.addr <= index - m.c.en <= ren - m.c.clk <= clk - rdata <= m.c.data - -;CHECK: module top( -;CHECK: output [31:0] rdata, -;CHECK: input [1:0] index, -;CHECK: input ren, -;CHECK: input clk -;CHECK: ); -;CHECK: reg [31:0] m [0:3]; -;CHECK: wire [31:0] m_c_data; -;CHECK: wire [1:0] m_c_addr; -;CHECK: wire m_c_en; -;CHECK: wire m_c_clk; -;CHECK: reg [1:0] GEN_0; -;CHECK: reg GEN_1; -;CHECK: assign rdata = m_c_data; -;CHECK: assign m_c_addr = index; -;CHECK: assign m_c_en = ren; -;CHECK: assign m_c_clk = clk; -;CHECK: assign m_c_data = m[GEN_0]; -;CHECK: `ifndef SYNTHESIS -;CHECK: integer initvar; -;CHECK: initial begin -;CHECK: #0.002; -;CHECK: for (initvar = 0; initvar < 4; initvar = initvar+1) -;CHECK: m[initvar] = {1{$random}}; -;CHECK: end -;CHECK: `endif -;CHECK: always @(posedge m_c_clk) begin -;CHECK: GEN_0 <= m_c_addr; -;CHECK: GEN_1 <= m_c_en; -;CHECK: end -;CHECK: endmodule diff --git a/test/passes/to-verilog/rdwr-mem.fir b/test/passes/to-verilog/rdwr-mem.fir deleted file mode 100644 index c7897163..00000000 --- a/test/passes/to-verilog/rdwr-mem.fir +++ /dev/null @@ -1,61 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog &> %s.out ; cat %s.v | FileCheck %s - -circuit top : - module top : - output rdata : UInt<32> - input wdata : UInt<32> - input index : UInt<2> - input ren : UInt<1> - input wen : UInt<1> - input clk : Clock - - smem m : UInt<32>[4] - infer mport c = m[index],clk - rdata is invalid - when ren : - rdata <= c - when wen : - c <= wdata - - -;CHECK: module top( -;CHECK: output [31:0] rdata, -;CHECK: input [31:0] wdata, -;CHECK: input [1:0] index, -;CHECK: input ren, -;CHECK: input wen, -;CHECK: input clk -;CHECK: ); -;CHECK: reg [31:0] m [0:3]; -;CHECK: wire m_c_wmode; -;CHECK: wire [31:0] m_c_rdata; -;CHECK: wire [31:0] m_c_data; -;CHECK: wire m_c_mask; -;CHECK: wire [1:0] m_c_addr; -;CHECK: wire m_c_en; -;CHECK: wire m_c_clk; -;CHECK: reg [1:0] GEN_0; -;CHECK: assign rdata = m_c_rdata; -;CHECK: assign m_c_clk = clk; -;CHECK: assign m_c_addr = index; -;CHECK: assign m_c_data = wdata; -;CHECK: assign m_c_addr = index; -;CHECK: assign m_c_mask = wen ? 1'h1 : 1'h0; -;CHECK: assign m_c_en = 1'h1; -;CHECK: assign m_c_wmode = wen ? 1'h1 : 1'h0; -;CHECK: assign m_c_rdata = m[GEN_0]; -;CHECK: `ifndef SYNTHESIS -;CHECK: integer initvar; -;CHECK: initial begin -;CHECK: #0.002; -;CHECK: for (initvar = 0; initvar < 4; initvar = initvar+1) -;CHECK: m[initvar] = {1{$random}}; -;CHECK: end -;CHECK: `endif -;CHECK: always @(posedge m_c_clk) begin -;CHECK: GEN_0 <= m_c_addr; -;CHECK: if(m_c_en & m_c_mask & m_c_wmode) begin -;CHECK: m[m_c_addr] <= m_c_data; -;CHECK: end -;CHECK: end -;CHECK: endmodule diff --git a/test/passes/to-verilog/shr.fir b/test/passes/to-verilog/shr.fir deleted file mode 100644 index 6921e74e..00000000 --- a/test/passes/to-verilog/shr.fir +++ /dev/null @@ -1,35 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s - -;CHECK: Lower Types -;CHECK: node T_928 = bits(s1_req_addr, 11, 0) -;CHECK: node s1_addr = cat(dtlb.resp_ppn, T_928) -;CHECK: Finished Lower Types - -circuit HellaCache : - module TLB_60 : - output resp : {ppn : UInt<20>} - resp.ppn <= UInt<1>("h00") - - module HellaCache : - input clock : Clock - input reset : UInt<1> - - inst dtlb of TLB_60 - poison init : {addr : UInt<40>} - reg s1_req : {addr : UInt<40>}, clock with : - reset => ( reset, init) - reg s2_req : {addr : UInt<40>}, clock with : - reset => ( reset, init) - reg s1_clk_en : UInt<1>, clock with : - reset => ( reset, UInt(0)) - - node T_928 = bits(s1_req.addr, 11, 0) - node s1_addr = cat(dtlb.resp.ppn, T_928) - when s1_clk_en : - s2_req.addr <= s1_addr - - s1_req.addr <= UInt<?>(0) - s1_clk_en <= UInt<?>(0) - - wire foo : UInt<28> - foo <= shr(s1_addr, 3) diff --git a/test/passes/to-verilog/signed-and.fir b/test/passes/to-verilog/signed-and.fir deleted file mode 100644 index ffb7bd23..00000000 --- a/test/passes/to-verilog/signed-and.fir +++ /dev/null @@ -1,17 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog ; cat %s.v | FileCheck %s - -circuit Top : - module Top : - input a : SInt<2> - output c : UInt<2> - c <= and(a,asSInt(UInt(2))) - -; CHECK: module Top( -; CHECK: input [1:0] a, -; CHECK: output [1:0] c -; CHECK: ); -; CHECK: wire [1:0] GEN_0; -; CHECK: assign c = $signed(a) & $signed(GEN_0); -; CHECK: assign GEN_0 = $signed(2'h2); -; CHECK: endmodule - diff --git a/test/passes/to-verilog/wr-mem.fir b/test/passes/to-verilog/wr-mem.fir deleted file mode 100644 index 8c197265..00000000 --- a/test/passes/to-verilog/wr-mem.fir +++ /dev/null @@ -1,45 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog &> %s.out ; cat %s.v | FileCheck %s - -circuit top : - module top : - input wdata : UInt<32> - input index : UInt<2> - input wen : UInt<1> - input clk : Clock - - smem m : UInt<32>[4] - write mport c = m[index],clk - when wen : - c <= wdata - -;CHECK: module top( -;CHECK: input [31:0] wdata, -;CHECK: input [1:0] index, -;CHECK: input wen, -;CHECK: input clk -;CHECK: ); -;CHECK: reg [31:0] m [0:3]; -;CHECK: wire [31:0] m_c_data; -;CHECK: wire [1:0] m_c_addr; -;CHECK: wire m_c_mask; -;CHECK: wire m_c_en; -;CHECK: wire m_c_clk; -;CHECK: assign m_c_data = wdata; -;CHECK: assign m_c_addr = index; -;CHECK: assign m_c_mask = wen ? 1'h1 : 1'h0; -;CHECK: assign m_c_en = 1'h1; -;CHECK: assign m_c_clk = clk; -;CHECK: `ifndef SYNTHESIS -;CHECK: integer initvar; -;CHECK: initial begin -;CHECK: #0.002; -;CHECK: for (initvar = 0; initvar < 4; initvar = initvar+1) -;CHECK: m[initvar] = {1{$random}}; -;CHECK: end -;CHECK: `endif -;CHECK: always @(posedge m_c_clk) begin -;CHECK: if(m_c_en & m_c_mask) begin -;CHECK: m[m_c_addr] <= m_c_data; -;CHECK: end -;CHECK: end -;CHECK: endmodule diff --git a/test/performance/Vector1000.fir b/test/performance/Vector1000.fir deleted file mode 100644 index 767645bb..00000000 --- a/test/performance/Vector1000.fir +++ /dev/null @@ -1,7 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog 2>&1 | tee %s.out | FileCheck %s -; CHECK: Done! -circuit Top : - module Top : - input in1 : UInt<32>[1000] - output out : UInt<32>[1000] - out <= in1 diff --git a/test/performance/Vector2000.fir b/test/performance/Vector2000.fir deleted file mode 100644 index 06a4eb13..00000000 --- a/test/performance/Vector2000.fir +++ /dev/null @@ -1,7 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog 2>&1 | tee %s.out | FileCheck %s -; CHECK: Done! -circuit Top : - module Top : - input in1 : UInt<32>[2000] - output out : UInt<32>[2000] - out <= in1 diff --git a/test/performance/Vector4000.fir b/test/performance/Vector4000.fir deleted file mode 100644 index 73b98e36..00000000 --- a/test/performance/Vector4000.fir +++ /dev/null @@ -1,7 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog 2>&1 | tee %s.out | FileCheck %s -; CHECK: Done! -circuit Top : - module Top : - input in1 : UInt<32>[4000] - output out : UInt<32>[4000] - out <= in1 diff --git a/test/performance/Vector8000.fir b/test/performance/Vector8000.fir deleted file mode 100644 index 24bdfad1..00000000 --- a/test/performance/Vector8000.fir +++ /dev/null @@ -1,7 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog 2>&1 | tee %s.out | FileCheck %s -; CHECK: Done! -circuit Top : - module Top : - input in1 : UInt<32>[8000] - output out : UInt<32>[8000] - out <= in1 |