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-rw-r--r--test/passes/remove-accesses/simple.fir14
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diff --git a/test/passes/remove-accesses/simple.fir b/test/passes/remove-accesses/simple.fir
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--- a/test/passes/remove-accesses/simple.fir
+++ /dev/null
@@ -1,14 +0,0 @@
-; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
-
-circuit top :
- module top :
- output o : UInt
- wire m : UInt<32>[2]
- wire i : UInt
- m[0] <= UInt("h1")
- m[1] <= UInt("h1")
- i <= UInt("h1")
- node a = m[i]
- o <= a
-
-;CHECK: Done!