diff options
179 files changed, 37 insertions, 14554 deletions
@@ -1,113 +1,23 @@ root_dir ?= $(PWD) -test_dir ?= $(root_dir)/test regress_dir ?= $(root_dir)/regress -firrtl_dir ?= $(root_dir)/src/main/stanza install_dir ?= $(root_dir)/utils/bin SBT ?= sbt -stanza ?= $(install_dir)/stanza -stanza_bin ?= $(install_dir)/firrtl-stanza scala_jar ?= $(install_dir)/firrtl.jar scala_src := $(shell find src -type f \( -name "*.scala" -o -path "*/resources/*" \)) -stanza_src=$(shell ls src/main/stanza/*.stanza) - -all-noise: - ${MAKE} all || ${MAKE} fail - -all: done - -# Installs Stanza into $(insall_dir) -stanza_zip_name = $(subst Darwin,mac,$(subst Linux,linux,$(shell uname))) -stanza_target_name = $(subst Darwin,os-x,$(subst Linux,linux,$(shell uname))) - -$(root_dir)/src/lib/stanza/stamp: src/lib/stanza-$(stanza_zip_name).zip - rm -rf src/lib/stanza - mkdir -p src/lib - cd src/lib && unzip stanza-$(stanza_zip_name).zip - touch $@ - -utils/bin/stanza: $(stanza) -$(stanza): $(root_dir)/src/lib/stanza/stamp $(root_dir)/utils/stanza-wrapper - cd src/lib/stanza && ./stanza -platform $(stanza_target_name) -install $(stanza) - cat $(root_dir)/utils/stanza-wrapper | sed 's!@@TOP@@!$(root_dir)!g' > $@ - -$(stanza_bin): $(stanza) $(stanza_src) - cd $(firrtl_dir) && $(stanza) -i firrtl-test-main.stanza -o $@ - -build-stanza: $(stanza) - cd $(firrtl_dir) && $(stanza) -i firrtl-test-main.stanza -o $(install_dir)/firrtl-stanza - $(MAKE) set-stanza - -build-fast: $(stanza) - cd $(firrtl_dir) && $(stanza) -i firrtl-test-main.stanza -o $(install_dir)/firrtl-stanza -flags OPTIMIZE - $(MAKE) set-stanza - -build-deploy: $(stanza) - cd $(firrtl_dir) && $(stanza) -i firrtl-main.stanza -o $(install_dir)/firrtl-stanza - $(MAKE) set-stanza - -check: - cd $(test_dir) && lit -j 2 -v . --path=$(install_dir)/ - -regress: - cd $(regress_dir) && $(install_dir)/firrtl -i rocket.fir -o rocket.v -X verilog - -parser: - cd $(test_dir)/parser && lit -v . --path=$(install_dir)/ - -perf: - cd $(test_dir)/performance && lit -v . --path=$(install_dir)/ - -jack: - cd $(test_dir)/passes/jacktest && lit -v . --path=$(install_dir)/ - -passes: - cd $(test_dir)/passes && lit -v . --path=$(install_dir)/ - -errors: - cd $(test_dir)/errors && lit -v . --path=$(install_dir)/ - -features: - cd $(test_dir)/features && lit -j 2 -v . --path=$(install_dir)/ - -chirrtl: - cd $(test_dir)/chirrtl && lit -v . --path=$(install_dir)/ - -custom: - cd $(test_dir)/custom && lit -v . --path=$(install_dir)/ --max-time=10 clean: - rm -f $(test_dir)/*/*/*.out - rm -f $(test_dir)/*/*.out - rm -rf src/lib/stanza - rm -f $(stanza) rm -f $(install_dir)/firrtl.jar - rm -f $(install_dir)/firrtl - rm -f $(install_dir)/firrtl-stanza $(SBT) "clean" -riscv: - cd $(test_dir)/riscv-mini && lit -v . --path=$(install_dir)/ - -units = ALUTop Datapath Control Core Test -v = $(addsuffix .fir.v, $(units)) - -$(units): % : - firrtl -X verilog -i test/chisel3/$*.fir -o test/chisel3/$*.fir.v -p c > test/chisel3/$*.fir.out - #scp test/chisel3/$*.fir.v adamiz@a5:/scratch/adamiz/firrtl-all/riscv-mini/generated-src/$*.v - -done: build-fast check regress - say "done" - -fail: - say "fail" - build: build-scala +regress: $(scala_jar) + cd $(regress_dir) && $(install_dir)/firrtl -i rocket.fir -o rocket.v -X verilog + # Scala Added Makefile commands build-scala: $(scala_jar) - $(MAKE) set-scala $(scala_jar): $(scala_src) $(SBT) "assembly" @@ -115,16 +25,4 @@ $(scala_jar): $(scala_src) test-scala: $(SBT) test -set-scala: - ln -f -s $(install_dir)/firrtl-scala $(install_dir)/firrtl - -set-stanza: - ln -f -s $(install_dir)/firrtl-stanza $(install_dir)/firrtl - -set-linux: - ln -f -s $(install_dir)/FileCheck_linux $(install_dir)/FileCheck - -set-osx: - ln -f -s $(install_dir)/FileCheck_mac $(install_dir)/FileCheck - -.PHONY: all install build-deploy build check clean fail succeed regress set-scala set-stanza build-scala test-scala +.PHONY: build clean regress build-scala test-scala @@ -1,56 +1,44 @@ # firrtl #### Flexible Internal Representation for RTL - This repository contains the compiler for .fir files. It is in ALPHA VERSION, so many things may change in the coming months. - There are two implementations, one in stanza and one in scala. + Firrtl is an intermediate representation (IR) for digital circuits designed as a platform for writing circuit-level transformations. + This repository consists of a collection of transformations (written in Scala) which simplify, verify, transform, or emit their input circuit. + + A Firrtl compiler is constructed by chaining together these transformations, then writing the final circuit to a file. + + This repository is in ALPHA VERSION, so many things may change in the coming months. #### Installation Instructions -*Disclaimer*: This project is in alpha, so there is no guarantee anything works. +*Disclaimer*: This project is in alpha, so there is no guarantee anything works. The installation instructions should work for OSX/Linux machines. -##### For Linux: - 1. Clone the repository: - `git clone https://github.com/ucb-bar/firrtl` - 1. Install lit (you need to have pip installed first): - `pip install lit` - 1. Inflate stanza (this will fail before it builds firrtl): - `make build` - 1. Remove first empty line in `utils/bin/stanza`, so the first line now becomes `#!/bin/bash`. - 1. Actually build firrtl: - `make build` - 1. Run `make set-linux`, which links the FileCheck binary to the Linux version. - * **Note**: This compiled binary may not run on all platforms. You may need to build - Clang/LLVM from source to extract the compiled FileCheck utility. - 1. Add `firrtl/utils/bin` to your `PATH`, so that the compiled firrtl will be - available anywhere. This also makes FileCheck available for the tests. - 1. Run tests: - `make check` - * **Note**: Stanza eats a 🐣🐣🐣🐣ton of memory and running many instances - simultaneously (as the build script does) may stall your system due to - excessive paging. Setting a memory limit seems to make everything behave - better: `ulimit -v 3096000` - 1. Build and test: - `make` +##### Prerequisites + 1. If not already installed, install [verilator](http://www.veripool.org/projects/verilator/wiki/Installing): + `brew install verilator` + 1. If not already installed, install [sbt](http://www.scala-sbt.org/): + `brew install sbt` + * **Note** Requires at least sbt 0.13.6 -##### For Mac: +##### Installation 1. Clone the repository: `git clone https://github.com/ucb-bar/firrtl` - 1. Install lit (you need to have pip installed first): - `pip install lit` - 1. Build firrtl: - `make build` - 1. Run `make set-osx`, which links the FileCheck binary to the Mac version. + `cd firrtl` + 1. Compile firrtl: + `sbt compile` 1. Run tests: - `make check` - 1. Build and test: - `make` + `sbt test` + 1. Build executable (utils/bin/firrtl): + `sbt assembly` + * **Note** You can add this directory to your path to call firrtl from other processes with th + 1. Run regression: + `mkdir -p build` + `./utils/bin/firrtl -i regress/rocket.fir -o build/rocket.v -X verilog -#### Scala implementation -The Scala FIRRTL implementation relies upon sbt 0.13.6. It uses sbt-assembly to create a fat JAR. -Using a bash script and a symbolic link it can be used with the same command-line arguments as the stanza implementation. -Example use: - 1. Build the fat JAR using the makefile: `make build-scala`, or using sbt: `sbt assembly` - * For development, you can have sbt automatically monitor for changes and recompile: `sbt ~assembly` - 1. Link firrtl to the Scala version: `make set-scala` (can be reverted with `make set-stanza`) - 1. Scala firrtl can be invoked in the same way as Stanza firrtl (and the test - make targets should continue to work): - `./utils/bin/firrtl -i <input> -o <output> -X <compiler>` +##### Useful sbt Tips + 1. Only invoke sbt once: + `sbt` + `> compile` + `> test` + 1. Run a single test suite: + `sbt "testOnly firrtlTests.UnitTests"` + 1. Continually execute a command: + `sbt ~compile` diff --git a/src/lib/stanza-linux.zip b/src/lib/stanza-linux.zip Binary files differdeleted file mode 100644 index 95f1b10b..00000000 --- a/src/lib/stanza-linux.zip +++ /dev/null diff --git a/src/lib/stanza-mac.zip b/src/lib/stanza-mac.zip Binary files differdeleted file mode 100644 index a902edd8..00000000 --- a/src/lib/stanza-mac.zip +++ /dev/null diff --git a/src/main/stanza/bigint2.stanza b/src/main/stanza/bigint2.stanza deleted file mode 100644 index e64cd9b6..00000000 --- a/src/main/stanza/bigint2.stanza +++ /dev/null @@ -1,228 +0,0 @@ -;Copyright (c) 2014 - 2016 The Regents of the University of -;California (Regents). All Rights Reserved. Redistribution and use in -;source and binary forms, with or without modification, are permitted -;provided that the following conditions are met: -; * Redistributions of source code must retain the above -; copyright notice, this list of conditions and the following -; two paragraphs of disclaimer. -; * Redistributions in binary form must reproduce the above -; copyright notice, this list of conditions and the following -; two paragraphs of disclaimer in the documentation and/or other materials -; provided with the distribution. -; * Neither the name of the Regents nor the names of its contributors -; may be used to endorse or promote products derived from this -; software without specific prior written permission. -;IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, -;SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, -;ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF -;REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT -;LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -;A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF -;ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION -;TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR -;MODIFICATIONS. - -defpackage bigint2 : - import core - import verse - -;============ Big Int Library ============= - -; d contains the Array<Int>, stored so the least significant word is at -; index 0. - -;------------ Helper Functions ------------ -public defn pow (x:Int,y:Int) -> Int : - var x* = 1 - var y* = y - while y* != 0 : - x* = times(x*,x) - y* = minus(y*,1) - x* - -public defn pow (x:Long,y:Long) -> Long : - var x* = to-long(1) - var y* = y - while y* != to-long(0) : - x* = times(x*,x) - y* = minus(y*,to-long(1)) - x* -public defn to-int (x:Long) -> Int : - if x > to-long(2147483647) or x < to-long(-2147483648) : error("Long too big to convert to Int") - else : to-int(to-string(x)) - -public defn to-int (x:BigInt) -> Int : - if length(d(x)) > 1 : error("BigInt too big to convert to Int") - else : d(x)[0] - -public defn req-num-bits (i: Int) -> Int : - val i* = - if i < 0 : ((-1 * i) - 1) - else : i - ceil-log2(i* + 1) + 1 -val word-size = 32 -val all-digits = "0123456789abcdef" - -defn as-digit (c: Char) -> Int : - index-of(all-digits, c) as Int - -defn num-words (b:BigInt) : length(d(b)) - -defn shamt (c:Char) : - if c == 'b': 1 - else if c == 'h': 4 - else: error("Unsupported BigInt base.") - -defn req-words (num-bits:Int) : (num-bits + word-size - 1) / word-size - -defn to-hex (b:BigInt) -> String : - defn as-hex (i: Int) -> String : substring(all-digits,i,i + 1) - var li = List<String>() - val tib = num-bits(b) % 4 - for i in 0 to num-bits(b) by 4 do : - val word-index = i / 32 - val bit-index = i % 32 - var mask = 15 - - val digit = - if (i + tib) == num-bits(b) : - (d(b)[word-index] >> bit-index) & (pow(2,tib) - 1) - else : - (d(b)[word-index] >> bit-index) & 15 - li = List(as-hex(digit),li) - var saw-not-zero? = false - val li* = Vector<String>() - for i in 0 to length(li) do : - val x = li[i] - if saw-not-zero? == false and x == "0" and i < length(li) - 1 : false - else : - saw-not-zero? = true - add(li*,x) - - string-join([ '\"' 'h' string-join(li*) '\"']) - -defn to-bin (b:BigInt) -> String : - string-join $ generate<Char> : - defn* loop (pos:Int) : - if (pos >= 0) : - yield(if (d(b)[pos / 32] >> (pos % 32))&1 == 1: '1' else: '0') - loop(pos - 1) - loop(num-bits(b) - 1) - -defn check-index (index:Int) -> False : - if index < 0 : error("Bit index cannot be negative") - false - -defn check-bit (bit:Int) -> False : - if bit != 0 and bit != 1 : error("Cannot set a bit other than 0 or 1") - -;------------ Library ---------------- -public defstruct BigInt <: Gettable & Settable : - d : Array<Int> - num-bits : Int -with : - constructor => #BigInt - -public defn BigInt (d:Array<Int>, num-bits:Int) : - check-index(num-bits) - if num-bits > length(d) * word-size : - error("Number of bits greater than size of BigInt") - val msw-index = req-words(num-bits) - 1 - val msb-index = num-bits % word-size - ;Zero out all bits above num-bits - if msb-index != 0 : - d[msw-index] = d[msw-index] & (2 ^ msb-index - 1) - for x in (msw-index + 1) to length(d) do : - d[msw-index] = 0 - #BigInt(d,num-bits) - -public defmethod get (b:BigInt, index:Int) -> Int : - check-index(index) - if index >= num-bits(b) : error("Bit index is too high") - val word-index = index / 32 - val bit-index = index % 32 - (d(b)[word-index] >> bit-index) & 1 - -defmethod set (b:BigInt, index:Int, bit:Int) -> False : - check-index(index) - check-bit(bit) - val word-index = index / 32 - val bit-index = index % 32 - d(b)[word-index] = ((bit & 1) << bit-index) | d(b)[word-index] - -public defmethod to-string (b:BigInt) : to-hex(b) - ;string-join([to-hex(b) "'" num-bits(b)]) - -public defmethod print (o:OutputStream, b:BigInt) : - print(o, to-string(b)) - -public defn req-num-bits (b:BigInt) -> Int : - var msb = 0 - var seen? = false - for i in 0 to num-bits(b) do : - val index = num-bits(b) - 1 - i - if b[index] != 0 and seen? == false : - msb = index - seen? = true - msb + 1 - -public defn BigIntZero (num-bits:Int) -> BigInt : - val num-words = (num-bits + word-size - 1) / word-size - val d = Array<Int>(num-words) - for i in 0 to length(d) do : - d[i] = 0 - BigInt(d,num-bits) - -public defn BigIntLit (data:Int) -> BigInt : - BigIntLit(data,req-num-bits(data)) - -public defn BigIntLit (data:Int, num-bits:Int) -> BigInt : - val b = BigIntZero(num-bits) - d(b)[0] = data - b - -public defn BigIntLit (data:String) -> BigInt : - val num-bits = (length(data) - 1) * shamt(data[0]) - BigIntLit(data,num-bits) - -public defn BigIntLit (data:String, num-bits:Int) -> BigInt : - val lit = BigIntZero(num-bits) - val digits = substring(data, 1) - ;; println-all(["BASE " base " SHAMT " shamt " DIGITS " digits]) - for i in 0 to num-words(lit) do : - d(lit)[i] = 0 - for i in 0 to length(digits) do : - val off = (length(digits) - 1 - i) * shamt(data[0]) - val wi = off / word-size - val bi = off % word-size - d(lit)[wi] = d(lit)[wi] | (as-digit(digits[i]) << bi) - ;; println-all(["OFF " off " wi " wi " bi " bi " lit[wi] " lit[wi] " => " lit]) - ;; println-all(["RES = " lit]) - lit - -;------------------- Library API ----------------- - - -;High is NOT inclusive -public defn bits (b:BigInt, high:Int, low:Int) -> BigInt : - check-index(high) - check-index(low) - if high <= low : error("High bit is less than or equal to low bit") - val b* = BigIntZero(high - low) - for i in 0 to num-bits(b*) do : - b*[i] = b[i + low] - b* - -public defn bit (b:BigInt, index:Int) -> BigInt : - check-index(index) - val b* = BigIntZero(1) - b*[0] = b[index] - b* - -public defn rsh (b:BigInt, amount:Int) -> BigInt : - check-index(amount) - bits(b,num-bits(b), amount) - - - diff --git a/src/main/stanza/chirrtl.stanza b/src/main/stanza/chirrtl.stanza deleted file mode 100644 index 43e6d2d6..00000000 --- a/src/main/stanza/chirrtl.stanza +++ /dev/null @@ -1,463 +0,0 @@ -;Copyright (c) 2014 - 2016 The Regents of the University of -;California (Regents). All Rights Reserved. Redistribution and use in -;source and binary forms, with or without modification, are permitted -;provided that the following conditions are met: -; * Redistributions of source code must retain the above -; copyright notice, this list of conditions and the following -; two paragraphs of disclaimer. -; * Redistributions in binary form must reproduce the above -; copyright notice, this list of conditions and the following -; two paragraphs of disclaimer in the documentation and/or other materials -; provided with the distribution. -; * Neither the name of the Regents nor the names of its contributors -; may be used to endorse or promote products derived from this -; software without specific prior written permission. -;IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, -;SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, -;ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF -;REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT -;LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -;A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF -;ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION -;TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR -;MODIFICATIONS. -defpackage firrtl/chirrtl : - import core - import verse - import firrtl/ir2 - import firrtl/ir-utils - import firrtl/primops - - -; =============================== -public val chirrtl-passes = to-list $ [ - CInferTypes() - CInferMDir() - RemoveCHIRRTL() - FromCHIRRTL() -] -; =============================== - - -; CHIRRTL Additional IR Nodes -public definterface MPortDir -public val MInfer = new MPortDir -public val MRead = new MPortDir -public val MWrite = new MPortDir -public val MReadWrite = new MPortDir - -defmethod print (o:OutputStream, m:MPortDir) : - switch { m == _ } : - MInfer : print(o,"infer") - MRead : print(o,"read") - MWrite : print(o,"write") - MReadWrite : print(o,"rdwr") - -public defstruct CDefMemory <: Stmt : ;LOW - info: FileInfo with: (as-method => true) - name: Symbol - type: Type - size: Int - seq?: True|False -public defstruct CDefMPort <: Stmt : - info: FileInfo with: (as-method => true) - name: Symbol - type: Type - mem: Symbol - exps: List<Expression> - direction: MPortDir - -defmethod print (o:OutputStream,c:CDefMemory) : - if seq?(c) : print-all(o, ["smem " name(c) " : " type(c) "[" size(c) "]"]) - else : print-all(o, ["cmem " name(c) " : " type(c) "[" size(c) "]"]) -defmethod map (f: Type -> Type, c:CDefMemory) -> CDefMemory : - CDefMemory(info(c),name(c),f(type(c)),size(c),seq?(c)) -defmethod map (f: Symbol -> Symbol, c:CDefMemory) -> CDefMemory : - CDefMemory(info(c),f(name(c)),type(c),size(c),seq?(c)) - -defmethod print (o:OutputStream,c:CDefMPort) : - print-all(o, [direction(c) " mport " name(c) " = " mem(c) "[" exps(c)[0] "], " exps(c)[1]]) -defmethod map (f: Expression -> Expression, c:CDefMPort) -> CDefMPort : - CDefMPort(info(c),name(c),type(c),mem(c),map(f,exps(c)),direction(c)) -defmethod map (f: Type -> Type, c:CDefMPort) -> CDefMPort : - CDefMPort(info(c),name(c),f(type(c)),mem(c),exps(c),direction(c)) -defmethod map (f: Symbol -> Symbol, c:CDefMPort) -> CDefMPort : - CDefMPort(info(c),f(name(c)),type(c),mem(c),exps(c),direction(c)) - - -;======================= Infer Chirrtl Types ====================== -public defstruct CInferTypes <: Pass -public defmethod pass (b:CInferTypes) -> (Circuit -> Circuit) : infer-types -public defmethod name (b:CInferTypes) -> String : "CInfer Types" -public defmethod short-name (b:CInferTypes) -> String : "cinfertypes" - -;--------------- Utils ----------------- - -defn set-type (s:Stmt,t:Type) -> Stmt : - match(s) : - (s:DefWire) : DefWire(info(s),name(s),t) - (s:DefRegister) : DefRegister(info(s),name(s),t,clock(s),reset(s),init(s)) - (s:CDefMemory) : CDefMemory(info(s),name(s),t,size(s),seq?(s)) - (s:CDefMPort) : CDefMPort(info(s),name(s),t,mem(s),exps(s),direction(s)) - (s:DefNode) : s - (s:DefPoison) : DefPoison(info(s),name(s),t) - -defn to-field (p:Port) -> Field : - if direction(p) == OUTPUT : Field(name(p),DEFAULT,type(p)) - else if direction(p) == INPUT : Field(name(p),REVERSE,type(p)) - else : error("Shouldn't be here") -defn module-type (m:Module) -> Type : - BundleType(for p in ports(m) map : to-field(p)) -defn field-type (v:Type,s:Symbol) -> Type : - match(v) : - (v:BundleType) : - val ft = for p in fields(v) find : name(p) == s - if ft != false : type(ft as Field) - else : UnknownType() - (v) : UnknownType() -defn sub-type (v:Type) -> Type : - match(v) : - (v:VectorType) : type(v) - (v) : UnknownType() - -;--------------- Pass ----------------- - -defn infer-types (c:Circuit) -> Circuit : - val module-types = HashTable<Symbol,Type>(symbol-hash) - defn infer-types (m:Module) -> Module : - val types = HashTable<Symbol,Type>(symbol-hash) - defn infer-types-e (e:Expression) -> Expression : - match(map(infer-types-e,e)) : - (e:Ref) : Ref(name(e), get?(types,name(e),UnknownType())) - (e:SubField) : SubField(exp(e),name(e),field-type(type(exp(e)),name(e))) - (e:SubIndex) : SubIndex(exp(e),value(e),sub-type(type(exp(e)))) - (e:SubAccess) : SubAccess(exp(e),index(e),sub-type(type(exp(e)))) - (e:DoPrim) : set-primop-type(e) - (e:Mux) : Mux(cond(e),tval(e),fval(e),mux-type(tval(e),tval(e))) - (e:ValidIf) : ValidIf(cond(e),value(e),type(value(e))) - (e:UIntValue|SIntValue) : e - defn infer-types-s (s:Stmt) -> Stmt : - match(s) : - (s:DefRegister) : - types[name(s)] = type(s) - map(infer-types-e,s) - s - (s:DefWire|DefPoison) : - types[name(s)] = type(s) - s - (s:DefNode) : - val s* = map(infer-types-e,s) - val t = type(value(s*)) - types[name(s*)] = t - s* - (s:DefMemory) : - types[name(s)] = get-type(s) - s - (s:CDefMPort) : - val t = get?(types,mem(s),UnknownType()) - types[name(s)] = t - CDefMPort(info(s),name(s),t,mem(s),exps(s),direction(s)) - (s:CDefMemory) : - types[name(s)] = type(s) - s - (s:DefInstance) : - types[name(s)] = get?(module-types,module(s),UnknownType()) - s - (s) : map{infer-types-e,_} $ map(infer-types-s,s) - for p in ports(m) do : - types[name(p)] = type(p) - match(m) : - (m:InModule) : - InModule(info(m),name(m),ports(m),infer-types-s(body(m))) - (m:ExModule) : m - - ; MAIN - for m in modules(c) do : - module-types[name(m)] = module-type(m) - Circuit{info(c), _, main(c) } $ - for m in modules(c) map : - infer-types(m) - -;========================================== - -public defstruct CInferMDir <: Pass -public defmethod pass (b:CInferMDir) -> (Circuit -> Circuit) : infer-mdir -public defmethod name (b:CInferMDir) -> String : "CInfer MDir" -public defmethod short-name (b:CInferMDir) -> String : "cinfermdir" - -defn infer-mdir (c:Circuit) -> Circuit : - defn infer-mdir (m:Module) -> Module : - val mports = HashTable<Symbol,MPortDir>(symbol-hash) - defn infer-mdir-e (e:Expression,dir:MPortDir) -> Expression : - match(map(infer-mdir-e{_,dir},e)) : - (e:Ref) : - if key?(mports,name(e)) : - val new_mport_dir = - switch fn ([x,y]) : mports[name(e)] == x and dir == y : - [MInfer,MInfer] : error("Shouldn't be here") - [MInfer,MWrite] : MWrite - [MInfer,MRead] : MRead - [MInfer,MReadWrite] : MReadWrite - [MWrite,MInfer] : error("Shouldn't be here") - [MWrite,MWrite] : MWrite - [MWrite,MRead] : MReadWrite - [MWrite,MReadWrite] : MReadWrite - [MRead,MInfer] : error("Shouldn't be here") - [MRead,MWrite] : MReadWrite - [MRead,MRead] : MRead - [MRead,MReadWrite] : MReadWrite - [MReadWrite,MInfer] : error("Shouldn't be here") - [MReadWrite,MWrite] : MReadWrite - [MReadWrite,MRead] : MReadWrite - [MReadWrite,MReadWrite] : MReadWrite - mports[name(e)] = new_mport_dir - e - (e) : e - defn infer-mdir-s (s:Stmt) -> Stmt : - match(s) : - (s:CDefMPort) : - mports[name(s)] = direction(s) - map(infer-mdir-e{_,MRead},s) - (s:Connect|BulkConnect) : - infer-mdir-e(exp(s),MRead) - infer-mdir-e(loc(s),MWrite) - s - (s) : map{infer-mdir-e{_,MRead},_} $ map(infer-mdir-s,s) - defn set-mdir-s (s:Stmt) -> Stmt : - match(s) : - (s:CDefMPort) : - CDefMPort(info(s),name(s),type(s),mem(s),exps(s),mports[name(s)]) - (s) : map(set-mdir-s,s) - match(m) : - (m:InModule) : - infer-mdir-s(body(m)) - InModule(info(m),name(m),ports(m),set-mdir-s(body(m))) - (m:ExModule) : m - - ; MAIN - Circuit{info(c), _, main(c) } $ - for m in modules(c) map : - infer-mdir(m) - -;========================================== -public defstruct RemoveCHIRRTL <: Pass -public defmethod pass (b:RemoveCHIRRTL) -> (Circuit -> Circuit) : remove-chirrtl -public defmethod name (b:RemoveCHIRRTL) -> String : "Remove CHIRRTL" -public defmethod short-name (b:RemoveCHIRRTL) -> String : "removechirrtl" - -defstruct MPort : - name : Symbol - clk : Expression -defstruct MPorts : - readers : Vector<MPort> - writers : Vector<MPort> - readwriters : Vector<MPort> -defstruct DataRef : - exp : Expression - male : Symbol - female : Symbol - mask : Symbol - rdwrite? : True|False - -public definterface Gender -public val MALE = new Gender -public val FEMALE = new Gender - -defn create-exps (e:Expression) -> List<Expression> : - match(e) : - (e:Mux) : - for (e1 in create-exps(tval(e)), e2 in create-exps(fval(e))) map : - Mux(cond(e),e1,e2,mux-type(e1,e2)) - (e:ValidIf) : - for e1 in create-exps(value(e)) map : - ValidIf(cond(e),e1,type(e1)) - (e) : - match(type(e)) : - (t:UIntType|SIntType|ClockType) : list(e) - (t:BundleType) : - for f in fields(t) map-append : - create-exps(SubField(e,name(f),type(f))) - (t:VectorType) : - for i in 0 to size(t) map-append : - create-exps(SubIndex(e,i,type(t))) - (t:UnknownType) : list(e) - -defn remove-chirrtl (c:Circuit) : - defn remove-chirrtl-m (m:InModule) -> InModule : - val hash = HashTable<Symbol,MPorts>(symbol-hash) - val sh = get-sym-hash(m,keys(v-keywords)) - val repl = HashTable<Symbol,DataRef>(symbol-hash) - val ut = UnknownType() - val mport-types = HashTable<Symbol,Type>(symbol-hash) - defn EMPs () -> MPorts : - MPorts(Vector<MPort>(),Vector<MPort>(),Vector<MPort>()) - defn collect-mports (s:Stmt) -> Stmt : - match(s) : - (s:CDefMPort) : - val mports = get?(hash,mem(s),EMPs()) - switch { _ == direction(s) } : - MRead : add(readers(mports),MPort(name(s),exps(s)[1])) - MWrite : add(writers(mports),MPort(name(s),exps(s)[1])) - MReadWrite : add(readwriters(mports),MPort(name(s),exps(s)[1])) - hash[mem(s)] = mports - s - (s) : map(collect-mports,s) - defn collect-refs (s:Stmt) -> Stmt : - match(s) : - (s:CDefMemory) : - mport-types[name(s)] = type(s) - val stmts = Vector<Stmt>() - ;val naddr = firrtl-gensym(`GEN,sh) - val taddr = UIntType(IntWidth(max(1,ceil-log2(size(s))))) - ;add(stmts,DefPoison(info(s),naddr,taddr)) - ;val ndata = firrtl-gensym(`GEN,sh) - val tdata = type(s) - ;add(stmts,DefPoison(info(s),ndata,tdata)) - defn set-poison (vec:List<MPort>,addr:Symbol) -> False : - for r in vec do : - add(stmts,IsInvalid(info(s),SubField(SubField(Ref(name(s),ut),name(r),ut),addr,taddr))) - add(stmts,Connect(info(s),SubField(SubField(Ref(name(s),ut),name(r),ut),`clk,taddr),clk(r))) - defn set-enable (vec:List<MPort>,en:Symbol) -> False: - for r in vec do : - add(stmts,Connect(info(s),SubField(SubField(Ref(name(s),ut),name(r),ut),en,taddr),zero)) - defn set-wmode (vec:List<MPort>,wmode:Symbol) -> False: - for r in vec do : - add(stmts,Connect(info(s),SubField(SubField(Ref(name(s),ut),name(r),ut),wmode,taddr),zero)) - defn set-write (vec:List<MPort>,data:Symbol,mask:Symbol) -> False : - val tmask = create-mask(type(s)) - for r in vec do : - add(stmts,IsInvalid(info(s),SubField(SubField(Ref(name(s),ut),name(r),ut),data,tdata))) - for x in create-exps(SubField(SubField(Ref(name(s),ut),name(r),ut),mask,tmask)) do : - add(stmts,Connect(info(s),x,zero)) - - val rds = to-list $ readers $ get?(hash,name(s),EMPs()) - set-poison(rds,`addr) - set-enable(rds,`en) - val wrs = to-list $ writers $ get?(hash,name(s),EMPs()) - set-poison(wrs,`addr) - set-enable(wrs,`en) - set-write(wrs,`data,`mask) - val rws = to-list $ readwriters $ get?(hash,name(s),EMPs()) - set-poison(rws,`addr) - set-wmode(rws,`wmode) - set-enable(rws,`en) - set-write(rws,`data,`mask) - val read-l = - if seq?(s) : 1 - else : 0 - val mem = DefMemory(info(s),name(s),type(s),size(s),1,read-l,map(name,rds),map(name,wrs),map(name,rws)) - Begin $ List(mem,to-list(stmts)) - (s:CDefMPort) : - mport-types[name(s)] = mport-types[mem(s)] - val addrs = Vector<Symbol>() - val ens = Vector<Symbol>() - val masks = Vector<Symbol>() - switch { _ == direction(s) } : - MReadWrite : - repl[name(s)] = DataRef(SubField(Ref(mem(s),ut),name(s),ut),`rdata,`data,`mask,true) - add(addrs,`addr) - add(ens,`en) - add(masks,`mask) - MWrite : - repl[name(s)] = DataRef(SubField(Ref(mem(s),ut),name(s),ut),`data,`data,`mask,false) - add(addrs,`addr) - add(ens,`en) - add(masks,`mask) - else : - repl[name(s)] = DataRef(SubField(Ref(mem(s),ut),name(s),ut),`data,`data,`blah,false) - add(addrs,`addr) - add(ens,`en) - - val stmts = Vector<Stmt>() - for x in addrs do : - add(stmts,Connect(info(s),SubField(SubField(Ref(mem(s),ut),name(s),ut),x,ut),exps(s)[0])) - for x in ens do : - add(stmts,Connect(info(s),SubField(SubField(Ref(mem(s),ut),name(s),ut),x,ut),one)) - Begin $ to-list $ stmts - (s) : map(collect-refs,s) - defn remove-chirrtl-s (s:Stmt) -> Stmt : - var has-write-mport? = false - var has-readwrite-mport? = false - defn remove-chirrtl-e (e:Expression,g:Gender) -> Expression : - match(e) : - (e:Ref) : - if key?(repl,name(e)) : - val vt = repl[name(e)] - switch {g == _ }: - MALE : SubField(exp(vt),male(vt),type(e)) - FEMALE : - has-write-mport? = true - if rdwrite?(vt) == true : - has-readwrite-mport? = SubField(exp(vt),`wmode,UIntType(IntWidth(1))) - SubField(exp(vt),female(vt),type(e)) - else : e - (e:SubAccess) : SubAccess(remove-chirrtl-e(exp(e),g),remove-chirrtl-e(index(e),MALE),type(e)) - (e) : map(remove-chirrtl-e{_,g},e) - defn get-mask (e:Expression) -> Expression : - match(map(get-mask,e)) : - (e:Ref) : - if key?(repl,name(e)) : - val vt = repl[name(e)] - val t = create-mask(type(e)) - SubField(exp(vt),mask(vt),t) - else : e - (e) : e - match(s) : - (s:Connect) : - val stmts = Vector<Stmt>() - val roc* = remove-chirrtl-e(exp(s),MALE) - val loc* = remove-chirrtl-e(loc(s),FEMALE) - add(stmts,Connect(info(s),loc*,roc*)) - if has-write-mport? : - val e = get-mask(loc(s)) - for x in create-exps(e) do : - add(stmts,Connect(info(s),x,one)) - if has-readwrite-mport? != false : - val wmode = has-readwrite-mport? as Expression - add(stmts,Connect(info(s),wmode,one)) - if length(stmts) > 1 : Begin(to-list(stmts)) - else : stmts[0] - (s:BulkConnect) : - val stmts = Vector<Stmt>() - val loc* = remove-chirrtl-e(loc(s),FEMALE) - val roc* = remove-chirrtl-e(exp(s),MALE) - add(stmts,BulkConnect(info(s),loc*,roc*)) - if has-write-mport? != false : - val ls = get-valid-points(type(loc(s)),type(exp(s)),DEFAULT,DEFAULT) - val locs = create-exps(get-mask(loc(s))) - for x in ls do : - val loc* = locs[x[0]] - add(stmts,Connect(info(s),loc*,one)) - if has-readwrite-mport? != false : - val wmode = has-readwrite-mport? as Expression - add(stmts,Connect(info(s),wmode,one)) - if length(stmts) > 1 : Begin(to-list(stmts)) - else : stmts[0] - (s) : map(remove-chirrtl-e{_,MALE}, map(remove-chirrtl-s,s)) - collect-mports(body(m)) - val s* = collect-refs(body(m)) - InModule(info(m),name(m), ports(m), remove-chirrtl-s(s*)) - Circuit(info(c),modules*, main(c)) where : - val modules* = - for m in modules(c) map : - match(m) : - (m:InModule) : remove-chirrtl-m(m) - (m:ExModule) : m - - -;============ FromCHIRRTL ============== - -public defstruct FromCHIRRTL <: Pass -public defmethod pass (b:FromCHIRRTL) -> (Circuit -> Circuit) : from-chirrtl -public defmethod name (b:FromCHIRRTL) -> String : "From CHIRRTL" -public defmethod short-name (b:FromCHIRRTL) -> String : "from-chirrtl" - -defn from-chirrtl (c:Circuit) -> Circuit : - val c1 = infer-types(c) - ;println(c1) - val c2 = infer-mdir(c1) - ;println(c2) - val c3 = remove-chirrtl(c2) - ;println(c3) - c3 diff --git a/src/main/stanza/compilers.stanza b/src/main/stanza/compilers.stanza deleted file mode 100644 index 1054b622..00000000 --- a/src/main/stanza/compilers.stanza +++ /dev/null @@ -1,235 +0,0 @@ -;Copyright (c) 2014 - 2016 The Regents of the University of -;California (Regents). All Rights Reserved. Redistribution and use in -;source and binary forms, with or without modification, are permitted -;provided that the following conditions are met: -; * Redistributions of source code must retain the above -; copyright notice, this list of conditions and the following -; two paragraphs of disclaimer. -; * Redistributions in binary form must reproduce the above -; copyright notice, this list of conditions and the following -; two paragraphs of disclaimer in the documentation and/or other materials -; provided with the distribution. -; * Neither the name of the Regents nor the names of its contributors -; may be used to endorse or promote products derived from this -; software without specific prior written permission. -;IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, -;SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, -;ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF -;REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT -;LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -;A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF -;ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION -;TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR -;MODIFICATIONS. -defpackage firrtl/compiler : - import core - import verse - import firrtl/passes - import firrtl/chirrtl - import firrtl/errors - ;import firrtl/flo - ;import firrtl/verilog - import firrtl/ir2 - import firrtl/ir-utils - import firrtl/firrtl - -;public defstruct StandardFlo <: Compiler : -; with-output : (() -> False) -> False with: (as-method => true) -;public defmethod passes (c:StandardFlo) -> List<Pass> : -; to-list $ [ -; RemoveSpecialChars() -; RemoveScopes() -; CheckHighForm() -; ;; TempElimination() -; ToWorkingIR() -; ResolveKinds() -; CheckKinds() -; InferTypes() -; CheckTypes() -; ResolveGenders() -; CheckGenders() -; ExpandAccessors() -; LowerToGround() -; InlineIndexed() -; ExpandWhens() -; InferWidths() -; Pad() -; Inline() -; SplitExp() -; ToRealIR() -; CheckWidths() -; ;RemoveSpecialChars() -; CheckHighForm() -; CheckLowForm() -; Flo(with-output(c)) -; ] - -public defstruct StandardVerilog <: Compiler : - with-output : (() -> False) -> False with: (as-method => true) -public defmethod backend (c:StandardVerilog) -> List<Pass> : - to-list $ [ Verilog(with-output(c)) ] -public defmethod passes (c:StandardVerilog) -> List<Pass> : - to-list $ [ - ;RemoveSpecialChars() - ;TempElimination() ; Needs to check number of uses - ;=============== - CInferTypes() - CInferMDir() - RemoveCHIRRTL() - ;=============== - ToWorkingIR() - ;=============== - CheckHighForm() - ;=============== - ResolveKinds() - InferTypes() - CheckTypes() - ResolveGenders() - CheckGenders() - InferWidths() - CheckWidths() - ;=============== - PullMuxes() - ;=============== - ExpandConnects() - ;=============== - RemoveAccesses() - ;=============== - ExpandWhens() - ;=============== - CheckInitialization() - ;=============== - ConstProp() - ;=============== - ResolveKinds() - InferTypes() - CheckTypes() - ResolveGenders() - CheckGenders() - InferWidths() - CheckWidths() - ;=============== - LowerTypes() - ;=============== - ResolveKinds() - InferTypes() - CheckTypes() - ResolveGenders() - CheckGenders() - InferWidths() - CheckWidths() - ;=============== - VerilogWrap() - SplitExp() - VerilogRename() - Verilog(with-output(c)) - ;=============== - ;ToRealIR() - ;Pad() - ;CheckWidths() - ;CheckHighForm() - ;CheckLowForm() - ;Verilog(with-output(c)) - ] - -public defstruct StandardFIRRTL <: Compiler : - with-output : (() -> False) -> False with: (as-method => true) -public defmethod backend (c:StandardFIRRTL) -> List<Pass> : - to-list $ [ FIRRTL(with-output(c)) ] -public defmethod passes (c:StandardFIRRTL) -> List<Pass> : - to-list $ [ - FIRRTL(with-output(c)) - ] - -public defstruct StandardLoFIRRTL <: Compiler : - with-output : (() -> False) -> False with: (as-method => true) -public defmethod backend (c:StandardLoFIRRTL) -> List<Pass> : - to-list $ [ FIRRTL(with-output(c)) ] -public defmethod passes (c:StandardLoFIRRTL) -> List<Pass> : - to-list $ [ - ;=============== - RemoveCHIRRTL() - ;=============== - CheckHighForm() - ;=============== - ToWorkingIR() - ;=============== - ResolveKinds() - InferTypes() - CheckTypes() - ResolveGenders() - CheckGenders() - InferWidths() - CheckWidths() - ;=============== - Resolve() - ;=============== - ExpandConnects() - ;=============== - RemoveAccesses() - ;=============== - ExpandWhens() - ;=============== - CheckInitialization() - ;=============== - ConstProp() - ;=============== - ResolveKinds() - InferTypes() - CheckTypes() - ResolveGenders() - CheckGenders() - InferWidths() - CheckWidths() - ;=============== - LowerTypes() - ;=============== - ResolveKinds() - InferTypes() - CheckTypes() - ResolveGenders() - CheckGenders() - InferWidths() - CheckWidths() - ;=============== - SplitExp() - ;=============== - FIRRTL(with-output(c)) - ] - -;============= DRIVER ====================================== -public defn run-backend (c:Circuit,pass:Pass) : - run-passes(c,list(pass)) -public defn run-passes (c:Circuit,comp:Compiler) -> Circuit: - run-passes(c,passes(comp)) -public defn run-passes (c:Circuit,ls:List<Pass>) -> Circuit: - var c*:Circuit = c - println("Compiling!") - if PRINT-CIRCUITS : println("Original Circuit") - if PRINT-CIRCUITS : print(c) - ;val start-time = current-time-us() - val start-time = to-int(to-string(current-time-us() / to-long(1000))) - var t = start-time - val time-table = Vector<[String,Int]>() - for p in ls do : - println-all(["Starting " name(p)]) - if PRINT-CIRCUITS : println(name(p)) - c* = pass(p)(c*) - if PRINT-CIRCUITS : print(c*) - val current-time = to-int(to-string(current-time-us() / to-long(1000))) - println-all(["Finished " name(p)]) - println-all(["Milliseconds since start: " current-time - start-time]) - println-all(["Milliseconds for this pass: " current-time - t]) - println-all(["\n"]) - ;println-all([current-time - t]) - add(time-table,[name(p), current-time - t]) - t = current-time - - println("===== Time Breakdown =====") - for x in time-table do : - println-all([x[0] " --- " to-float(x[1] as Int * 100) / to-float(t - start-time) "%" " --- " to-float(x[1] as Int * 100) "ms"]) - println-all(["Total Time --- " to-float(t - start-time) "ms"]) - println("==========================") - println("Done!") - c* diff --git a/src/main/stanza/custom-compiler.stanza b/src/main/stanza/custom-compiler.stanza deleted file mode 100644 index 95686189..00000000 --- a/src/main/stanza/custom-compiler.stanza +++ /dev/null @@ -1,71 +0,0 @@ -;Copyright (c) 2014 - 2016 The Regents of the University of -;California (Regents). All Rights Reserved. Redistribution and use in -;source and binary forms, with or without modification, are permitted -;provided that the following conditions are met: -; * Redistributions of source code must retain the above -; copyright notice, this list of conditions and the following -; two paragraphs of disclaimer. -; * Redistributions in binary form must reproduce the above -; copyright notice, this list of conditions and the following -; two paragraphs of disclaimer in the documentation and/or other materials -; provided with the distribution. -; * Neither the name of the Regents nor the names of its contributors -; may be used to endorse or promote products derived from this -; software without specific prior written permission. -;IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, -;SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, -;ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF -;REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT -;LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -;A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF -;ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION -;TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR -;MODIFICATIONS. -;defpackage firrtl/custom-compiler : -; import core -; import verse -; import firrtl/ir-utils -; import firrtl/ir2 -; import firrtl/passes -; import firrtl/errors -; import firrtl/verilog -; import firrtl/custom-passes -; -;public defstruct InstrumentedVerilog <: Compiler : -; with-output: (() -> False) -> False with: (as-method => true) -; args: List<String> -;public defmethod passes (c:InstrumentedVerilog) -> List<Pass> : -; to-list $ [ -; WhenCoverage(args(c)[0],args(c)[1]) -; RemoveSpecialChars() -; RemoveScopes() -; CheckHighForm() -; TempElimination() -; ToWorkingIR() -; ;; MakeExplicitReset() -; ResolveKinds() -; CheckKinds() -; InferTypes() -; CheckTypes() -; ResolveGenders() -; CheckGenders() -; ExpandAccessors() -; LowerToGround() -; InlineIndexed() -; InferTypes() -; CheckGenders() -; ExpandWhens() -; InferWidths() -; ;Pad() -; ConstProp() -; SplitExp() -; ToRealIR() -; ;RemoveSpecialChars() -; CheckHighForm() -; CheckLowForm() -; CheckInitialization() -; Verilog(with-output(c)) -; ] -; -; diff --git a/src/main/stanza/custom-passes.stanza b/src/main/stanza/custom-passes.stanza deleted file mode 100644 index 089b9318..00000000 --- a/src/main/stanza/custom-passes.stanza +++ /dev/null @@ -1,248 +0,0 @@ -;Copyright (c) 2014 - 2016 The Regents of the University of -;California (Regents). All Rights Reserved. Redistribution and use in -;source and binary forms, with or without modification, are permitted -;provided that the following conditions are met: -; * Redistributions of source code must retain the above -; copyright notice, this list of conditions and the following -; two paragraphs of disclaimer. -; * Redistributions in binary form must reproduce the above -; copyright notice, this list of conditions and the following -; two paragraphs of disclaimer in the documentation and/or other materials -; provided with the distribution. -; * Neither the name of the Regents nor the names of its contributors -; may be used to endorse or promote products derived from this -; software without specific prior written permission. -;IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, -;SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, -;ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF -;REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT -;LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -;A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF -;ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION -;TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR -;MODIFICATIONS. -;defpackage firrtl/custom-passes : -; import core -; import verse -; import firrtl/ir-utils -; import firrtl/ir2 -; import bigint2 -; -;;============ When Coverage ============= -;public defstruct WhenCoverage <: Pass : -; port-name : String -; reg-name : String -;public defmethod pass (b:WhenCoverage) -> (Circuit -> Circuit) : when-coverage{port-name(b),reg-name(b),_} -;public defmethod name (b:WhenCoverage) -> String : "When Coverage" -;public defmethod short-name (b:WhenCoverage) -> String : "when-coverage" -; -;;============ Utilz ============= -;defn concat-all (ls:List<Expression>) -> Expression : -; if length(ls) == 0 : error("Shouldn't be here") -; if length(ls) == 1 : head(ls) -; else : DoPrim( CONCAT-OP, -; list(head(ls),concat-all(tail(ls))), -; list(), -; UIntType(UnknownWidth())) -; -;;============ When Coverage Pass ============= -;;port width = 1 bit per scope + portwidths of all instances -; -;defn needs-instrumentation (m:Module,ms:List<Module>,instrument?:HashTable<Symbol,True|False>) -> False : -; defn needs-instrumentation-s (s:Stmt) -> False : -; match(s) : -; (s:Conditionally) :instrument?[name(m)] = true -; (s:DefInstance) : -; val module-of-inst = for x in ms find : name(x) == name(module(s) as Ref) -; if module-of-inst != false : -; needs-instrumentation(module-of-inst as Module,ms,instrument?) -; instrument?[name(m)] = instrument?[name(module-of-inst as Module)] -; (s) : false -; do(needs-instrumentation-s,s) -; -; match(m) : -; (m:InModule) : do(needs-instrumentation-s,body(m)) -; (m:ExModule) : false -; -;defn when-coverage (port-name:Symbol, reg-name:Symbol, instrument?:HashTable<Symbol,True|False>, m:InModule) -> InModule : -; val when-bits = Vector<Ref>() -; val inst-bits = Vector<Ref>() -; val sym = HashTable<Symbol,Int>(symbol-hash) -; val w1 = LongWidth(1) -; val t1 = UIntType(w1) -; val u1 = UIntValue(BigIntLit("h1"),w1) -; defn when-coverage (s:Stmt) -> Stmt : -; match(s) : -; (s:Conditionally) : -; val ref = Ref(firrtl-gensym(reg-name,sym),t1) -; add(when-bits,ref) -; val conseq* = Begin(list(Connect(FileInfo()ref,u1),conseq(s))) -; map(when-coverage,Conditionally(info(s),pred(s),conseq*,alt(s))) -; (s:DefInstance) : -; if instrument?[name(module(s) as Ref)] : -; val ref = Ref(firrtl-gensym(port-name,sym),UIntType(UnknownWidth())) -; add(inst-bits,ref) -; val sfld = Subfield(Ref(name(s),UnknownType()),port-name,UnknownType()) -; Begin(list(s,Connect(FileInfo(),ref,sfld))) -; else : s -; (s) : map(when-coverage,s) -; -; val body* = when-coverage(body(m)) -; val logic = Vector<Stmt>() -; val port-ref = Ref(port-name,UIntType(UnknownWidth())) -; -; val w-ls = to-list $ when-bits -; if length(w-ls) != 0 : -; val reg-ref = Ref(reg-name,UIntType(LongWidth(length(w-ls)))) -; ;add{logic,_} $ DefRegister(FileInfo(),name(reg-ref),type(reg-ref)) TODO add clock and reset -; for (x in w-ls, i in 0 to false) do : -; add{logic,_} $ DefWire(FileInfo(),name(x),type(x)) -; add{logic,_} $ Connect(FileInfo(),x,DoPrim(BIT-SELECT-OP,list(reg-ref),list(i),UIntType(w1))) -; add{logic,_} $ Connect(FileInfo(),reg-ref,concat-all(w-ls)) -; add{logic,_} $ OnReset(FileInfo(),reg-ref,UIntValue(BigIntLit("h0"),LongWidth(length(w-ls)))) -; -; val i-ls = to-list $ inst-bits -; if length(i-ls) != 0 : -; for (x in i-ls, i in 0 to false) do : -; add{logic,_} $ DefWire(FileInfo(),name(x),type(x)) -; add{logic,_} $ Connect(FileInfo(),x,UIntValue(BigIntLit("h0"),UnknownWidth())) -; -; if instrument?[name(m)] : add{logic,_} $ Connect(FileInfo(),port-ref,concat-all(append(w-ls,i-ls))) -; -; if length(logic) != 0 : -; val ports* = List(Port(FileInfo(),port-name,OUTPUT,UIntType(UnknownWidth())),ports(m)) -; val body** = Begin(list(Begin(to-list $ logic),body*)) -; InModule(info(m),name(m),ports*,body**) -; else : m -; -;public defn when-coverage (port-name:String, reg-name:String, c:Circuit) : -; val instrument? = HashTable<Symbol,True|False>(symbol-hash) -; for m in modules(c) do : -; instrument?[name(m)] = false -; val top = for m in modules(c) find : name(m) == main(c) -; if top != false : needs-instrumentation(top as Module,modules(c),instrument?) -; -; val modules* = for m in modules(c) map : -; match(m) : -; (m:InModule) : -; when-coverage(to-symbol $ port-name,to-symbol $ reg-name,instrument?,m) -; (m:ExModule) : m -; Circuit(info(c),modules*,main(c)) -; -;;;============ Temporal Check ============= -;;public defstruct TemporalAssert : -;; module : String -;; name : String -;; value : Int -;; cycle : Int -;;public defstruct InsertTemporalAsserts <: Pass : -;; asserts : List<TemporalAssert> -;;public defmethod pass (b:InsertTemporalAsserts) -> (Circuit -> Circuit) : insert-temporal-assert{asserts(b),_} -;;public defmethod name (b:InsertTemporalAsserts) -> String : "Insert Temporal Assert" -;;public defmethod short-name (b:InsertTemporalAsserts) -> String : "insert-temporal-assert" -;; -;;;============ Utilz ============= -;;defn concat-all (ls:List<Expression>) -> Expression : -;; if length(ls) == 0 : error("Shouldn't be here") -;; if length(ls) == 1 : head(ls) -;; else : DoPrim( CONCAT-OP, -;; list(head(ls),concat-all(tail(ls))), -;; list(), -;; UIntType(UnknownWidth())) -;; -;;;============ Insert Temporal Asserts Pass ============= -;; -;; -;;public defn insert-temporal-assert (asserts:List<TemporalAssert>,m:Module) -> Module : -;; -;; for statement in body(m) do : -;; -;; for a in asserts do : -;; val mod* = for m in modules(c) find : name(m) == module(a) -;; match(mod*) : -;; (m:False) : error("Module not found") -;; (m:Module) : -;; -;; -;;defn needs-ita-instrumentation (m:Module,ms:List<Module>,instrument?:HashTable<Symbol,True|False>,asserts:List<TemporalAssert>) -> False : -;; defn needs-instrumentation-s (s:Stmt) -> False : -;; match(s) : -;; (s:DefWire|DefRegister) : instrument?[name(m)] = contains?(name(s),map(name,asserts)) -;; (s:DefInstance) : -;; val module-of-inst = for x in ms find : name(x) == name(module(s) as Ref) -;; if module-of-inst != false : -;; needs-ita-instrumentation(module-of-inst as Module,ms,instrument?,asserts) -;; instrument?[name(m)] = instrument?[name(module-of-inst as Module)] -;; (s) : false -;; do(needs-instrumentation-s,s) -;; -;; match(m) : -;; (m:InModule) : do(needs-instrumentation-s,body(m)) -;; (m:ExModule) : false -;; -;;defn insert-temporal-asserts (port-name:Symbol,assert-name:Symbol,asserts:List<TemporalAssert>,instrument?:HashTable<Symbol,True|False>, m:InModule) -> InModule : -;; val when-bits = Vector<Ref>() -;; val inst-bits = Vector<Ref>() -;; val sym = HashTable<Symbol,Int>(symbol-hash) -;; val w1 = LongWidth(1) -;; val t1 = UIntType(w1) -;; val u1 = UIntValue(to-long $ 1,w1) -;; defn insert-temporal-asserts (s:Stmt) -> Stmt : -;; match(s) : -;; (s:DefWire|DefRegister) : -;; val ref = Ref(firrtl-gensym(name(s),sym),t1) -;; add(when-bits,ref) -;; val conseq* = Begin(list(Connect(FileInfo()ref,u1),conseq(s))) -;; map(when-coverage,Conditionally(info(s),pred(s),conseq*,alt(s))) -;; (s:DefInstance) : -;; if instrument?[name(module(s) as Ref)] : -;; val ref = Ref(firrtl-gensym(port-name,sym),UIntType(UnknownWidth())) -;; add(inst-bits,ref) -;; val sfld = Subfield(Ref(name(s),UnknownType()),port-name,UnknownType()) -;; Begin(list(s,Connect(FileInfo(),ref,sfld))) -;; else : s -;; (s) : map(when-coverage,s) -;; -;; val body* = when-coverage(body(m)) -;; val logic = Vector<Stmt>() -;; val port-ref = Ref(port-name,UIntType(UnknownWidth())) -;; -;; val w-ls = to-list $ when-bits -;; if length(w-ls) != 0 : -;; val reg-ref = Ref(reg-name,UIntType(LongWidth(length(w-ls)))) -;; add{logic,_} $ DefRegister(FileInfo(),name(reg-ref),type(reg-ref)) -;; add{logic,_} $ OnReset(FileInfo(),reg-ref,UIntValue(to-long $ 0,LongWidth(length(w-ls)))) -;; for (x in w-ls, i in 0 to false) do : -;; add{logic,_} $ DefWire(FileInfo(),name(x),type(x)) -;; add{logic,_} $ Connect(FileInfo(),x,DoPrim(BIT-SELECT-OP,list(reg-ref),list(i),UIntType(w1))) -;; add{logic,_} $ Connect(FileInfo(),reg-ref,concat-all(w-ls)) -;; -;; val i-ls = to-list $ inst-bits -;; if length(i-ls) != 0 : -;; for (x in i-ls, i in 0 to false) do : -;; add{logic,_} $ DefWire(FileInfo(),name(x),type(x)) -;; add{logic,_} $ Connect(FileInfo(),x,UIntValue(to-long $ 0,UnknownWidth())) -;; -;; if instrument?[name(m)] : add{logic,_} $ Connect(FileInfo(),port-ref,concat-all(append(w-ls,i-ls))) -;; -;; if length(logic) != 0 : -;; val ports* = List(Port(FileInfo(),port-name,OUTPUT,UIntType(UnknownWidth())),ports(m)) -;; val body** = Begin(list(Begin(to-list $ logic),body*)) -;; InModule(info(m),name(m),ports*,body**) -;; else : m -;; -;;public defn when-coverage (port-name:String, reg-name:String, c:Circuit) : -;; val instrument? = HashTable<Symbol,True|False>(symbol-hash) -;; for m in modules(c) do : -;; instrument?[name(m)] = false -;; val top = for m in modules(c) find : name(m) == main(c) -;; if top != false : needs-instrumentation(top as Module,modules(c),instrument?) -;; -;; val modules* = for m in modules(c) map : -;; match(m) : -;; (m:InModule) : -;; when-coverage(to-symbol $ port-name,to-symbol $ reg-name,instrument?,m) -;; (m:ExModule) : m -;; Circuit(info(c),modules*,main(c)) -;; diff --git a/src/main/stanza/errors.stanza b/src/main/stanza/errors.stanza deleted file mode 100644 index 6d702e9b..00000000 --- a/src/main/stanza/errors.stanza +++ /dev/null @@ -1,1032 +0,0 @@ -;Copyright (c) 2014 - 2016 The Regents of the University of -;California (Regents). All Rights Reserved. Redistribution and use in -;source and binary forms, with or without modification, are permitted -;provided that the following conditions are met: -; * Redistributions of source code must retain the above -; copyright notice, this list of conditions and the following -; two paragraphs of disclaimer. -; * Redistributions in binary form must reproduce the above -; copyright notice, this list of conditions and the following -; two paragraphs of disclaimer in the documentation and/or other materials -; provided with the distribution. -; * Neither the name of the Regents nor the names of its contributors -; may be used to endorse or promote products derived from this -; software without specific prior written permission. -;IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, -;SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, -;ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF -;REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT -;LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -;A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF -;ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION -;TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR -;MODIFICATIONS. -defpackage firrtl/errors : - import core - import verse - import firrtl/ir2 - import firrtl/ir-utils - import firrtl/primops - import firrtl/passes - import firrtl-main - import bigint2 - -; TODO -; make sure it compiles, write tests, look over code to make sure its right -;========== ALL CHECKS ================= -;PARSER CHECK -; * No nested modules <- parser -; * Only modules in circuit (no statements or expressions) <- parser -; * Module must be a reference in inst declaration - -;AFTER ?????? -; o No combinational loops - -;================= High Form Check ========================== -; * Subexps of Subfield and Index can only be subfields, index, or refs -; * Can only connect to a Ref or Subfield or Index or WritePort -; * A module has the same name as main of circuit -; * mems cannot be a bundle with flips -; * instance module must have the same name as a defined module -; * Unique names per module -; * No name can be a prefix of any other name. -; * all references are declared -; * UInt only has positive ints -; * Vector types has positive size -; * Width sizes are positive -; * Primops have the correct number of arguments - -public defstruct CheckHighForm <: Pass -public defmethod pass (b:CheckHighForm) -> (Circuit -> Circuit) : check-high-form -public defmethod name (b:CheckHighForm) -> String : "High Form Check" -public defmethod short-name (b:CheckHighForm) -> String : "high-form-check" - -var sinfo! = FileInfo() - -;----------------- Errors ------------------------ -defn NotUnique (name:Symbol) : - PassException $ string-join $ - [sinfo! ": [module " mname "] Reference " name " does not have a unique name."] - -defn IsPrefix (prefix:Symbol) : - PassException $ string-join $ - [sinfo! ": [module " mname "] Symbol " prefix " is a prefix."] - -defn InvalidLOC () : - PassException $ string-join $ - [sinfo! ": [module " mname "] Invalid connect to an expression that is not a reference or a WritePort."] - -defn NegUInt () : - PassException $ string-join $ - [sinfo! ": [module " mname "] UIntValue cannot be negative."] - -defn UndeclaredReference (name:Symbol) : - PassException $ string-join $ - [sinfo! ": [module " mname "] Reference " name " is not declared."] - -defn PoisonWithFlip (name:Symbol) : - PassException $ string-join $ - [sinfo! ": [module " mname "] Poison " name " cannot be a bundle type with flips."] - -defn MemWithFlip (name:Symbol) : - PassException $ string-join $ - [sinfo! ": [module " mname "] Memory " name " cannot be a bundle type with flips."] - -defn InvalidAccess () : - PassException $ string-join $ - [sinfo! ": [module " mname "] Invalid access to non-reference."] - -defn NoTopModule (name:Symbol) : - PassException $ string-join $ - [sinfo! ": A single module must be named " name "."] - -defn ModuleNotDefined (name:Symbol) : - PassException $ string-join $ - [sinfo! ": Module " name " is not defined."] - -defn IncorrectNumArgs (op:Symbol, n:Int) : - PassException $ string-join $ - [sinfo! ": [module " mname "] Primop " op " requires " n " expression arguments."] - -defn IncorrectNumConsts (op:Symbol, n:Int) : - PassException $ string-join $ - [sinfo! ": [module " mname "] Primop " op " requires " n " integer arguments."] - -defn NegWidth () : - PassException $ string-join $ - [sinfo! ": [module " mname "] Width cannot be negative or zero."] - -defn NegVecSize () : - PassException $ string-join $ - [sinfo! ": [module " mname "] Vector type size cannot be negative."] - -defn NegMemSize () : - PassException $ string-join $ - [sinfo! ": [module " mname "] Memory size cannot be negative or zero."] - -defn IllegalUnknownWidth () : - PassException $ string-join $ - [sinfo! ": [module " mname "] Widths must be defined for memories and poison nodes."] - -defn BadPrintf (x:Char) : - PassException $ string-join $ - [sinfo! ": [module " mname "] Bad printf format: \"%" x "\""];" - -defn BadPrintfTrailing () : - PassException $ string-join $ - [sinfo! ": [module " mname "] Bad printf format: trailing \"%\""];" - -defn BadPrintfIncorrectNum () : - PassException $ string-join $ - [sinfo! ": [module " mname "] Bad printf format: incorrect number of arguments"];" - - -;---------------- Helper Functions -------------- -defn has-flip? (t:Type) -> True|False : - var has? = false - defn find-flip (t:Type) -> Type : - match(t) : - (t:BundleType) : - for f in fields(t) do : - if flip(f) == REVERSE : has? = true - t - (t) : t - find-flip(t) - map(find-flip,t) - has? - -defn contains?<?T> (c:?T,cs:Streamable<?T>) -> True|False : - label<True|False> myret : - for x in cs do : - if x == c : myret(true) - false - -;--------------- Prefix Checker -------------------- - -defstruct Trie : - children : HashTable<Symbol,Trie> - end? : True|False with: (setter => set-end) - -defmethod print (o:OutputStream,t:Trie) : - print-all(o,["[end?:" end?(t) ",children:" children(t) "]"]) - -defn split (s:Symbol) -> List<Symbol> : - map(to-symbol,split(to-string(s),'$')) - -defn contains? (t:Trie,s:Symbol) -> True|False : - key?(children(t),s) - -defn empty? (t:Trie) -> True|False : - length(children(t)) == 0 - -defn add (t:Trie,ls:List<Symbol>) -> True|False : - var t*:Trie = t - var saw-end? = false - for x in ls do : - if end?(t*) : saw-end? = true - if contains?(t*,x) : t* = children(t*)[x] - else : - val temp = Trie(HashTable<Symbol,Trie>(symbol-hash),false) - children(t*)[x] = temp - t* = temp - set-end(t*,true) - saw-end? or not empty?(t*) - -defn contains? (t:Trie,ls:List<Symbol>) -> True|False : - var t*:Trie = t - label<True|False> myret : - for x in ls do : - if contains?(t*,x) : t* = children(t*)[x] - else : myret(false) - myret(end?(t*)) - -;--------------- Check High Form Pass ------------------- -public defn check-high-form (c:Circuit) -> Circuit : - val errors = Vector<PassException>() - defn check-high-form-primop (e:DoPrim) -> False : - defn correct-num (ne:Int|False,nc:Int) -> False : - if not (ne typeof False) : - if length(args(e)) != ne as Int : add(errors,IncorrectNumArgs(to-symbol(op(e)),ne as Int)) - if length(consts(e)) != nc : add(errors,IncorrectNumConsts(to-symbol $ op(e),nc)) - - switch {op(e) == _} : - ADD-OP : correct-num(2,0) - SUB-OP : correct-num(2,0) - MUL-OP : correct-num(2,0) - DIV-OP : correct-num(2,0) - REM-OP : correct-num(2,0) - LESS-OP : correct-num(2,0) - LESS-EQ-OP : correct-num(2,0) - GREATER-OP : correct-num(2,0) - GREATER-EQ-OP : correct-num(2,0) - EQUAL-OP : correct-num(2,0) - NEQUAL-OP : correct-num(2,0) - PAD-OP : correct-num(1,1) - AS-UINT-OP : correct-num(1,0) - AS-SINT-OP : correct-num(1,0) - AS-CLOCK-OP : correct-num(1,0) - SHIFT-LEFT-OP : correct-num(1,1) - SHIFT-RIGHT-OP : correct-num(1,1) - DYN-SHIFT-LEFT-OP : correct-num(2,0) - DYN-SHIFT-RIGHT-OP : correct-num(2,0) - CONVERT-OP : correct-num(1,0) - NEG-OP : correct-num(1,0) - NOT-OP : correct-num(1,0) - AND-OP : correct-num(2,0) - OR-OP : correct-num(2,0) - XOR-OP : correct-num(2,0) - AND-REDUCE-OP : correct-num(false,0) - OR-REDUCE-OP : correct-num(false,0) - XOR-REDUCE-OP : correct-num(false,0) - CONCAT-OP : correct-num(2,0) - BITS-SELECT-OP : correct-num(1,2) - HEAD-OP : correct-num(1,1) - TAIL-OP : correct-num(1,1) - - defn check-fstring (s:String,i:Int) -> False : - val valid-formats = "bedxs" - var percent = false - var ret = true - var npercents = 0 - for x in s do : - if (not contains?(valid-formats,x)) and percent : - add(errors,BadPrintf(x)) - if x == '%' : npercents = npercents + 1 - percent = x == '%' - if percent : add(errors,BadPrintfTrailing()) - if npercents != i : add(errors,BadPrintfIncorrectNum()) - defn check-valid-loc (e:Expression) -> False : - match(e) : - (e:UIntValue|SIntValue|DoPrim) : - add(errors,InvalidLOC()) - (e) : false - defn check-high-form-w (w:Width) -> Width : - match(w) : - (w:IntWidth) : - if width(w) <= to-long(0) : - add(errors,NegWidth()) - w - (w) : w - defn check-high-form-t (t:Type) -> Type : - match(map(check-high-form-t,t)) : - (t:VectorType) : - if size(t) < 0 : add(errors,NegVecSize()) - (t) : false - map(check-high-form-w,t) - - defn check-high-form-m (m:Module) -> Module : - val names = HashTable<Symbol,True>(symbol-hash) - val mnames = HashTable<Symbol,True>(symbol-hash) - val tries = Trie(HashTable<Symbol,Trie>(symbol-hash),false) - defn check-high-form-e (e:Expression) -> Expression : - defn valid-subexp (e:Expression) -> Expression : - match(e) : - (e:WRef|WSubField|WSubIndex|WSubAccess|Mux|ValidIf) : false - (e) : add(errors,InvalidAccess()) - e - match(map(check-high-form-e,e)) : - (e:WRef) : - if not key?(names,name(e)) : - add(errors,UndeclaredReference(name(e))) - (e:DoPrim) : check-high-form-primop(e) - (e:Mux|ValidIf) : e - (e:UIntValue) : false - (e:WSubAccess) : - valid-subexp(exp(e)) - e - (e) : map(valid-subexp,e) - map(check-high-form-w,e) - map(check-high-form-t,e) - e - defn check-high-form-s (s:Stmt) -> Stmt : - defn check-name (name:Symbol) -> Symbol : - if key?(names,name) : add(errors,NotUnique(name)) - else : names[name] = true - val ls = split(name) - if add(tries,ls) : add(errors,IsPrefix(name)) - name - sinfo! = info(s) - map(check-name,s) - map(check-high-form-t,s) - map(check-high-form-e,s) - match(s) : - (s:DefWire|DefRegister|DefNode|Conditionally|Stop|Begin) : false - (s:DefPoison) : - if has-flip?(type(s)) : add(errors, PoisonWithFlip(name(s))) - check-high-form-t(type(s)) - (s:DefMemory) : - if has-flip?(data-type(s)) : add(errors, MemWithFlip(name(s))) - if depth(s) <= 0 : add(errors,NegMemSize()) - (s:WDefInstance) : - if not contains?(module(s),map(name,modules(c))) : - add(errors, ModuleNotDefined(module(s))) - (s:Connect) : check-valid-loc(loc(s)) - (s:Print) : check-fstring(string(s),length(args(s))) - (s:BulkConnect) : check-valid-loc(loc(s)) - (s) : false - - map(check-high-form-s,s) - - mname = name(m) - for m in modules(c) do : - mnames[name(m)] = true - for p in ports(m) do : - names[name(p)] = true - map(check-high-form-t,type(p)) - map(check-high-form-w,type(p)) - - match(m) : - (m:ExModule) : false - (m:InModule) : check-high-form-s(body(m)) - m - - var number-top-m = 0 - for m in modules(c) do : - if name(m) == main(c) : number-top-m = number-top-m + 1 - check-high-form-m(m) - sinfo! = info!(c) - if number-top-m != 1 : add(errors,NoTopModule(main(c))) - throw(PassExceptions(errors)) when not empty?(errors) - c - -;==================== CHECK TYPES ===================== -; o Subfields are only on bundles, before type inference <- need to not error, just do unknown-type -; o Indexes are only on vectors -; o pred in conditionally must be of type UInt -; o enable/index in read/writeports must be UInt -; o node's value cannot be a bundle with a flip in it -; o := has same types -; o 2nd arg in dshr/l must be UInt, in general do primops -; o clock must be ClockType -; o reset must be UInt<1> - -public defstruct CheckTypes <: Pass -public defmethod pass (b:CheckTypes) -> (Circuit -> Circuit) : check-types -public defmethod name (b:CheckTypes) -> String : "Check Types" -public defmethod short-name (b:CheckTypes) -> String : "check-types" - -;----------------- Errors --------------------- -defn SubfieldNotInBundle (info:FileInfo, name:Symbol) : - PassException $ string-join $ - [info ": [module " mname "] Subfield " name " is not in bundle."] - -defn SubfieldOnNonBundle (info:FileInfo, name:Symbol) : - PassException $ string-join $ - [info ": [module " mname "] Subfield " name " is accessed on a non-bundle."] - -defn IndexTooLarge (info:FileInfo, value:Int) : - PassException $ string-join $ - [info ": [module " mname "] Index with value " value " is too large."] - -defn IndexOnNonVector (info:FileInfo) : - PassException $ string-join $ - [info ": [module " mname "] Index illegal on non-vector type."] - -defn AccessIndexNotUInt (info:FileInfo) : - PassException $ string-join $ - [info ": [module " mname "] Access index must be a UInt type."] - -defn IndexNotUInt (info:FileInfo) : - PassException $ string-join $ - [info ": [module " mname "] Index is not of UIntType."] - -defn EnableNotUInt (info:FileInfo) : - PassException $ string-join $ - [info ": [module " mname "] Enable is not of UIntType."] - -defn InvalidConnect (info:FileInfo) : - PassException $ string-join $ - [info ": [module " mname "] Type mismatch."] - -defn PrintfArgNotGround (info:FileInfo) : - PassException $ string-join $ - [info ": [module " mname "] Printf arguments must be either UIntType or SIntType."] - -defn ReqClk (info:FileInfo) : - PassException $ string-join $ - [info ": [module " mname "] Requires a clock typed signal."] - -defn EnNotUInt (info:FileInfo) : - PassException $ string-join $ - [info ": [module " mname "] Enable must be a UIntType typed signal."] - -defn PredNotUInt (info:FileInfo) : - PassException $ string-join $ - [info ": [module " mname "] Predicate not a UIntType."] - -defn OpNotGround (info:FileInfo, op:Symbol) : - PassException $ string-join $ - [info ": [module " mname "] Primop " op " cannot operate on non-ground types."] - -defn OpNotUInt (info:FileInfo, op:Symbol,e:Symbol) : - PassException $ string-join $ - [info ": [module " mname "] Primop " op " requires argument " e " to be a UInt type."] - -defn OpNotAllUInt (info:FileInfo, op:Symbol) : - PassException $ string-join $ - [info ": [module " mname "] Primop " op " requires all arguments to be UInt type."] - -defn OpNotAllSameType (info:FileInfo, op:Symbol) : - PassException $ string-join $ - [info ": [module " mname "] Primop " op " requires all operands to have the same type."] - -defn NodePassiveType (info:FileInfo) : - PassException $ string-join $ - [info ": [module " mname "] Node must be a passive type."] - -defn MuxSameType (info:FileInfo) : - PassException $ string-join $ - [info ": [module " mname "] Must mux between equivalent types."] - -defn MuxPassiveTypes (info:FileInfo) : - PassException $ string-join $ - [info ": [module " mname "] Must mux between passive types."] - -defn MuxCondUInt (info:FileInfo) : - PassException $ string-join $ - [info ": [module " mname "] A mux condition must be of type UInt."] - -defn ValidIfPassiveTypes (info:FileInfo) : - PassException $ string-join $ - [info ": [module " mname "] Must validif a passive type."] - -defn ValidIfCondUInt (info:FileInfo) : - PassException $ string-join $ - [info ": [module " mname "] A validif condition must be of type UInt."] - -;---------------- Helper Functions -------------- -defmethod equal? (t1:Type,t2:Type) -> True|False : - match(t1,t2) : - (t1:ClockType,t2:ClockType) : true - (t1:UIntType,t2:UIntType) : true - (t1:SIntType,t2:SIntType) : true - (t1:BundleType,t2:BundleType) : - var same? = true - for (f1 in fields(t1),f2 in fields(t2)) do : - if flip(f1) != flip(f2) : same? = false - if name(f1) != name(f2) : same? = false - if type(f1) != type(f2) : same? = false - same? - (t1:VectorType,t2:VectorType) : - if type(t1) == type(t2) and size(t1) == size(t2) : true - else : false - (t1,t2) : false - -defn ut () -> UIntType : UIntType(UnknownWidth()) -defn st () -> SIntType : SIntType(UnknownWidth()) - -defn check-types-primop (e:DoPrim, errors:Vector<PassException>,info:FileInfo) -> False : - defn all-same-type (ls:List<Expression>) -> False : - var error? = false - for x in ls do : - if type(head(ls)) != type(x) : - error? = true - if error? : add(errors,OpNotAllSameType(info,to-symbol $ op(e))) - defn all-ground (ls:List<Expression>) -> False : - var error? = false - for x in ls do : - if not (type(x) typeof UIntType or type(x) typeof SIntType) : - error? = true - if error? : add(errors,OpNotGround(info,to-symbol $ op(e))) - defn all-uint (ls:List<Expression>) -> False : - var error? = false - for x in ls do : - if not (type(x) typeof UIntType) : - error? = true - if error? : add(errors,OpNotAllUInt(info,to-symbol $ op(e))) - defn is-uint (x:Expression) -> False : - var error? = false - if not (type(x) typeof UIntType) : - error? = true - if error? : add(errors,OpNotUInt(info,to-symbol $ op(e),to-symbol(x))) - - switch {op(e) == _} : - AS-UINT-OP : false - AS-SINT-OP : false - AS-CLOCK-OP : false - DYN-SHIFT-LEFT-OP : (is-uint(args(e)[1]) all-ground(args(e))) - DYN-SHIFT-RIGHT-OP : (is-uint(args(e)[1]) all-ground(args(e))) - ADD-OP : all-ground(args(e)) - SUB-OP : all-ground(args(e)) - MUL-OP : all-ground(args(e)) - DIV-OP : all-ground(args(e)) - REM-OP : all-ground(args(e)) - LESS-OP : all-ground(args(e)) - LESS-EQ-OP : all-ground(args(e)) - GREATER-OP : all-ground(args(e)) - GREATER-EQ-OP : all-ground(args(e)) - EQUAL-OP : all-ground(args(e)) - NEQUAL-OP : all-ground(args(e)) - PAD-OP : all-ground(args(e)) - SHIFT-LEFT-OP : all-ground(args(e)) - SHIFT-RIGHT-OP : all-ground(args(e)) - CONVERT-OP : all-ground(args(e)) - NEG-OP : all-ground(args(e)) - NOT-OP : all-ground(args(e)) - AND-OP : all-ground(args(e)) - OR-OP : all-ground(args(e)) - XOR-OP : all-ground(args(e)) - AND-REDUCE-OP : all-ground(args(e)) - OR-REDUCE-OP : all-ground(args(e)) - XOR-REDUCE-OP : all-ground(args(e)) - CONCAT-OP : all-ground(args(e)) - BITS-SELECT-OP : all-ground(args(e)) - HEAD-OP : all-ground(args(e)) - TAIL-OP : all-ground(args(e)) - -;----------------- Check Types Pass --------------------- -public defn check-types (c:Circuit) -> Circuit : - val errors = Vector<PassException>() - defn passive? (t:Type) -> True|False : - match(t) : - (t:UIntType|SIntType) : true - (t:VectorType) : passive?(type(t)) - (t:BundleType) : - var p? = true - for x in fields(t) do : - if (flip(x) == REVERSE) : p? = false - if not passive?(type(x)) : p? = false - p? - (t) : true - defn check-types-e (info:FileInfo,e:Expression) -> Expression : - match(map(check-types-e{info,_},e)) : - (e:WRef) : e - (e:WSubField) : - match(type(exp(e))) : - (t:BundleType) : - val ft = for p in fields(t) find : name(p) == name(e) - if ft == false : add(errors,SubfieldNotInBundle(info,name(e))) - (t) : add(errors,SubfieldOnNonBundle(info,name(e))) - (e:WSubIndex) : - match(type(exp(e))) : - (t:VectorType) : - if value(e) >= size(t) : add(errors,IndexTooLarge(info,value(e))) - (t) : add(errors,IndexOnNonVector(info)) - (e:WSubAccess) : - match(type(exp(e))) : - (t:VectorType) : false - (t) : add(errors,IndexOnNonVector(info)) - match(type(index(e))) : - (t:UIntType) : false - (t) : add(errors,AccessIndexNotUInt(info)) - (e:DoPrim) : check-types-primop(e,errors,info) - (e:Mux) : - if type(tval(e)) != type(fval(e)) : add(errors,MuxSameType(info)) - if not passive?(type(e)) : add(errors,MuxPassiveTypes(info)) - if not passive?(type(e)) : add(errors,MuxPassiveTypes(info)) - if not (type(cond(e)) typeof UIntType) : add(errors,MuxCondUInt(info)) - (e:ValidIf) : - if not passive?(type(e)) : add(errors,ValidIfPassiveTypes(info)) - if not (type(cond(e)) typeof UIntType) : add(errors,ValidIfCondUInt(info)) - (e:UIntValue|SIntValue) : false - e - - defn bulk-equals? (t1:Type,t2:Type) -> True|False : - match(t1,t2) : - (t1:BundleType,t2:BundleType) : - var same? = true - for (f1 in fields(t1),f2 in fields(t2)) do : - if name(f1) == name(f2) : - if flip(f1) != flip(f2) : same? = false - if not bulk-equals?(type(f1),type(f2)) : same? = false - same? - (t1:ClockType,t2:ClockType) : true - (t1:UIntType,t2:UIntType) : true - (t1:SIntType,t2:SIntType) : true - (t1:VectorType,t2:VectorType) : - if bulk-equals?(type(t1),type(t2)) : true - else : false - (t1,t2) : false - - defn check-types-s (s:Stmt) -> Stmt : - map{check-types-s,_} $ { - match(map(check-types-e{info(s),_},s)) : - (s:Connect) : - if type(loc(s)) != type(exp(s)) : add(errors,InvalidConnect(info(s))) - (s:BulkConnect) : - if not bulk-equals?(type(loc(s)),type(exp(s))) : - add(errors,InvalidConnect(info(s))) - (s:Stop) : - if type(clk(s)) != ClockType() : add(errors,ReqClk(info(s))) - if type(en(s)) != ut() : add(errors,EnNotUInt(info(s))) - (s:Print) : - for x in args(s) do : - if type(x) != ut() and type(x) != st(): - add(errors,PrintfArgNotGround(info(s))) - if type(clk(s)) != ClockType() : add(errors,ReqClk(info(s))) - if type(en(s)) != ut() : add(errors,EnNotUInt(info(s))) - (s:Conditionally) : - if type(pred(s)) != ut() : add(errors,PredNotUInt(info(s))) - (s:DefNode) : - if not passive?(type(value(s))) : - add(errors,NodePassiveType(info(s))) - (s) : false - s }() - - for m in modules(c) do : - mname = name(m) - match(m) : - (m:ExModule) : false - (m:InModule) : check-types-s(body(m)) - throw(PassExceptions(errors)) when not empty?(errors) - c - -;================= GENDER CHECK ========================== -; o Nodes always male -; o Accessors only have one gender, unless rdwr -; o output/input only one gender -; o correctly check for the base bundle - -public defstruct CheckGenders <: Pass -public defmethod pass (b:CheckGenders) -> (Circuit -> Circuit) : check-genders -public defmethod name (b:CheckGenders) -> String : "Check Genders" -public defmethod short-name (b:CheckGenders) -> String : "check-genders" - -;----------------- Errors --------------------- -defn WrongGender (info:FileInfo,expr:Symbol,wrong:Symbol,right:Symbol) : - PassException $ string-join $ - [info ": [module " mname "] Expression " expr " is used as a " wrong " but can only be used as a " right "."] - -;---------------- Helper Functions -------------- -defn dir-to-gender (d:Direction) -> Gender : - switch {_ == d} : - INPUT : MALE - OUTPUT : FEMALE ;BI-GENDER - -defn as-srcsnk (g:Gender) -> Symbol : - switch {_ == g} : - MALE : `source - FEMALE : `sink - UNKNOWN-GENDER : `unknown - BI-GENDER : `sourceOrSink - -;----------------- Check Genders Pass --------------------- - -public defn check-genders (c:Circuit) -> Circuit : - val errors = Vector<PassException>() - defn get-kind (e:Expression) -> Kind : - match(e) : - (e:WRef) : kind(e) - (e:WSubField) : get-kind(exp(e)) - (e:WSubIndex) : get-kind(exp(e)) - (e:WSubAccess) : get-kind(exp(e)) - (e) : NodeKind() - - defn check-gender (info:FileInfo,genders:HashTable<Symbol,Gender>,e:Expression,desired:Gender) -> False : - val gender = get-gender(e,genders) - val kind* = get-kind(e) - defn flip? (t:Type) -> True|False : - var f? = false - defn flip-rec (t:Type,f:Flip) -> Type : - match(t) : - (t:BundleType) : - for field in fields(t) do : - flip-rec(type(field),f * flip(field)) - (t:VectorType) : flip-rec(type(t),f) - (t) : if f == REVERSE : f? = true - t - flip-rec(t,DEFAULT) - f? - - val has-flip? = flip?(type(e)) - ;println(e) - ;println(gender) - ;println(desired) - ;println(kind*) - ;println(desired == gender) - ;if gender != desired and gender != BI-GENDER: - switch fn ([x,y]) : gender == x and desired == y : - [MALE, FEMALE] : - add(errors,WrongGender(info,to-symbol(e),as-srcsnk(desired),as-srcsnk(gender))) - [FEMALE, MALE] : - if (kind* == PortKind() or kind* == InstanceKind()) and has-flip? == false : - ; OK! - false - else : - ; Not Ok! - add(errors,WrongGender(info,to-symbol(e),as-srcsnk(desired),as-srcsnk(gender))) - else : false - - defn get-gender (e:Expression,genders:HashTable<Symbol,Gender>) -> Gender : - match(e) : - (e:WRef) : genders[name(e)] - (e:WSubField) : - val f = {_ as Field} $ for f in fields(type(exp(e)) as BundleType) find : name(f) == name(e) - get-gender(exp(e),genders) * flip(f) - (e:WSubIndex) : get-gender(exp(e),genders) - (e:WSubAccess) : get-gender(exp(e),genders) - (e:DoPrim) : MALE - (e:UIntValue) : MALE - (e:SIntValue) : MALE - (e:Mux) : MALE - (e:ValidIf) : MALE - - defn check-genders-e (info:FileInfo,e:Expression,genders:HashTable<Symbol,Gender>) -> False : - do(check-genders-e{info,_,genders},e) - match(e) : - (e:WRef) : false - (e:WSubField) : false - (e:WSubIndex) : false - (e:WSubAccess) : false - (e:DoPrim) : - for e in args(e) do : - check-gender(info,genders,e,MALE) - (e:Mux) : do(check-gender{info,genders,_,MALE},e) - (e:ValidIf) : do(check-gender{info,genders,_,MALE},e) - (e:UIntValue) : false - (e:SIntValue) : false - - defn check-genders-s (s:Stmt,genders:HashTable<Symbol,Gender>) -> False : - do(check-genders-e{info(s),_:Expression,genders},s) - do(check-genders-s{_:Stmt,genders},s) - match(s) : - (s:DefWire) : genders[name(s)] = BI-GENDER - (s:DefPoison) : genders[name(s)] = MALE - (s:DefRegister) : genders[name(s)] = BI-GENDER - (s:DefNode) : - check-gender(info(s),genders,value(s),MALE) - genders[name(s)] = MALE - (s:DefMemory) : genders[name(s)] = MALE - (s:WDefInstance) : genders[name(s)] = MALE - (s:Connect) : - check-gender(info(s),genders,loc(s),FEMALE) - check-gender(info(s),genders,exp(s),MALE) - (s:Print) : - for x in args(s) do : - check-gender(info(s),genders,x,MALE) - check-gender(info(s),genders,en(s),MALE) - check-gender(info(s),genders,clk(s),MALE) - (s:BulkConnect) : - check-gender(info(s),genders,loc(s),FEMALE) - check-gender(info(s),genders,exp(s),MALE) - (s:Conditionally) : - check-gender(info(s),genders,pred(s),MALE) - (s:Empty) : false - (s:Stop) : - check-gender(info(s),genders,en(s),MALE) - check-gender(info(s),genders,clk(s),MALE) - (s:Begin|IsInvalid) : false - - for m in modules(c) do : - mname = name(m) - val genders = HashTable<Symbol,Gender>(symbol-hash) - for p in ports(m) do : - genders[name(p)] = dir-to-gender(direction(p)) - match(m) : - (m:ExModule) : false - (m:InModule) : check-genders-s(body(m),genders) - throw(PassExceptions(errors)) when not empty?(errors) - c - -;================= Width Check ========================== -;AFTER WIDTH INFERENCE -; * No names -; * No Unknowns -; * All widths are positive -; * widths are large enough to contain value - - -public defstruct CheckWidths <: Pass -public defmethod pass (b:CheckWidths) -> (Circuit -> Circuit) : check-width -public defmethod name (b:CheckWidths) -> String : "Width Check" -public defmethod short-name (b:CheckWidths) -> String : "width-check" - -;----------------- Errors ------------------------ - -defn UninferredWidth (info:FileInfo) : - PassException $ string-join $ - [info ": [module " mname "] Uninferred width."] - -defn WidthTooSmall (info:FileInfo,v:String) : - PassException $ string-join $ - [info ": [module " mname "] Width too small for constant " v "."] - -;---------------- Helper Functions -------------- - -;--------------- Check Width Pass ------------------- -public defn check-width (c:Circuit) -> Circuit : - val errors = Vector<PassException>() - - defn check-width-m (m:Module) -> False : - defn check-width-w (info:FileInfo,w:Width) -> Width : - match(w) : - (w:IntWidth) : - if width(w) <= to-long(0) : add(errors,NegWidth()) - (w) : - add(errors,UninferredWidth(info)) - w - - defn check-width-e (info:FileInfo,e:Expression) -> Expression : - match(map(check-width-e{info,_},e)) : - (e:UIntValue) : - match(width(e)) : - (w:IntWidth) : - if max(to-long(1),to-long(req-num-bits(value(e)) - 1)) > width(w) : - add(errors,WidthTooSmall(info,to-string(value(e)))) - (w) : add(errors,UninferredWidth(info)) - check-width-w(info,width(e)) - (e:SIntValue) : - match(width(e)) : - (w:IntWidth) : - if to-long(req-num-bits(value(e))) > width(w) : - add(errors,WidthTooSmall(info,to-string(value(e)))) - (w) : add(errors,UninferredWidth(info)) - check-width-w(info,width(e)) - (e:DoPrim) : false - (e) : false - - ;mapr(check-width-w{info,_},type(map(check-width-e{info,_},e))) - e - - defn check-width-s (s:Stmt) -> Stmt : - sinfo! = info(s) - map(check-width-e{info(s),_},map(check-width-s,s)) - map(mapr{check-width-w{info(s),_},_:Type},s) - - for p in ports(m) do : - mapr(check-width-w{info(p),_},type(p)) - - match(m) : - (m:ExModule) : false - (m:InModule) : check-width-s(body(m)) - false - - for m in modules(c) do : - mname = name(m) - check-width-m(m) - throw(PassExceptions(errors)) when not empty?(errors) - c - - -;================ Initialization Check ================== -; Error on all componenents that are not connected to. - -public defstruct CheckInitialization <: Pass -public defmethod pass (b:CheckInitialization) -> (Circuit -> Circuit) : check-init -public defmethod name (b:CheckInitialization) -> String : "Check Initialization" -public defmethod short-name (b:CheckInitialization) -> String : "check-init" - -;----------------- Errors ------------------------ - -defn RefNotInitialized (info:FileInfo, name:Symbol) : - PassException $ string-join $ - [info ": [module " mname "] Reference " name " is not fully initialized."] - -;------------ Helper Functions ------------- - -;------------ Pass ------------------ - -public defn check-init (c:Circuit) : - val errors = Vector<PassException>() - - defn check-init-m (m:InModule) : - defn get-name (e:Expression) -> Symbol : - match(e) : - (e:WRef) : name(e) - (e:WSubField) : symbol-join([get-name(exp(e)) `. name(e)]) - (e:WSubIndex) : symbol-join([get-name(exp(e)) to-symbol("[") value(e) to-symbol("]")]) - (e) : error("Shouldn't be here") - defn has-void? (e:Expression) -> True|False : - var void? = false - defn has-void (e:Expression) -> Expression : - match(e) : - (e:WVoid) : - void? = true - e - (e) : map(has-void,e) - has-void(e) - void? - defn check-init-s (s:Stmt) -> Stmt : - match(s) : - (s:Connect) : - if has-void?(exp(s)) : add(errors,RefNotInitialized(info(s),get-name(loc(s)))) - s - (s) : map(check-init-s,s) - - check-init-s(body(m)) - - for m in modules(c) do : - mname = name(m) - match(m) : - (m:InModule) : check-init-m(m) - (m) : false - - throw(PassExceptions(errors)) when not empty?(errors) - c - -;;================= Low Form Check ========================== -;;AFTER LOWERING -;; o All things connect to once -;; o no reg -;; o no accessors -;; o only vecs are for memories -;; o no bundles (future, will have them for mems) -;; o only predicated conditional connects -; -;public defstruct CheckLowForm <: Pass -;public defmethod pass (b:CheckLowForm) -> (Circuit -> Circuit) : check-low-form -;public defmethod name (b:CheckLowForm) -> String : "Low Form Check" -;public defmethod short-name (b:CheckLowForm) -> String : "low-form-check" -; -;;----------------- Errors ------------------------ -;defn InvalidVec (info:FileInfo,name:Symbol) : -; PassException $ string-join $ -; [info ": [module " mname "] Expression " name " has an illegal vector type."] -; -;defn InvalidBundle (info:FileInfo,name:Symbol) : -; PassException $ string-join $ -; [info ": [module " mname "] Expression " name " has an illegal bundle type."] -; -;defn NoWhen (info:FileInfo) : -; PassException $ string-join $ -; [info ": [module " mname "] Illegal when statement. No when statements with multiple statements are allowed in low firrtl."] -; -;defn SingleAssignment (info:FileInfo,name:Symbol) : -; PassException $ string-join $ -; [info ": [module " mname "] Illegal assignment to " name ". Wires can only be assigned to once."] -; -;defn NoOnReset (info:FileInfo) : -; PassException $ string-join $ -; [info ": [module " mname "] Invalid use of on-reset. No on-resets are allowed in low firrtl."] -; -;defn NoBulkConnect (info:FileInfo) : -; PassException $ string-join $ -; [info ": [module " mname "] Invalid use of <>. No <>'s are allowed in low firrtl."] -; -;;---------------- Helper Functions -------------- -; -;;--------------- Check Low Form Pass ------------------- -;public defn check-low-form (c:Circuit) -> Circuit : -; val errors = Vector<PassException>() -; -; defn check-low-form-t (info:FileInfo,t:Type,name:Symbol) -> False : -; match(t) : -; (t:VectorType) : add(errors,InvalidVec(info,name)) -; (t:BundleType) : add(errors,InvalidBundle(info,name)) -; (t) : false -; -; defn check-low-form-m (m:Module) -> False : -; for p in ports(m) do : -; check-low-form-t(info(p),type(p),name(p)) -; -; val assigned? = HashTable<Symbol,True>(symbol-hash) -; val insts = Vector<Symbol>() -; val mems = Vector<Symbol>() -; defn check-correct-exp (info:FileInfo,e:Expression) -> False : -; do(check-correct-exp{info,_:Expression},e) -; match(e) : -; (e:Ref) : -; if contains?(insts,name(e)) : -; for f in fields(type(e) as BundleType) do : -; check-low-form-t(info,type(f),name(e)) -; if contains?(mems,name(e)) : -; check-low-form-t(info,type(type(e) as VectorType),name(e)) -; (e) : false ;check-low-form-t(info,type(e),to-symbol $ to-string(e)) -; defn check-low-form-s (s:Stmt) -> False : -; match(s) : -; (s:DefWire) : -; check-low-form-t(info(s),type(s),name(s)) -; (s:DefPoison) : -; check-low-form-t(info(s),type(s),name(s)) -; (s:DefMemory) : -; check-low-form-t(info(s),type(s),name(s)) -; add(mems,name(s)) -; (s:DefInstance) : -; for f in fields(type(module(s)) as BundleType) do : -; check-low-form-t(info(s),type(f),name(s)) -; add(insts,name(s)) -; (s:DefNode) : -; check-correct-exp(info(s),value(s)) -; (s:Print) : -; for x in args(s) do : -; check-correct-exp(info(s),x) -; (s:DefRegister) : false -; (s:DefAccessor) : false -; (s:Conditionally) : -; if (not alt(s) typeof Empty) or (conseq(s) typeof Begin) : add(errors,NoWhen(info(s))) -; (s:OnReset) : add(errors,NoOnReset(info(s))) -; (s:BulkConnect) : add(errors,NoBulkConnect(info(s))) -; (s:Connect) : -; check-correct-exp(info(s),exp(s)) -; match(loc(s)) : -; (e:Ref|Subfield) : -; val n* = to-symbol $ to-string $ e -; if key?(assigned?,n*) : add(errors,SingleAssignment(info(s),n*)) -; else : assigned?[to-symbol $ to-string $ e] = true -; (e) : check-correct-exp(info(s),e) -; (s:Empty) : false -; (s:Stop) : false -; (s:Begin) : do(check-low-form-s,s) -; -; match(m) : -; (m:ExModule) : false -; (m:InModule) : check-low-form-s(body(m)) -; false -; -; for m in modules(c) do : -; mname = name(m) -; check-low-form-m(m) -; throw(PassExceptions(errors)) when not empty?(errors) -; c -; diff --git a/src/main/stanza/firrtl-ir.stanza b/src/main/stanza/firrtl-ir.stanza deleted file mode 100644 index fdb7659a..00000000 --- a/src/main/stanza/firrtl-ir.stanza +++ /dev/null @@ -1,238 +0,0 @@ -;Copyright (c) 2014 - 2016 The Regents of the University of -;California (Regents). All Rights Reserved. Redistribution and use in -;source and binary forms, with or without modification, are permitted -;provided that the following conditions are met: -; * Redistributions of source code must retain the above -; copyright notice, this list of conditions and the following -; two paragraphs of disclaimer. -; * Redistributions in binary form must reproduce the above -; copyright notice, this list of conditions and the following -; two paragraphs of disclaimer in the documentation and/or other materials -; provided with the distribution. -; * Neither the name of the Regents nor the names of its contributors -; may be used to endorse or promote products derived from this -; software without specific prior written permission. -;IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, -;SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, -;ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF -;REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT -;LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -;A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF -;ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION -;TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR -;MODIFICATIONS. -defpackage firrtl/ir2 : - import core - import verse - import bigint2 - -public defmulti info! (x:?) -> FileInfo -public defmethod info! (x:?) : FileInfo() - -public val vector-expand-delin = `$ -public val bundle-expand-delin = `$ -public val module-expand-delin = `$ -public val scope-delin = `_ -public val inline-delin = `_ -public val delin = `_ - -public definterface Direction -public val INPUT = new Direction -public val OUTPUT = new Direction - -public definterface Flip -public val DEFAULT = new Flip -public val REVERSE = new Flip - -public definterface Width -public defstruct UnknownWidth <: Width -public defn IntWidth (width:Int) : IntWidth(to-long(width)) -public defstruct IntWidth <: Width : - width: Long - -public definterface PrimOp -public val ADD-OP = new PrimOp -public val SUB-OP = new PrimOp -public val MUL-OP = new PrimOp -public val DIV-OP = new PrimOp -public val REM-OP = new PrimOp -public val LESS-OP = new PrimOp -public val LESS-EQ-OP = new PrimOp -public val GREATER-OP = new PrimOp -public val GREATER-EQ-OP = new PrimOp -public val NEQUAL-OP = new PrimOp -public val EQUAL-OP = new PrimOp -public val PAD-OP = new PrimOp -public val AS-UINT-OP = new PrimOp -public val AS-SINT-OP = new PrimOp -public val AS-CLOCK-OP = new PrimOp -public val SHIFT-LEFT-OP = new PrimOp -public val SHIFT-RIGHT-OP = new PrimOp -public val DYN-SHIFT-LEFT-OP = new PrimOp -public val DYN-SHIFT-RIGHT-OP = new PrimOp -public val NEG-OP = new PrimOp -public val CONVERT-OP = new PrimOp -public val NOT-OP = new PrimOp -public val AND-OP = new PrimOp -public val OR-OP = new PrimOp -public val XOR-OP = new PrimOp -public val AND-REDUCE-OP = new PrimOp -public val OR-REDUCE-OP = new PrimOp -public val XOR-REDUCE-OP = new PrimOp -public val CONCAT-OP = new PrimOp -public val BITS-SELECT-OP = new PrimOp -public val HEAD-OP = new PrimOp -public val TAIL-OP = new PrimOp - -public definterface Expression -public defmulti type (e:Expression) -> Type - -public defstruct Ref <: Expression : - name: Symbol - type: Type with: (as-method => true) -public defstruct SubField <: Expression : - exp: Expression - name: Symbol - type: Type with: (as-method => true) -public defstruct SubIndex <: Expression : - exp: Expression - value: Int - type: Type with: (as-method => true) -public defstruct SubAccess <: Expression : - exp: Expression - index: Expression - type: Type with: (as-method => true) -public defstruct Mux <: Expression : - cond: Expression - tval: Expression - fval: Expression - type: Type with: (as-method => true) -public defstruct ValidIf <: Expression : - cond: Expression - value: Expression - type: Type with: (as-method => true) -public defstruct UIntValue <: Expression : - value: BigInt - width: Width -public defstruct SIntValue <: Expression : - value: BigInt - width: Width -public defstruct DoPrim <: Expression : - op: PrimOp - args: List<Expression> - consts: List<Int> - type: Type with: (as-method => true) - -public definterface Stmt -public defmulti info (s:Stmt) -> FileInfo - -public defstruct DefWire <: Stmt : ;LOW - info: FileInfo with: (as-method => true) - name: Symbol - type: Type -public defstruct DefRegister <: Stmt : - info: FileInfo with: (as-method => true) - name: Symbol - type: Type - clock: Expression - reset: Expression - init: Expression -public defstruct DefInstance <: Stmt : ;LOW - info: FileInfo with: (as-method => true) - name: Symbol - module: Symbol -public defstruct DefMemory <: Stmt : ;LOW - info: FileInfo with: (as-method => true) - name: Symbol - data-type: Type - depth: Int - write-latency: Int - read-latency: Int - readers: List<Symbol> - writers: List<Symbol> - readwriters: List<Symbol> -public defstruct DefNode <: Stmt : ;LOW - info: FileInfo with: (as-method => true) - name: Symbol - value: Expression -public defstruct DefPoison <: Stmt : ;LOW - info: FileInfo with: (as-method => true) - name: Symbol - type: Type -public defstruct Conditionally <: Stmt : - info: FileInfo with: (as-method => true) - pred: Expression - conseq: Stmt - alt: Stmt -public defstruct Begin <: Stmt : ;LOW - body: List<Stmt> -public defstruct BulkConnect <: Stmt : - info: FileInfo with: (as-method => true) - loc: Expression - exp: Expression -public defstruct Connect <: Stmt : ;LOW - info: FileInfo with: (as-method => true) - loc: Expression - exp: Expression -public defstruct IsInvalid <: Stmt : ;LOW - info: FileInfo with: (as-method => true) - exp: Expression -public defstruct Stop <: Stmt : ;LOW - info: FileInfo with: (as-method => true) - ret: Int - clk: Expression - en: Expression -public defstruct Print <: Stmt : ;LOW - info: FileInfo with: (as-method => true) - string: String - args: List<Expression> - clk: Expression - en: Expression -public defstruct Empty <: Stmt ;LOW - - -public definterface Type -public defstruct UIntType <: Type : - width: Width -public defstruct SIntType <: Type : - width: Width -public defstruct BundleType <: Type : - fields: List<Field> -public defstruct VectorType <: Type : - type: Type - size: Int -public defstruct ClockType <: Type -public defstruct UnknownType <: Type - -public defstruct Field : - name: Symbol - flip: Flip - type: Type - -public defstruct Port : - info: FileInfo - name: Symbol - direction: Direction - type: Type - -public definterface Module -public defmulti name (m:Module) -> Symbol -public defmulti ports (m:Module) -> List<Port> -public defmulti info (m:Module) -> FileInfo - -public defstruct InModule <: Module : - info: FileInfo with: (as-method => true) - name: Symbol with: (as-method => true) - ports: List<Port> with: (as-method => true) - body: Stmt - -public defstruct ExModule <: Module : - info: FileInfo with: (as-method => true) - name: Symbol with: (as-method => true) - ports: List<Port> with: (as-method => true) - -public defstruct Circuit : - info: FileInfo - modules: List<Module> - main: Symbol diff --git a/src/main/stanza/firrtl-lexer.stanza b/src/main/stanza/firrtl-lexer.stanza deleted file mode 100644 index 1d119d00..00000000 --- a/src/main/stanza/firrtl-lexer.stanza +++ /dev/null @@ -1,596 +0,0 @@ -;Copyright (c) 2014 - 2016 The Regents of the University of -;California (Regents). All Rights Reserved. Redistribution and use in -;source and binary forms, with or without modification, are permitted -;provided that the following conditions are met: -; * Redistributions of source code must retain the above -; copyright notice, this list of conditions and the following -; two paragraphs of disclaimer. -; * Redistributions in binary form must reproduce the above -; copyright notice, this list of conditions and the following -; two paragraphs of disclaimer in the documentation and/or other materials -; provided with the distribution. -; * Neither the name of the Regents nor the names of its contributors -; may be used to endorse or promote products derived from this -; software without specific prior written permission. -;IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, -;SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, -;ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF -;REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT -;LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -;A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF -;ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION -;TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR -;MODIFICATIONS. -defpackage firrtl/lexer : - import core - import core/stringeater - import verse - import bigint2 - -;=============== PUBLIC INTERFACE =========================== -public defn lex (text:String) -> List<Token> : - lex-all-forms(StringEater(text, "NOFILE")) - -public defn lex-file (filename:String) -> List<Token> : - println-all(["Reading " filename]) - val eater = StringEater(read-file(filename), filename) - lex-all-forms(eater) - -public defn lex-form (eater:StringEater) : - init-lexer(eater) - eat-lexeme() - while (EATER[0] != false) and not empty?(SCOPES) : - eat-lexeme() - val form = head(lex-all(group-all())) - throw(LexerExceptions(ERRORS)) when not empty?(ERRORS) - form - -public defn lex-all-forms (eater:StringEater) : - init-lexer(eater) - eat-all() - val grouped = group-all() - val form = lex-all(grouped) - throw(LexerExceptions(ERRORS)) when not empty?(ERRORS) - form - -;=============== TOKEN CLASSES ============================== -defstruct Indentation : - indent:Int -defmethod print (o:OutputStream, i:Indentation) : - print-all(o, ["[Indentation " indent(i) "]"]) - -defstruct OpenToken : - symbol:Symbol -defmethod print (o:OutputStream, t:OpenToken) : - print-all(o, ["OPEN[" symbol(t) "]"]) - -defstruct CloseToken : - symbol:Symbol -defmethod print (o:OutputStream, t:CloseToken) : - print-all(o, ["CLOSE[" symbol(t) "]"]) - -defstruct PuncToken : - symbol:Symbol -defmethod print (o:OutputStream, t:PuncToken) : - print-all(o, ["PUNC[" symbol(t) "]"]) - -;=============== LEXER STATE ================================ -var LEXEMES: Vector<Token> -var SCOPES: Vector<Symbol> -var ERRORS: Vector<LexerException> -var EATER: StringEater -var STAR?: True|False - -defn init-lexer (eater:StringEater) : - EATER = eater - LEXEMES = Vector<Token>() - SCOPES = Vector<Symbol>() - ERRORS = Vector<LexerException>() - STAR? = false - -;================= CHARACTER CLASSES ======================== -val CHAR-CLASSES = String(256, to-char(0)) -defn class? (c, bit:Int) -> True|False : - match(c) : - (c:Char) : - val mask = to-int(CHAR-CLASSES[to-int(c as Char)]) - bit-set?(mask, bit) - (c) : - false - -defn tag-class (class:String, bit:Int) : - val tag = 1 << bit - for c in class do : - val i = to-int(c) - val mask = to-int(CHAR-CLASSES[i]) - val c2 = to-char(mask | tag) - CHAR-CLASSES[i] = c2 - -val DIGIT-CHAR = 0 -val ALPHA-CHAR = 1 -val PUNC-CHAR = 2 -val OPEN-BRACE-CHAR = 3 -val CLOSE-BRACE-CHAR = 4 -val OPERATOR-CHAR = 5 -val SYMBOL-CHAR = 6 -val WHITESPACE-CHAR = 7 - -let : - val digits = "0123456789" - val letters = "abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZ" - tag-class(letters, ALPHA-CHAR) - tag-class("_?", ALPHA-CHAR) - tag-class(digits, DIGIT-CHAR) - tag-class("`", PUNC-CHAR) - tag-class(" ,", WHITESPACE-CHAR) - tag-class("([{<", OPEN-BRACE-CHAR) - tag-class(")]}>", CLOSE-BRACE-CHAR) - tag-class("~!@#$%^*+-=/", OPERATOR-CHAR) - tag-class("~!@#$%^*+-=/", SYMBOL-CHAR) - tag-class(".:<&|", OPERATOR-CHAR) - tag-class("_?", SYMBOL-CHAR) - tag-class(letters, SYMBOL-CHAR) - tag-class(digits, SYMBOL-CHAR) - -;================ LOW LEVEL PREDICATES ===================== -;Lexer Predicates -defn whitespace? (c) : class?(c, WHITESPACE-CHAR) -defn digit? (c) : class?(c, DIGIT-CHAR) -defn alpha? (c) : class?(c, ALPHA-CHAR) -defn punc? (c) : class?(c, PUNC-CHAR) -defn open-brace? (c) : class?(c, OPEN-BRACE-CHAR) -defn close-brace? (c) : class?(c, CLOSE-BRACE-CHAR) -defn number-char? (c) : digit?(c) or (c == '.') -defn symbol-char? (c) : class?(c, SYMBOL-CHAR) -defn operator-char? (c) : - if c == '>' : - empty?(SCOPES) or (peek(SCOPES) != `>) - else : - class?(c, OPERATOR-CHAR) - -;================ EATING FUNCTIONS ========================= -defn update-stack (info:FileInfo, c:Symbol) : - defn pop-stack () : - if empty?(SCOPES) : - throw(ExtraClosingToken(info, c)) - else if peek(SCOPES) != c : - throw(WrongClosingToken(info, peek(SCOPES), c)) - else : - pop(SCOPES) - - switch {c == _} : - `\|<| : add(SCOPES, `\|>|) - `\|[| : add(SCOPES, `\|]|) - `\|{| : add(SCOPES, `\|}|) - `\|(| : add(SCOPES, `\|)|) - `\|*<| : add(SCOPES, `\|>|) - `\|*[| : add(SCOPES, `\|]|) - `\|*{| : add(SCOPES, `\|}|) - `\|*(| : add(SCOPES, `\|)|) - `\|>| : pop-stack() - `\|]| : pop-stack() - `\|}| : pop-stack() - `\|)| : pop-stack() - -defn token-eaten (t:Token) : - ;Update Lexemes - add(LEXEMES, t) - - ;Update the stack - match(item(t)) : - (x:OpenToken) : update-stack(info(t), symbol(x)) - (x:CloseToken) : update-stack(info(t), symbol(x)) - (x) : false - - ;Update STAR? - STAR? = - match(item(t)) : - (x:CloseToken) : true - (x:Int|Float|Char|String) : true - (x:True|False) : true - (x:Symbol) : any?(alpha?, to-string(x)) - (x) : false - - true - -defn escape-char (c:Char) -> Char : - switch {c == _} : - 'n' : '\n' - '\\' : c - '"' : c - '\'' : c - '|' : c - else : throw(InvalidEscapeChar(info(EATER), c)) - -defn eat-escaped-chars () : - val buf = StringBuffer() - val end-char = EATER[0] - val end = loop(1) where : - defn* loop (i:Int) : - val c1 = EATER[i] - val c2 = EATER[i + 1] - if c1 == false : - false - else if c1 == end-char : - i + 1 - else if c1 == '\\' and c2 != false : - add(buf, escape-char(c2 as Char)) - loop(i + 2) - else : - add(buf, c1 as Char) - loop(i + 1) - if end != false : - eat(EATER, end as Int) - to-string(buf) - -defn eat-comment () -> True|False : - if EATER[0] == ';' : - while (EATER[0] != false and EATER[0] != '\n') : - eat(EATER) - true - -defn eat-string () : - val info = info(EATER) - if EATER[0] == '"' : - match(eat-escaped-chars()) : - (s:String) : token-eaten(Token(s, info)) - (s:False) : throw(UnclosedString(info)) - -defn eat-char () : - val info = info(EATER) - if EATER[0] == '\'' : - match(eat-escaped-chars()) : - (s:String) : - if length(s) == 1 : token-eaten(Token(s[0], info)) - else : throw(InvalidCharString(info)) - (s:False) : throw(UnclosedCharString(info)) - -defn eat-escaped-symbol () : - val info = info(EATER) - if EATER[0] == '\\' and EATER[1] == '|' : - eat(EATER) - match(eat-escaped-chars()) : - (s:String) : token-eaten(Token(to-symbol(s), info)) - (s:False) : throw(UnclosedSymbol(info)) - -defn symbol-end (start:Int) -> False|Int : - defn length (a?:True|False, i:Int) : - if symbol-char?(EATER[i]) : - length(a? or alpha?(EATER[i]), i + 1) - else if a? : - i - length(false, start) - -defn eat-symbol () : - match(symbol-end(0)) : - (len:Int) : - val info = info(EATER) - val str = eat(EATER, len) - switch {str == _} : - "true" : token-eaten(Token(true, info)) - "false" : token-eaten(Token(false, info)) - else : token-eaten(Token(to-symbol(str), info)) - (len:False) : - false - -defn eat-operator () : - val len = look-forward(0) where : - defn* look-forward (i:Int) : - if operator-char?(EATER[i]) : look-forward(i + 1) - else if alpha?(EATER[i]) : look-back(i - 1) - else : i - defn* look-back (i:Int) : - if symbol-char?(EATER[i]) : look-back(i - 1) - else : i + 1 - if len > 0 : - val info = info(EATER) - token-eaten(Token(to-symbol(eat(EATER, len)), info)) - -defn* eat-indent () : - val info = info(EATER) - val len = find({EATER[_] != ' '}, 0 to length(EATER) + 1) as Int - eat(EATER, len) - val indent = Token(Indentation(len), info) - if eat-comment() : - eat-indent() - else if EATER[0] == '\n' : - eat(EATER) - eat-indent() - else : - token-eaten(indent) - -defn eat-number () : - if digit?(EATER[0]) or - (EATER[0] == '-' and digit?(EATER[1])) : - - val info = info(EATER) - val end = find({not number-char?(EATER[_])}, 1 to length(EATER) + 1) as Int - val str = eat(EATER, end) - if contains?(str, '.') : - match(to-float(str)) : - (f:Float) : token-eaten(Token(f, info)) - (f:False) : throw(InvalidNumber(info)) - else : token-eaten(Token(to-int(str), info)) - ;else : token-eaten(Token(BigIntLit(str),info)) - ;else : - ;match(to-long(str)) : - ; (l:Long) : - ; if l < (to-long("2147483647") as Long) and l > (to-long("-2147483648") as Long) : token-eaten(Token(to-int(str), info)) - ; else : token-eaten(Token(l, info)) - ; (l:False) : token-eaten(Token(to-int(str), info)) - -defn eat-here-string () : - if EATER[0] == '\\' and EATER[1] == '<' : - val info = info(EATER) - eat(EATER) - val tag-len = - match(find({EATER[_] == '>'}, 0 to length(EATER))) : - (i:Int) : i + 1 - (n:False) : throw(InvalidTag(info)) - defn tag? (i:Int) : - for j in 0 to tag-len all? : - EATER[i + j] == EATER[j] - val str-len = - match(find(tag?, tag-len to length(EATER))) : - (i:Int) : i - tag-len - (n:False) : throw(NoEndTagFound(info)) - eat(EATER, tag-len) - val str = eat(EATER, str-len) - eat(EATER, tag-len) - token-eaten(Token(str, info)) - -defn eat-structural-token () : - val info = info(EATER) - if open-brace?(EATER[0]) : - token-eaten(Token(OpenToken(to-symbol(eat(EATER))), info)) - else if close-brace?(EATER[0]) : - token-eaten(Token(CloseToken(to-symbol(eat(EATER))), info)) - else if punc?(EATER[0]) : - token-eaten(Token(PuncToken(to-symbol(eat(EATER))), info)) - -defn eat-star-token () : - val info = info(EATER) - if open-brace?(EATER[0]) : - token-eaten(Token(OpenToken(symbol-join(["*" eat(EATER)])), info)) - -defn eat-capture () : - if (EATER[0] == '?') : - match(symbol-end(1)) : - (end:Int) : - val pinfo = info(EATER) - token-eaten(Token(PuncToken(to-symbol(eat(EATER))), pinfo)) - val info = info(EATER) - token-eaten(Token(to-symbol(eat(EATER, end - 1)), info)) - (end:False) : - false - -defn eat-lexeme! () : - val ate? = - eat-capture() or - eat-here-string() or - eat-escaped-symbol() or - eat-char() or - eat-string() or - eat-number() or - eat-symbol() or - eat-operator() or - eat-structural-token() - if ate? : - eat-star-token() when STAR? - else : throw(InvalidToken(info(EATER))) - -defn eat-whitespace () : - if whitespace?(EATER[0]) : - while whitespace?(EATER[0]) : - eat(EATER) - STAR? = false - -defn eat-lexeme () : - eat-whitespace() - if EATER[0] != false : - if eat-comment() : - eat-lexeme() - else if EATER[0] == '\n' : - eat(EATER) - eat-indent() - else : - eat-lexeme!() - -defn eat-all () : - while EATER[0] != false : - eat-lexeme() - -;================ GROUPING ================================== -val OPEN-PAREN = `\|(| -val STAR-PAREN = `\|*(| -val CLOSE-PAREN = `\|)| -val OPEN-BRACKET = `\|{| -val STAR-BRACKET = `\|*{| -val CLOSE-BRACKET = `\|}| -val OPEN-BRACE = `\|[| -val STAR-BRACE = `\|*[| -val CLOSE-BRACE = `\|]| -val STAR-ANGLE = `\|*<| -val CLOSE-ANGLE = `\|>| -val COLON = `: -val QUESTION = `? -val BACKTICK = `\|`| - -defn matching-end (s:Symbol) : - if s == OPEN-PAREN : CLOSE-PAREN - else if s == STAR-PAREN : CLOSE-PAREN - else if s == OPEN-BRACKET : CLOSE-BRACKET - else if s == STAR-BRACKET : CLOSE-BRACKET - else if s == OPEN-BRACE : CLOSE-BRACE - else if s == STAR-BRACE : CLOSE-BRACE - else if s == STAR-ANGLE : CLOSE-ANGLE - else : error("No matching end") - -var START-INFO = false -var TOKEN-STREAM : Vector<Token> -defn group-all () -> List : - TOKEN-STREAM = Vector<Token>(length(LEXEMES)) - while not empty?(LEXEMES) : - add(TOKEN-STREAM, pop(LEXEMES)) - group-rest(false) - -defn group-rest (end) -> List : - if empty?(TOKEN-STREAM) : - match(end) : - (end:Symbol) : - throw(NoClosingToken(START-INFO as FileInfo, end)) - (end) : - List() - else : - val x = peek(TOKEN-STREAM) - match(item(x)) : - (t:CloseToken) : - match(end) : - (end:Symbol) : - pop(TOKEN-STREAM) - List() - (end:Indentation) : - List() - (t:OpenToken) : - pop(TOKEN-STREAM) - val old-info = START-INFO - START-INFO = info(x) - val g = group-rest(matching-end(symbol(t))) - START-INFO = old-info - List(List(x, g), group-rest(end)) - (t:PuncToken) : - pop(TOKEN-STREAM) - List(x, group-rest(end)) - (s:Symbol) : - pop(TOKEN-STREAM) - if s == COLON : - match(item(peek(TOKEN-STREAM))) : - (i:Indentation) : - val y = pop(TOKEN-STREAM) - val g = group-rest(i) - List(x, List(y, g), group-rest(end)) - (t) : - List(x, group-rest(end)) - else : - List(x, group-rest(end)) - (i:Indentation) : - if (end typeof Indentation) and - (indent(i) < indent(end as Indentation)) : - List() - else : - pop(TOKEN-STREAM) - group-rest(end) - (t) : - pop(TOKEN-STREAM) - List(x, group-rest(end)) - -;============== ADDING SHORTCUTS ============================ -defn indentation? (x) : - unwrap-token(x) typeof Indentation -defn opentoken? (x, s:Symbol) : - match(unwrap-token(x)) : - (x:OpenToken) : symbol(x) == s - (x) : false -defn opentoken? (x, s:Streamable<Symbol>) : - match(unwrap-token(x)) : - (x:OpenToken) : contains?(s, symbol(x)) - (x) : false -defn punctoken? (x, s:Symbol) : - match(unwrap-token(x)) : - (x:PuncToken) : symbol(x) == s - (x) : false -defn startoken-pending? (xs:List) : - if not empty?(xs) : - match(head(xs)) : - (x:FullList) : opentoken?(head(x), [STAR-PAREN, STAR-BRACE, STAR-BRACKET, STAR-ANGLE]) - (x) : false - -defn lex-atom (x) -> ? : - match(x) : - (x:Token) : - map(lex-atom, x) - (x:FullList) : - if indentation?(head(x)) : lex-all(tail(x)) - else if opentoken?(head(x), OPEN-PAREN) : lex-all(tail(x)) - else if opentoken?(head(x), OPEN-BRACE) : List(`@tuple, lex-all(tail(x))) - else if opentoken?(head(x), OPEN-BRACKET) : List(`@afn, lex-all(tail(x))) - else if opentoken?(head(x), STAR-PAREN) : List(`@do, lex-all(tail(x))) - else if opentoken?(head(x), STAR-BRACE) : List(`@get, lex-all(tail(x))) - else if opentoken?(head(x), STAR-BRACKET) : List(`@do-afn, lex-all(tail(x))) - else if opentoken?(head(x), STAR-ANGLE) : List(`@of, lex-all(tail(x))) - else : error(string-join(["Invalid grouped form: " x])) - (x) : x - -defn lex-all (xs:List) -> List : - if empty?(xs) : - xs - else if punctoken?(head(xs), QUESTION) : - val capped = list(OpenToken(`\|(|), `@cap, xs[1]) - lex-all(List(capped, tailn(xs, 2))) - else if punctoken?(head(xs), BACKTICK) : - if empty?(tail(xs)) : - `(@quote) - else : - val rest = lex-all(tail(xs)) - List(list(`@quote, head(rest)), tail(rest)) - else : - List(lex-atom(head(xs)), lex-all(tail(xs))) - -;============== LEXER ERRORS ================================ -definterface LexerException <: Exception -defn LexerException (s:String) : - new LexerException : - defmethod print (o:OutputStream, this) : - print(o, s) - -defn LexerExceptions (xs:Streamable<LexerException>) : - LexerException(string-join(xs, "\n")) - -defn NoClosingToken (info:FileInfo, end:Symbol) : - LexerException $ string-join $ - [info ": No closing token found. Expecting " end "."] - -defn InvalidNumber (info:FileInfo) : - LexerException $ string-join $ - [info ": Invalid number."] - -defn InvalidToken (info:FileInfo) : - LexerException $ string-join $ - [info ": Invalid token."] - -defn InvalidEscapeChar (info:FileInfo, c:Char) : - LexerException $ string-join $ - [info ": Invalid escape character: " c "."] - -defn UnclosedString (info:FileInfo) : - LexerException $ string-join $ - [info ": Unclosed string. "] - -defn UnclosedCharString (info:FileInfo) : - LexerException $ string-join $ - [info ": Unclosed character. "] - -defn UnclosedSymbol (info:FileInfo) : - LexerException $ string-join $ - [info ": Unclosed symbol. "] - -defn InvalidCharString (info:FileInfo) : - LexerException $ string-join $ - [info ": Invalid character string. Must have length 1."] - -defn WrongClosingToken (info:FileInfo, expected:Symbol, actual:Symbol) : - LexerException $ string-join $ - [info ": Wrong closing parenthesis. Expecting " expected " but got " actual "."] - -defn ExtraClosingToken (info:FileInfo, c:Symbol) : - LexerException $ string-join $ - [info ": Extra closing token found: " c "."] - -defn InvalidTag (info:FileInfo) : - LexerException $ string-join $ - [info ": Invalid tag for here string."] - -defn NoEndTagFound (info:FileInfo) : - LexerException $ string-join $ - [info ": No ending tag found for here string."] diff --git a/src/main/stanza/firrtl-main.stanza b/src/main/stanza/firrtl-main.stanza deleted file mode 100644 index 362961af..00000000 --- a/src/main/stanza/firrtl-main.stanza +++ /dev/null @@ -1,57 +0,0 @@ -;Copyright (c) 2014 - 2016 The Regents of the University of -;California (Regents). All Rights Reserved. Redistribution and use in -;source and binary forms, with or without modification, are permitted -;provided that the following conditions are met: -; * Redistributions of source code must retain the above -; copyright notice, this list of conditions and the following -; two paragraphs of disclaimer. -; * Redistributions in binary form must reproduce the above -; copyright notice, this list of conditions and the following -; two paragraphs of disclaimer in the documentation and/or other materials -; provided with the distribution. -; * Neither the name of the Regents nor the names of its contributors -; may be used to endorse or promote products derived from this -; software without specific prior written permission. -;IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, -;SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, -;ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF -;REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT -;LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -;A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF -;ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION -;TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR -;MODIFICATIONS. -#include<"core/stringeater.stanza"> -#include<"core/macro-utils.stanza"> -#include<"compiler/stz-algorithms.stanza"> -#include<"compiler/stz-parser.stanza"> -#include<"compiler/stz-lexer.stanza"> -#include("firrtl-lexer.stanza") -#include("firrtl-ir.stanza") -#include("ir-utils.stanza") -#include("ir-parser.stanza") -#include("passes.stanza") -#include("primop.stanza") -#include("errors.stanza") -#include("symbolic-value.stanza") - -defpackage firrtl-main : - import core - import verse - import firrtl/parser - import firrtl/passes - import firrtl/lexer - import stz/parser - import firrtl/ir-utils - -defn main () : - val arg = commandline-arguments() - val args = split(arg,' ') - val lexed = lex-file(args[1]) - val c = parse-firrtl(lexed) - ;println(c) - run-passes(c,to-list(args[2])) - -main() - diff --git a/src/main/stanza/firrtl-test-main.stanza b/src/main/stanza/firrtl-test-main.stanza deleted file mode 100644 index 4fcc9dee..00000000 --- a/src/main/stanza/firrtl-test-main.stanza +++ /dev/null @@ -1,177 +0,0 @@ -;Copyright (c) 2014 - 2016 The Regents of the University of -;California (Regents). All Rights Reserved. Redistribution and use in -;source and binary forms, with or without modification, are permitted -;provided that the following conditions are met: -; * Redistributions of source code must retain the above -; copyright notice, this list of conditions and the following -; two paragraphs of disclaimer. -; * Redistributions in binary form must reproduce the above -; copyright notice, this list of conditions and the following -; two paragraphs of disclaimer in the documentation and/or other materials -; provided with the distribution. -; * Neither the name of the Regents nor the names of its contributors -; may be used to endorse or promote products derived from this -; software without specific prior written permission. -;IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, -;SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, -;ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF -;REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT -;LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -;A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF -;ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION -;TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR -;MODIFICATIONS. -#include<"core/stringeater.stanza"> -#include<"core/macro-utils.stanza"> -#include<"compiler/stz-algorithms.stanza"> -#include<"compiler/stz-parser.stanza"> -#include<"compiler/stz-lexer.stanza"> -#include("bigint2.stanza") -#include("firrtl-lexer.stanza") -#include("firrtl-ir.stanza") -#include("ir-utils.stanza") -#include("ir-parser.stanza") -#include("passes.stanza") -#include("chirrtl.stanza") -#include("primop.stanza") -#include("errors.stanza") -#include("compilers.stanza") -#include("firrtl.stanza") -;#include("flo.stanza") -;#include("verilog.stanza") -;#include("symbolic-value.stanza") - -;Custom Packages -;#include("custom-passes.stanza") -;#include("custom-compiler.stanza") - -defpackage firrtl-main : - import core - import verse - import firrtl/parser - import firrtl/passes - import firrtl/ir2 - import firrtl/lexer - import stz/parser - import firrtl/ir-utils - import firrtl/compiler - import firrtl/chirrtl - import firrtl/firrtl - ;Custom Packages - ;import firrtl/custom-passes - ;import firrtl/custom-compiler - -defn set-printvars! (p:List<Char>) : - if contains(p,'t') : PRINT-TYPES = true - if contains(p,'k') : PRINT-KINDS = true - if contains(p,'w') : PRINT-WIDTHS = true - if contains(p,'T') : PRINT-TWIDTHS = true - if contains(p,'g') : PRINT-GENDERS = true - if contains(p,'c') : PRINT-CIRCUITS = true - if contains(p,'d') : PRINT-DEBUG = true - if contains(p,'i') : PRINT-INFO = true - -defn get-passes (pass-names:List<String>) -> List<Pass> : - for n in pass-names map : - val p = for p in append(standard-passes,chirrtl-passes) find : - n == short-name(p) - if p == false : - error(to-string $ ["Unrecognized pass flag: " n]) - p as Pass - -defn main () : - val args = commandline-arguments() - var input = false - var output = false - var firms = Vector<String>() - var compiler = false - val pass-names = Vector<String>() - val pass-args = Vector<String>() - var printvars = "" - var last-s = "" - var backend = false - - val prev-out = CURRENT-OUTPUT-STREAM - CURRENT-OUTPUT-STREAM = STANDARD-ERROR - - - for (s in args, i in 0 to false) do : - if s == "-i" : last-s = s - else if s == "-o" : last-s = s - else if s == "-x" : last-s = s - else if s == "-X" : last-s = s - else if s == "-p" : last-s = s - else if s == "-s" : last-s = s - else if s == "-m" : last-s = s - else if s == "-b" : last-s = s - else : - if last-s == "-i" : input = args[i] - if last-s == "-o" : output = args[i] - if last-s == "-x" : add(pass-names,args[i]) - if last-s == "-X" : compiler = args[i] - if last-s == "-p" : printvars = to-string([printvars args[i]]) - if last-s == "-s" : add(pass-args,args[i]) - if last-s == "-m" : add(firms,args[i]) - if last-s == "-b" : backend = args[i] - - var with-output = - fn (f:()->False) : - val prev-stream = CURRENT-OUTPUT-STREAM - CURRENT-OUTPUT-STREAM = STANDARD-OUTPUT - f() - CURRENT-OUTPUT-STREAM = prev-stream - - if input == false : - error("No input file provided. Use -i flag.") - if output != false and output != "-": - with-output = - fn (f:()->False) : - val prev-stream = CURRENT-OUTPUT-STREAM - val out-stream = FileOutputStream(output as String) - CURRENT-OUTPUT-STREAM = out-stream - f() - CURRENT-OUTPUT-STREAM = prev-stream - close(out-stream) - - if compiler == false and backend == false and length(pass-names) == 0 : - error("Must specify a compiler or a backend. Use -X flag or -b flag.") - - val lexed = lex-file(input as String) - val circuit = parse-firrtl(lexed) - - val modules* = Vector<Module>() - for m in modules(circuit) do : - add(modules*,m) - - val included-c = - for m in firms map : - val lexed = lex-file(m as String) - parse-firrtl(lexed) - - for c in included-c do : - for m in modules(c) do : - add(modules*,m) - - val circuit* = Circuit(info(circuit),to-list(modules*),main(circuit)) - - set-printvars!(to-list(printvars)) - - if compiler == false : - var c*:Circuit = run-passes(circuit*,get-passes(to-list(pass-names))) - switch {_ == backend} : - "verilog" : run-backend(c*,LoToVerilog(with-output)) - "firrtl" : run-backend(c*,FIRRTL(with-output)) - else : error("Invalid backend flag!") - else : - switch {_ == compiler} : - ;"flo" : error("Flo backend not currently supported.") - ; run-passes(circuit*,StandardFlo(with-output)) - "verilog" : run-passes(circuit*,StandardVerilog(with-output)) - "firrtl" : run-passes(circuit*,StandardFIRRTL(with-output)) - "lofirrtl" : run-passes(circuit*,StandardLoFIRRTL(with-output)) - ;"verilute" : run-passes(circuit*,InstrumentedVerilog(with-output,to-list $ pass-args)) - else : error("Invalid compiler flag") - - CURRENT-OUTPUT-STREAM = prev-out -main() diff --git a/src/main/stanza/firrtl.stanza b/src/main/stanza/firrtl.stanza deleted file mode 100644 index f51a13a6..00000000 --- a/src/main/stanza/firrtl.stanza +++ /dev/null @@ -1,45 +0,0 @@ -;Copyright (c) 2014 - 2016 The Regents of the University of -;California (Regents). All Rights Reserved. Redistribution and use in -;source and binary forms, with or without modification, are permitted -;provided that the following conditions are met: -; * Redistributions of source code must retain the above -; copyright notice, this list of conditions and the following -; two paragraphs of disclaimer. -; * Redistributions in binary form must reproduce the above -; copyright notice, this list of conditions and the following -; two paragraphs of disclaimer in the documentation and/or other materials -; provided with the distribution. -; * Neither the name of the Regents nor the names of its contributors -; may be used to endorse or promote products derived from this -; software without specific prior written permission. -;IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, -;SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, -;ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF -;REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT -;LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -;A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF -;ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION -;TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR -;MODIFICATIONS. -defpackage firrtl/firrtl : - import core - import verse - import firrtl/ir-utils - import firrtl/ir2 - - -;============ FIRRTL ============== - -public defstruct FIRRTL <: Pass : - with-output: (() -> False) -> False -public defmethod pass (b:FIRRTL) -> (Circuit -> Circuit) : emit-firrtl{with-output(b),_} -public defmethod name (b:FIRRTL) -> String : "To FIRRTL" -public defmethod short-name (b:FIRRTL) -> String : "To FIRRTL" - -;============ Utilz ============= - -public defn emit-firrtl (with-output:(() -> False) -> False, c:Circuit) : - with-output $ fn () : - print(c) - c diff --git a/src/main/stanza/flo.stanza b/src/main/stanza/flo.stanza deleted file mode 100644 index ad04bb23..00000000 --- a/src/main/stanza/flo.stanza +++ /dev/null @@ -1,228 +0,0 @@ -;Copyright (c) 2014 - 2016 The Regents of the University of -;California (Regents). All Rights Reserved. Redistribution and use in -;source and binary forms, with or without modification, are permitted -;provided that the following conditions are met: -; * Redistributions of source code must retain the above -; copyright notice, this list of conditions and the following -; two paragraphs of disclaimer. -; * Redistributions in binary form must reproduce the above -; copyright notice, this list of conditions and the following -; two paragraphs of disclaimer in the documentation and/or other materials -; provided with the distribution. -; * Neither the name of the Regents nor the names of its contributors -; may be used to endorse or promote products derived from this -; software without specific prior written permission. -;IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, -;SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, -;ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF -;REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT -;LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -;A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF -;ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION -;TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR -;MODIFICATIONS. -defpackage firrtl/flo : - import core - import verse - import firrtl/ir-utils - import firrtl/ir2 - import firrtl/passes - import bigint2 - -;============= Flo Backend ================ - -public defstruct Flo <: Pass : - with-output: (() -> False) -> False -public defmethod pass (b:Flo) -> (Circuit -> Circuit) : emit-flo{with-output(b),_} -public defmethod name (b:Flo) -> String : "To Flo" - -definterface FloKind -defstruct FRegKind <: FloKind -defstruct FWritePortKind <: FloKind : - mem: Expression - index: Expression -defstruct FOutputPortKind <: FloKind - -defn is-sint? (arg:Expression) -> True|False : type(arg) typeof SIntType -defn type (s:DefAccessor) -> Type : type(type(source(s)) as VectorType) - -defn flo-op-name (op:PrimOp, args:List<Expression>) -> String : - switch {op == _ } : - ADD-OP : "add" - ADD-WRAP-OP : "add" - SUB-OP : "sub" - SUB-WRAP-OP : "sub" - MUL-OP : "mul" ;; todo: signed version - DIV-OP : "div" ;; todo: signed version - REM-OP : "mod" ;; todo: signed version - QUO-OP : "div" ;; todo: signed version - REM-OP : "mod" ;; todo: signed version - LESS-OP : "lt" ;; todo: signed version - LESS-EQ-OP : "lte" ;; todo: swap args - GREATER-OP : "lt" ;; todo: swap args - GREATER-EQ-OP : "lte" ;; todo: signed version - NEQUIV-OP : "neq" - EQUIV-OP : "eq" - NEQUAL-OP : "neq" - EQUAL-OP : "eq" - MUX-OP : "mux" - NEG-OP : "neg" - AS-UINT-OP : "mov" - AS-SINT-OP : "mov" - SHIFT-LEFT-OP : "lsh" - SHIFT-RIGHT-OP : if is-sint?(args[0]): "arsh" else: "rsh" - DYN-SHIFT-LEFT-OP : "lsh" - DYN-SHIFT-RIGHT-OP : if is-sint?(args[0]): "arsh" else: "rsh" - PAD-OP : if is-sint?(args[0]): "arsh" else: "rsh" - CONVERT-OP : if is-sint?(args[0]): "arsh" else: "rsh" - BIT-AND-OP : "and" - BIT-NOT-OP : "not" - BIT-OR-OP : "or" - BIT-XOR-OP : "xor" - CONCAT-OP : "cat" - BIT-SELECT-OP : "rsh" - BITS-SELECT-OP : "rsh" - BIT-XOR-REDUCE-OP : "xorr" - else : - error $ string-join $ ["Unable to print Primop: " op] - -defn sane-width (wd:Width) -> Int|Long : - match(wd) : - (w:LongWidth) : max(to-long(1), width(w)) - (w) : error(string-join(["Unknown width: " w])) - -defn prim-width (type:Type) -> Int|Long : - match(type) : - (t:UIntType) : sane-width(width(t)) - (t:SIntType) : sane-width(width(t)) - (t:ClockType) : 1 - (t) : error("Bad prim width type") - -defn emit-all (es:Streamable, top:Symbol) : - for e in es do : - match(e) : - (ex:Expression) : emit!(ex,top) - (ex:String) : print(ex) - (ex:Symbol) : print(ex) - ;; (ex:Int) : print-all([ex "'" sizeof(ex)]) - (ex:Int) : print(ex) - (ex) : print(ex) - -defn emit! (e:Expression,top:Symbol) : - defn greater-op? (op: PrimOp) -> True|False : - contains?([GREATER-OP], op) - defn greater-eq-op? (op: PrimOp) -> True|False : - contains?([GREATER-EQ-OP], op) - defn less-eq-op? (op: PrimOp) -> True|False : - contains?([LESS-EQ-OP], op) - defn less-op? (op: PrimOp) -> True|False : - contains?([LESS-OP], op) - defn cmp-op? (op: PrimOp) -> True|False : - greater-op?(op) or greater-eq-op?(op) or less-op?(op) or less-eq-op?(op) or - contains?([EQUAL-OP NEQUAL-OP] op) - match(e) : - (e:Ref) : emit-all([top "::" name(e)], top) - (e:UIntValue) : emit-all([value(e) "'" sane-width(width(e))], top) - (e:SIntValue) : emit-all([value(e) "'" sane-width(width(e))], top) - (e:Subfield) : emit-all([exp(e) "/" name(e)], top) - (e:Index) : emit-all([exp(e) "/" value(e)], top) - (e:DoPrim) : - if cmp-op?(op(e)) : - emit-all([flo-op-name(op(e), args(e)) "'" prim-width(type(args(e)[0]))], top) - if greater-op?(op(e)) or greater-eq-op?(op(e)) : - emit-all([" " args(e)[1] " " args(e)[0]], top) - else : - emit-all([" " args(e)[0] " " args(e)[1]], top) - else if op(e) == BIT-SELECT-OP : - emit-all([flo-op-name(op(e), args(e)) "'1 " args(e)[0] " " consts(e)[0]], top) - else if op(e) == BITS-SELECT-OP : - val w = consts(e)[0] - consts(e)[1] + 1 - emit-all([flo-op-name(op(e), args(e)) "'" w " " args(e)[0] " " consts(e)[1]], top) - else if op(e) == CONCAT-OP : - val w = prim-width(type(args(e)[1])) - emit-all([flo-op-name(op(e), args(e)) "'" w " " args(e)[0] " " args(e)[1]], top) - else if op(e) == PAD-OP or op(e) == CONVERT-OP : - emit-all([flo-op-name(op(e), args(e)) "'" prim-width(type(e)) " " args(e)[0] " 0"], top) - else : - emit-all([flo-op-name(op(e), args(e)) "'" prim-width(type(e))], top) - for arg in args(e) do : - print(" ") - emit!(arg, top) - for const in consts(e) do : - print-all([" " const "'" req-num-bits(const)]) - (e) : error("SHOULDN'T EMIT THIS") ;; print-all(["EMIT(" e ")"]) - ;(e) : emit-all(["mov'" prim-width(type(e)) " " e], top) ;TODO, not sure which one is right - -defn maybe-mov (e:Expression) -> String : - val need-mov? = match(e) : - (e:Ref) : true - (e:UIntValue) : true - (e:SIntValue) : true - (e:Subfield) : true - (e:Index) : true - (e) : false - if need-mov?: "mov " else: "" - -defn emit-s (s:Stmt, flokinds:HashTable<Symbol,FloKind>, top:Symbol,sh:HashTable<Symbol,Int>) : - defn emit-connect (s:Connect, en:Expression) : - match(loc(s)) : - (r:Ref) : - val n = name(r) - if key?(flokinds,n) : - match(flokinds[n]) : - (k:FRegKind) : - emit-all(["reg'" prim-width(type(r)) " " en " " exp(s)], top) - (k:FWritePortKind) : - emit-all([top "::" n " = wr'" prim-width(type(r)) " " en " " mem(k) " " index(k) " " exp(s) "\n"], top) - (k:FOutputPortKind) : - emit-all([top "::" n " = out'" prim-width(type(r)) " " exp(s) "\n"], top) - (k) : error("Shouldn't be here") - else : - emit-all([top "::" n " = " maybe-mov(exp(s)) exp(s) "\n"], top) - (o) : - println-all(["CONNEcT LOC " loc(s)]) - error("Unknown Connect") - match(s) : - (s:DefWire) : "" - (s:DefPoison) : "" - (s:DefInstance) : error("Shouldn't be here") - (e:DefAccessor) : - if acc-dir == READ : - emit-all(["rd'" prim-width(type(e)) " " "1" " " source(e) " " index(e)], top) - (s:DefMemory) : - val vtype = type(s) as VectorType - emit-all([top "::" name(s) " = mem'" prim-width(type(vtype)) " " size(vtype) "\n"], top) - (s:DefNode) : - emit-all([top "::" name(s) " = " maybe-mov(value(s)) value(s) "\n"], top) - (s:Begin) : do(emit-s{_, flokinds, top,sh}, body(s)) - (s:Connect) : emit-connect(s,UIntValue(BigIntLit("1"),LongWidth(1))) - (s:Conditionally) : emit-connect(conseq(s) as Connect,pred(s)) - (s) : s - -defn emit-module (m:InModule,sh:HashTable<Symbol,Int>) : - val flokinds = HashTable<Symbol,FloKind>(symbol-hash) - defn build-table (s:Stmt) -> False : - do(build-table,s) - match(s) : - (s:DefRegister) : flokinds[name(s)] = FRegKind() - (s:DefAccessor) : - switch {_ == acc-dir(s)} : - WRITE : flokinds[name(s)] = FWritePortKind(source(s),index(s)) - else : false - (s) : false - - for port in ports(m) do : - if name(port) ==`reset : - emit-all([name(m) "::" name(port) " = rst'1\n"], name(m)) - else : switch {_ == direction(port)} : - INPUT : print-all([name(m) "::" name(port) " = " "in'" prim-width(type(port)) "\n"]) - OUTPUT : flokinds[name(port)] = FOutputPortKind() - emit-s(body(m), flokinds, name(m),sh) - -public defn emit-flo (with-output:(() -> False) -> False, c:Circuit) : - with-output $ { - emit-module(modules(c)[0] as InModule,get-sym-hash(modules(c)[0] as InModule)) - false - } - c diff --git a/src/main/stanza/ir-parser.stanza b/src/main/stanza/ir-parser.stanza deleted file mode 100644 index 6bbfa432..00000000 --- a/src/main/stanza/ir-parser.stanza +++ /dev/null @@ -1,409 +0,0 @@ -;Copyright (c) 2014 - 2016 The Regents of the University of -;California (Regents). All Rights Reserved. Redistribution and use in -;source and binary forms, with or without modification, are permitted -;provided that the following conditions are met: -; * Redistributions of source code must retain the above -; copyright notice, this list of conditions and the following -; two paragraphs of disclaimer. -; * Redistributions in binary form must reproduce the above -; copyright notice, this list of conditions and the following -; two paragraphs of disclaimer in the documentation and/or other materials -; provided with the distribution. -; * Neither the name of the Regents nor the names of its contributors -; may be used to endorse or promote products derived from this -; software without specific prior written permission. -;IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, -;SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, -;ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF -;REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT -;LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -;A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF -;ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION -;TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR -;MODIFICATIONS. -defpackage firrtl/parser : - import core - import verse - import firrtl/ir2 - import stz/parser - import firrtl/lexer - import bigint2 - import firrtl/ir-utils - import firrtl/chirrtl - -;======= Convenience Types =========== -definterface MStat -defstruct Reader <: MStat : - value: Symbol -defstruct Writer <: MStat : - value: Symbol -defstruct ReadWriter <: MStat : - value: Symbol -defstruct ReadLatency <: MStat : - value: Int -defstruct WriteLatency <: MStat : - value: Int -defstruct DataType <: MStat : - value: Type -defstruct Depth <: MStat : - value: Int -;======= Convenience Functions ======== -defn first-info? (form) -> FileInfo|False : - match(form) : - (form:Token) : info(form) - (form:List) : search(first-info?, form) - (form) : false - -defn first-info (form:List) : - match(first-info?(form)) : - (i:FileInfo) : i - (f:False) : FileInfo() - -defn FPE (form, x) : - throw $ new Exception : - defmethod print (o:OutputStream, this) : - print(o, "[~] FIRRTL Parsing Error: ~" << [first-info(form), x]) - -defn* apply-suffix-ops (x, fs:List) : - if empty?(fs) : x - else : apply-suffix-ops(head(fs)(x), tail(fs)) - -defn parse-stmts (forms:List) : - val cs = Vector<Stmt>() - defn* loop (forms:List) : - match-syntax(forms) : - () : to-list(cs) - (?s:#stmt ?rest ...) : (add(cs, s), loop(rest)) - (?rest ...) : FPE(rest, "Expected a statement here.") - loop(forms) - -;======== Parser Utilities ============== -defn atom? (x) : unwrap-token(x) not-typeof List - -defn primop (x:Symbol) : get?(OPERATORS, x, false) -val OPERATORS = HashTable<Symbol, PrimOp>(symbol-hash) -OPERATORS[`add] = ADD-OP -OPERATORS[`sub] = SUB-OP -OPERATORS[`mul] = MUL-OP -OPERATORS[`div] = DIV-OP -OPERATORS[`rem] = REM-OP -OPERATORS[`lt] = LESS-OP -OPERATORS[`leq] = LESS-EQ-OP -OPERATORS[`gt] = GREATER-OP -OPERATORS[`geq] = GREATER-EQ-OP -OPERATORS[`eq] = EQUAL-OP -OPERATORS[`neq] = NEQUAL-OP -OPERATORS[`pad] = PAD-OP -OPERATORS[`neg] = NEG-OP -OPERATORS[`asUInt] = AS-UINT-OP -OPERATORS[`asSInt] = AS-SINT-OP -OPERATORS[`asClock] = AS-CLOCK-OP -OPERATORS[`shl] = SHIFT-LEFT-OP -OPERATORS[`shr] = SHIFT-RIGHT-OP -OPERATORS[`dshl] = DYN-SHIFT-LEFT-OP -OPERATORS[`dshr] = DYN-SHIFT-RIGHT-OP -OPERATORS[`cvt] = CONVERT-OP -OPERATORS[`neg] = NEG-OP -OPERATORS[`not] = NOT-OP -OPERATORS[`and] = AND-OP -OPERATORS[`or] = OR-OP -OPERATORS[`xor] = XOR-OP -OPERATORS[`andr] = AND-REDUCE-OP -OPERATORS[`orr] = OR-REDUCE-OP -OPERATORS[`xorr] = XOR-REDUCE-OP -OPERATORS[`cat] = CONCAT-OP -OPERATORS[`bits] = BITS-SELECT-OP -OPERATORS[`head] = HEAD-OP -OPERATORS[`tail] = TAIL-OP - -;======== Parser Rules ================== -defsyntax firrtl : - ;Useful Atoms - defrule atoms : - ;Unconditionally parse next form as identifier. - id = (?x) when atom?(x) : - match(unwrap-token(x)) : - (x:Symbol) : x - (x) : FPE(form, "Expected an identifier here. Got ~ instead." << [x]) - - ;Parses next form if integer literal - int = (?x) when unwrap-token(x) typeof Int : - unwrap-token(x) - - string = (?x) when unwrap-token(x) typeof String : - unwrap-token(x) - - ;Parses next form if long literal - intorlong = (?x) when unwrap-token(x) typeof Int|Long : - unwrap-token(x) - - ;Parses next form if symbol - sym = (?x) when unwrap-token(x) typeof Symbol : - unwrap-token(x) - - ;Error Handling Productions - defrule : - ;Error if not an identifier - id! = (?x:#id) : x - id! != () : FPE(form, "Expected an identifier here.") - - ;Error if not => - =>! = (=>) : (`=>) - =>! != () : FPE(form, "Expected => here.") - - ;Error if not a colon - :! = (:) : (`:) - :! != () : FPE(form, "Expected a colon here.") - - ;Error if not 'of' keyword - of! = (of) : `of - of! != () : FPE(form, "Expected the 'of' keyword here.") - - ;Error if not a = - =! = (=) : `= - =! != () : FPE(form, "Expected a '=' here.") - - ;Error if not a single integer - int$ = (?i:#int ?rest ...) when empty?(rest) : i - int$ != () : FPE(form, "Expected a single integer literal here.") - - ;Error if not an integer - int! = (?i:#int) : i - int! != () : FPE(form, "Expected an integer literal here.") - - ;Error if not a single long integer - long$ = (?i:#intorlong ?rest ...) when empty?(rest) : - match(i) : - (i:Long) : i - (i) : to-long(i) - long$ != () : FPE(form, "Expected a single long integer literal here.") - - ;Error if not a single width - width$ = (?w:#width ?rest ...) when empty?(rest) : w - width$ != () : FPE(form, "Expected a single width specifier here.") - - ;Error if not a type - type! = (?t:#type) : t - type! != () : FPE(form, "Expected a type here.") - - ;Error if not a vec type - vectype! = (?t:#type!) : - FPE(form, "Expected a vector type here.") when t not-typeof VectorType - t - - ;Error if not an expression - exp! = (?e:#exp) : e - exp! != () : FPE(form, "Expected an expression here.") - - ;Error if not a single expression - exp$ = (?e:#exp ?rest ...) when empty?(rest) : e - exp$ != () : FPE(form, "Expected a single expression here.") - - ;Error if not a stmt - stmt! = (?s:#stmt) : s - stmt! != () : FPE(form, "Expected a statement here.") - - ;Error if not a reference expression - ref! = (?e:#exp!) : - FPE(form, "Expected a reference expression here.") when e not-typeof Ref - e - - ;Main Circuit Production - defrule circuit : - circuit = (circuit ?name:#id! #:! (?ms:#module ... ?rest ...)) : - if not empty?(rest) : - FPE(rest, "Expected a module declaration here.") - Circuit(first-info(form),ms, name) - circuit != (circuit) : - FPE(form, "Invalid syntax for circuit definition.") - - ;Main Module Production - defrule module : - ;module = (module ?name:#id! #:! (?ps:#port ... ?rest ...)) : - ; InModule(first-info(form), name, ps, Begin(parse-stmts(rest))) - module = (module ?name:#id! #:! (?ps:#port ... ?cs:#stmt ... ?rest ...)) : - if not empty?(rest) : - FPE(rest, "Expected a statement here.") - InModule(first-info(form),name, ps, Begin(cs)) - module = (extmodule ?name:#id! #:! (?ps:#port ... ?rest ...)) : - if not empty?(rest) : - FPE(rest, "Expected a port here.") - ExModule(first-info(form),name, ps) - module != (module) : - FPE(form, "Invalid syntax for module definition.") - module != (exmodule) : - FPE(form, "Invalid syntax for exmodule definition.") - - defrule port : - port = (input ?name:#id! #:! ?type:#type!) : Port(first-info(form),name, INPUT, type) - port = (output ?name:#id! #:! ?type:#type!) : Port(first-info(form),name, OUTPUT, type) - - ;Main Type Productions - defrule type : - inttype = (UInt<?w:#width$>) : UIntType(w) - inttype = (UInt) : UIntType(UnknownWidth()) - inttype = (SInt<?w:#width$>) : SIntType(w) - inttype = (SInt) : SIntType(UnknownWidth()) - - clktype = (Clock) : ClockType() - - type = (?t:#typeterm ?ops:#typeop ...) : apply-suffix-ops(t, ops) - type = (?t:#clktype) : t - typeop = ((@get ?size:#int$)) : (fn (t) : VectorType(t, size)) - - typeterm = (?t:#inttype) : t - typeterm = ({?fs:#field ... ?rest ...}) : - if not empty?(rest) : - FPE(rest, "Expected a bundle field declaration here.") - BundleType(fs) - - defrule field : - field = (flip ?name:#id! #:! ?type:#type!) : Field(name, REVERSE, type) - field = (?name:#id #:! ?type:#type!) : Field(name, DEFAULT, type) - - defrule width : - width = (?x:#int) : IntWidth(x) - width = (?) : UnknownWidth() - - ;Main Statement Productions - defrule mstat : - mstat = (reader #=>! ?name:#id!) : Reader(name) - mstat = (writer #=>! ?name:#id!) : Writer(name) - mstat = (readwriter #=>! ?name:#id!) : ReadWriter(name) - mstat = (read-latency #=>! ?i:#int!) : ReadLatency(i) - mstat = (write-latency #=>! ?i:#int!) : WriteLatency(i) - mstat = (data-type #=>! ?t:#type!) : DataType(t) - mstat = (depth #=>! ?i:#int!) : Depth(i) - defrule statements : - stmt = (skip) : Empty() - stmt = (wire ?name:#id! #:! ?t:#type!) : DefWire(first-info(form),name, t) - stmt = (reg ?name:#id! #:! ?t:#type! ?clk:#exp! with #:! ( reset => (?reset:#exp! ?init:#exp!))) : DefRegister(first-info(form),name,t,clk,reset,init) - stmt = (reg ?name:#id! #:! ?t:#type! ?clk:#exp!) : DefRegister(first-info(form),name,t,clk,zero,Ref(name,UnknownType())) - stmt = (cmem ?name:#id! #:! ?t:#vectype! ) : CDefMemory(first-info(form),name,type(t),size(t),false) - stmt = (smem ?name:#id! #:! ?t:#vectype! ) : CDefMemory(first-info(form),name,type(t),size(t),true) - - stmt = (read mport ?name:#id! #=! ?mem:#id! (@get ?index:#exp!) ?clk:#exp!) : - CDefMPort(first-info(form),name,UnknownType(),mem,list(index,clk),MRead) - stmt = (write mport ?name:#id! #=! ?mem:#id! (@get ?index:#exp!) ?clk:#exp!) : - CDefMPort(first-info(form),name,UnknownType(),mem,list(index,clk),MWrite) - stmt = (rdwr mport ?name:#id! #=! ?mem:#id! (@get ?index:#exp!) ?clk:#exp!) : - CDefMPort(first-info(form),name,UnknownType(),mem,list(index,clk),MReadWrite) - stmt = (infer mport ?name:#id! #=! ?mem:#id! (@get ?index:#exp!) ?clk:#exp!) : - CDefMPort(first-info(form),name,UnknownType(),mem,list(index,clk),MInfer) - - stmt = (mem ?name:#id! #:! (?ms:#mstat ...)) : - defn grab (f:MStat -> True|False) : - map(value,to-list(filter(f,ms))) as List - defn grab1 (f:MStat -> True|False,s:String) : - val ls = grab(f) - if length(ls) != 1 : FPE(form,"Must declare one ~." << [s]) - head(ls) - val readers = grab({_ typeof Reader}) - val writers = grab({_ typeof Writer}) - val readwriters = grab({_ typeof ReadWriter}) - val write-latency = grab1({_ typeof WriteLatency},"write-latency") - val read-latency = grab1({_ typeof ReadLatency},"read-latency") - val depth = grab1({_ typeof Depth},"depth") - val dt = grab1({_ typeof DataType},"data type") - DefMemory(first-info(form),name,dt,depth,write-latency,read-latency,readers,writers,readwriters) - stmt = (inst ?name:#id! #of! ?m:#id!) : DefInstance(first-info(form),name,m) - stmt = (node ?name:#id! #=! ?e:#exp!) : DefNode(first-info(form),name,e) - stmt = (poison ?name:#id! #:! ?t:#type!) : DefPoison(first-info(form),name, t) - stmt = (stop(?clk:#exp, ?en:#exp, ?ret:#int)) : Stop(first-info(form),ret,clk,en) - stmt = (printf(?clk:#exp ?en:#exp ?str:#string ?es:#exp ...)) : Print(first-info(form),str,es,clk,en) - stmt = (?s:#stmt/when) : s - - stmt = (?x:#exp <= ?y:#exp!) : Connect(first-info(form),x, y) ;> - stmt = (?x:#exp <- ?y:#exp!) : BulkConnect(first-info(form),x, y);> - stmt = (?x:#exp is invalid) : IsInvalid(first-info(form),x) - - ;stmt = ((?s:#stmt ?rest ...)) : - ; Begin(List(s, parse-stmts(rest))) - stmt = ((?s:#stmt ?ss:#stmt ... ?rest ...)) : - if not empty?(rest) : - FPE(rest, "Expected a statement here.") - Begin(List(s, ss)) - stmt = (()) : - Begin(List()) - - defrule stmt/when : - stmt/when = (when ?pred:#exp! #:! ?conseq:#stmt! else ?alt:#stmt/when) : - Conditionally(first-info(form),pred, conseq, alt) - stmt/when = (when ?pred:#exp! #:! ?conseq:#stmt! else #:! ?alt:#stmt!) : - Conditionally(first-info(form),pred, conseq, alt) - stmt/when = (when ?pred:#exp! #:! ?conseq:#stmt!) : - Conditionally(first-info(form),pred, conseq, Empty()) - - ;Main Expressions - defrule exp : - ;Suffix Operators - exp = (?x:#expterm ?ops:#expop ...) : apply-suffix-ops(x, ops) - expop = ((@get ?f:#int)) : (fn (x) : SubIndex(x, f, UnknownType())) - expop = ((@get ?f:#exp!)) : (fn (x) : SubAccess(x, f, UnknownType())) - expop = (. ?f:#id!) : (fn (x) : SubField(x, f, UnknownType())) - - ;Prefix Operators - expterm = (?t:#inttype(?v:#string)) : - val b = BigIntLit(v as String) - match(t) : - (t:UIntType) : - match(width(t)) : - (w:IntWidth) : - if to-long(req-num-bits(b)) > width(w) : - FPE(form, "Width too small for UIntValue.") - if width(w) == to-long(0) : println("is zero at") - UIntValue(b, w) - (w) : - ;UIntValue(b, w) - val num-bits = req-num-bits(b) - UIntValue(b,IntWidth(max(1,num-bits))) - (t:SIntType) : - match(width(t)) : - (w:IntWidth) : - if to-long(req-num-bits(b)) > width(w) : - FPE(form, "Width too small for SIntValue.") - SIntValue(b, w) - (w) : - SIntValue(b, w) - - expterm = (?t:#inttype(?v:#int$)) : - match(t) : - (t:UIntType) : - if (v as Int) < 0 : - FPE(form, "UIntValue cannot be negative.") - match(width(t)) : - (w:IntWidth) : - UIntValue(BigIntLit(v as Int,to-int(width(w)) + 1),w) - (w) : - val num-bits = req-num-bits(v as Int) - UIntValue(BigIntLit(v as Int,num-bits), IntWidth(max(1,num-bits - 1))) - (t:SIntType) : - match(width(t)) : - (w:IntWidth) : - SIntValue(BigIntLit(v as Int,to-int(width(w))),w) - (w) : - val num-bits = req-num-bits(v as Int) - SIntValue(BigIntLit(v as Int,num-bits), IntWidth(num-bits)) - - expterm = (mux(?cond:#exp ?tval:#exp ?fval:#exp)) : - Mux(cond,tval,fval,UnknownType()) - expterm = (validif(?cond:#exp ?value:#exp)) : - ValidIf(cond,value,UnknownType()) - expterm = (?op:#sym(?es:#exp ... ?ints:#int ... ?rest ...)) : - if not empty?(rest) : - FPE(rest, "Illegal operands to primitive operator.") - match(primop(op)) : - (p:PrimOp) : DoPrim(p, es, ints, UnknownType()) - (p:False) : FPE(form, "Unrecognized primitive operator '~'." << [op]) - expterm = (?op:#sym) : - Ref(op, UnknownType()) - -public defn parse-firrtl (forms:List) : - with-syntax(firrtl) : - match-syntax(forms) : - (?c:#circuit) : c - (_ ...) : FPE(form, "Invalid firrtl circuit.") - -public defn parse-firrtl-file (filename:String) : - parse-firrtl(lex-file(filename)) diff --git a/src/main/stanza/ir-utils.stanza b/src/main/stanza/ir-utils.stanza deleted file mode 100644 index a96d7503..00000000 --- a/src/main/stanza/ir-utils.stanza +++ /dev/null @@ -1,981 +0,0 @@ -;Copyright (c) 2014 - 2016 The Regents of the University of -;California (Regents). All Rights Reserved. Redistribution and use in -;source and binary forms, with or without modification, are permitted -;provided that the following conditions are met: -; * Redistributions of source code must retain the above -; copyright notice, this list of conditions and the following -; two paragraphs of disclaimer. -; * Redistributions in binary form must reproduce the above -; copyright notice, this list of conditions and the following -; two paragraphs of disclaimer in the documentation and/or other materials -; provided with the distribution. -; * Neither the name of the Regents nor the names of its contributors -; may be used to endorse or promote products derived from this -; software without specific prior written permission. -;IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, -;SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, -;ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF -;REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT -;LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -;A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF -;ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION -;TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR -;MODIFICATIONS. -defpackage firrtl/ir-utils : - import core - import verse - import firrtl/ir2 - import bigint2 - -;============== DEBUG STUFF ============================= - -public defmulti print-debug (o:OutputStream, e:Expression|Stmt|Type|Port|Field|Module|Circuit) -> False -public defmethod print-debug (o:OutputStream, e:Expression|Stmt|Type|Port|Field|Module|Circuit) -> False : false -public defmulti turn-off-debug (x:False) -> False -;public defmethod turn-off-debug (x:False) : false -public defmulti turn-on-debug (x:False) -;public defmethod turn-on-debug (x:False) : false - -;============== GENSYM STUFF ====================== - -defn generated? (s:String) -> False|Int : - for i in 1 to length(s) - 1 find : - val sub = substring(s,i + 1) - s[i] == '_' and digits?(sub) and s[i - 1] != '_' -defn digits? (s:String) -> True|False : - val digits = "0123456789" - var yes = true - for c in s do : - if not contains?(digits,c) : yes = false - yes - -val gen-names = HashTable<Symbol,Int>(symbol-hash) -public defn firrtl-gensym (s:Symbol) -> Symbol : - firrtl-gensym(s,HashTable<Symbol,Int>(symbol-hash)) -public defn firrtl-gensym (sym-hash:HashTable<Symbol,Int>) -> Symbol : - firrtl-gensym(`gen,sym-hash) -public defn firrtl-gensym (s:Symbol,sym-hash:HashTable<Symbol,Int>) -> Symbol : - defn get-name (s:Symbol) -> Symbol : - if key?(sym-hash,s) : - val num = sym-hash[s] + 1 - sym-hash[s] = num - symbol-join([s delin num]) - else : - sym-hash[s] = 0 - symbol-join([s delin 0]) - val s* = to-string(s) - val i* = generated?(s*) - val nex = match(i*) : - (i:False) : get-name(s) - (i:Int) : get-name(to-symbol(substring(s*,0,i))) - nex - -public defn get-sym-hash (m:InModule) -> HashTable<Symbol,Int> : - get-sym-hash(m,list()) -public defn get-sym-hash (m:InModule,keywords:Streamable<Symbol>) -> HashTable<Symbol,Int> : - val sym-hash = HashTable<Symbol,Int>(symbol-hash) - for k in keywords do : - sym-hash[k] = 0 - defn add-name (s:Symbol) -> Symbol : - val s* = to-string(s) - val i* = generated?(s*) - match(i*) : - (i:False) : - if key?(sym-hash,s) : - val num = sym-hash[s] - sym-hash[s] = max(num,0) - else : - sym-hash[s] = 0 - (i:Int) : - val name = to-symbol(substring(s*,0,i)) - val digit = to-int(substring(s*,i + 1)) - if key?(sym-hash,name) : - val num = sym-hash[name] - sym-hash[name] = max(num,digit) - else : - sym-hash[name] = digit - s - - defn to-port (p:Port) : add-name(name(p)) - defn to-stmt (s:Stmt) -> Stmt : - map{to-stmt,_} $ map(add-name,s) - - to-stmt(body(m)) - map(to-port,ports(m)) - sym-hash - -; ======== Expression Computation Library =========== - -public defn BoolType () : UIntType(IntWidth(1)) -public val zero = UIntValue(BigIntLit(0),IntWidth(1)) -public val one = UIntValue(BigIntLit(1),IntWidth(1)) -public defn uint (i:Int) -> UIntValue : - val num-bits = req-num-bits(i) - val w = IntWidth(max(1,num-bits - 1)) - UIntValue(BigIntLit(i),w) -public defn sint (i:Int) -> SIntValue : - val num-bits = req-num-bits(i) - val w = IntWidth(max(1,num-bits)) - SIntValue(BigIntLit(i),w) - -public defn AND (e1:Expression,e2:Expression) -> Expression : - if e1 == e2 : e1 - else if e1 == zero or e2 == zero : zero - else if e1 == one : e2 - else if e2 == one : e1 - else : DoPrim(AND-OP,list(e1,e2),list(),UIntType(IntWidth(1))) - -public defn OR (e1:Expression,e2:Expression) -> Expression : - if e1 == e2 : e1 - else if e1 == one or e2 == one : one - else if e1 == zero : e2 - else if e2 == zero : e1 - else : DoPrim(OR-OP,list(e1,e2),list(),UIntType(IntWidth(1))) - -public defn EQV (e1:Expression,e2:Expression) -> Expression : - DoPrim(EQUAL-OP,list(e1,e2),list(),type(e1)) - -public defn MUX (p:Expression,e1:Expression,e2:Expression) -> Expression : - Mux(p,e1,e2,mux-type(type(e1),type(e2))) - -public defn mux-type (e1:Expression,e2:Expression) -> Type : - mux-type(type(e1),type(e2)) -public defn mux-type (t1:Type,t2:Type) -> Type : - if t1 == t2 : - match(t1,t2) : - (t1:UIntType,t2:UIntType) : UIntType(UnknownWidth()) - (t1:SIntType,t2:SIntType) : SIntType(UnknownWidth()) - (t1:VectorType,t2:VectorType) : VectorType(mux-type(type(t1),type(t2)),size(t1)) - (t1:BundleType,t2:BundleType) : - BundleType $ for (f1 in fields(t1),f2 in fields(t2)) map : - Field(name(f1),flip(f1),mux-type(type(f1),type(f2))) - else : UnknownType() - -public defn CAT (e1:Expression,e2:Expression) -> Expression : - DoPrim(CONCAT-OP,list(e1,e2),list(),type(e1)) - -public defn NOT (e1:Expression) -> Expression : - if e1 == one : zero - else if e1 == zero : one - else : DoPrim(EQUAL-OP,list(e1,zero),list(),UIntType(IntWidth(1))) - -public defn children (e:Expression) -> List<Expression> : - val es = Vector<Expression>() - defn f (e:Expression) : - add(es,e) - e - map(f,e) - to-list(es) - -public var mname : Symbol = `blah -public defn exp-hash (e:Expression) -> Int : - turn-off-debug(false) - ;val i = symbol-hash(to-symbol(string-join(map(to-string,list(mname `.... e))))) - val i = symbol-hash(to-symbol(to-string(e))) - turn-on-debug(false) - i - -public defn type-hash (t:Type) -> Int : - symbol-hash(to-symbol(to-string(t))) - -public defn list-hash (l:List) -> Int : - turn-off-debug(false) - val i = symbol-hash(to-symbol(string-join(map(to-string,l)))) - turn-on-debug(false) - i - -;===== Type Expansion Algorithms ========= -public defn times (f1:Flip,f2:Flip) -> Flip : - switch {_ == f2} : - DEFAULT : f1 - REVERSE : swap(f1) -public defn swap (f:Flip) -> Flip : - switch {_ == f} : - DEFAULT : REVERSE - REVERSE : DEFAULT - -public defmulti get-type (s:Stmt) -> Type -public defmethod get-type (s:Stmt) -> Type : - match(s) : - (s:DefWire|DefPoison|DefRegister) : type(s) - (s:DefNode) : type(value(s)) - (s:DefMemory) : - val depth = depth(s) - ; Fields - val addr = Field(`addr,DEFAULT,UIntType(IntWidth(ceil-log2(depth)))) - val en = Field(`en,DEFAULT,BoolType()) - val clk = Field(`clk,DEFAULT,ClockType()) - val def-data = Field(`data,DEFAULT,data-type(s)) - val rev-data = Field(`data,REVERSE,data-type(s)) - val mask = Field(`mask,DEFAULT,create-mask(data-type(s))) - val wmode = Field(`wmode,DEFAULT,UIntType(IntWidth(1))) - val rdata = Field(`rdata,REVERSE,data-type(s)) - - val read-type = BundleType(to-list([rev-data,addr,en,clk])) - val write-type = BundleType(to-list([def-data,mask,addr,en,clk])) - val readwrite-type = BundleType(to-list([wmode,rdata,def-data,mask,addr,en,clk])) - - val mem-fields = Vector<Field>() - for x in readers(s) do : - add(mem-fields,Field(x,REVERSE,read-type)) - for x in writers(s) do : - add(mem-fields,Field(x,REVERSE,write-type)) - for x in readwriters(s) do : - add(mem-fields,Field(x,REVERSE,readwrite-type)) - BundleType(to-list(mem-fields)) - (s:DefInstance) : UnknownType() - (s:Begin|Connect|BulkConnect|Stop|Print|Empty|IsInvalid) : UnknownType() - -public defn get-size (t:Type) -> Int : - val x = match(t) : - (t:BundleType) : - var sum = 0 - for f in fields(t) do : - sum = sum + get-size(type(f)) - sum - (t:VectorType) : size(t) * get-size(type(t)) - (t) : 1 - x -public defn get-valid-points (t1:Type,t2:Type,flip1:Flip,flip2:Flip) -> List<[Int,Int]> : - ;println-all(["Inside with t1:" t1 ",t2:" t2 ",f1:" flip1 ",f2:" flip2]) - match(t1,t2) : - (t1:UIntType,t2:UIntType) : - if flip1 == flip2 : list([0, 0]) - else: list() - (t1:SIntType,t2:SIntType) : - if flip1 == flip2 : list([0, 0]) - else: list() - (t1:BundleType,t2:BundleType) : - val points = Vector<[Int,Int]>() - var ilen = 0 - var jlen = 0 - for i in 0 to length(fields(t1)) do : - for j in 0 to length(fields(t2)) do : - ;println(i) - ;println(j) - ;println(ilen) - ;println(jlen) - val f1 = fields(t1)[i] - val f2 = fields(t2)[j] - if name(f1) == name(f2) : - val ls = get-valid-points(type(f1),type(f2),flip1 * flip(f1), - flip2 * flip(f2)) - for x in ls do : - add(points,[x[0] + ilen, x[1] + jlen]) - ;println(points) - jlen = jlen + get-size(type(fields(t2)[j])) - ilen = ilen + get-size(type(fields(t1)[i])) - jlen = 0 - to-list(points) - (t1:VectorType,t2:VectorType) : - val points = Vector<[Int,Int]>() - var ilen = 0 - var jlen = 0 - for i in 0 to min(size(t1),size(t2)) do : - val ls = get-valid-points(type(t1),type(t2),flip1,flip2) - for x in ls do : - add(points,[x[0] + ilen, x[1] + jlen]) - ilen = ilen + get-size(type(t1)) - jlen = jlen + get-size(type(t2)) - to-list(points) - -;============= Useful functions ============== -public defn create-mask (dt:Type) -> Type : - match(dt) : - (t:VectorType) : VectorType(create-mask(type(t)),size(t)) - (t:BundleType) : - val fields* = for f in fields(t) map : - Field(name(f),flip(f),create-mask(type(f))) - BundleType(fields*) - (t:UIntType|SIntType) : BoolType() - -;============== Exceptions ===================== - -public definterface PassException <: Exception -public defn PassException (s:String) : - new PassException : - defmethod print (o:OutputStream, this) : - print(o, s) - -public defn PassExceptions (xs:Streamable<PassException>) : - PassException(string-join(xs, "\n")) - -;============== Pass/Compiler Structs ============ - -public definterface Compiler -public defmulti passes (c:Compiler) -> List<Pass> -public defmulti backend (c:Compiler) -> List<Pass> -defmethod passes (c:Compiler) : List<Pass>() -public defmulti with-output (c:Compiler) -> ((() -> False) -> False) -defmethod with-output (c:Compiler) : 1 as ? - -public definterface Pass -public defmulti pass (p:Pass) -> (Circuit -> Circuit) -public defmethod pass (p:Pass) : fn (c:Circuit) : c -public defmulti name (p:Pass) -> String -public defmethod name (p:Pass) -> String : "--" -public defmulti short-name (p:Pass) -> String -public defmethod short-name (p:Pass) -> String : "--" -public defmethod print (o:OutputStream, p:Pass) : - print(o,name(p)) - -;============== Various Useful Functions ============== - -public defn add-all (v1:Vector,v2:Vector) -> False : - for x in v2 do : - add(v1,x) - - -public defn ceil-log2 (i:Long) -> Long : - defn* loop (n:Long, l:Long) : - if n < i : - if l == 30 : to-long(31) - else : loop(n * to-long(2), l + to-long(1)) - else : l - error("Log of negative number!") when i < to-long(0) - loop(to-long $ 1, to-long $ 0) - - -public defn abs (x:Long) -> Long : - if x < to-long(0) : to-long(0) - x - else : x - -public defn max (x:Long,y:Long) -> Long : - if x < y : y - else : x - - -defn escape (s:String) -> String : - val s* = Vector<String>() - add(s*,"\"");" - for c in s do : - if c == '\n' : - add(s*,"\\n") - else : add(s*,to-string(c)) - add(s*,"\"");" - string-join(s*) - ;" - -;============== PRINTERS =================================== - -defmethod print (o:OutputStream, d:Flip) : - print{o, _} $ - switch {d == _} : - DEFAULT : "" - REVERSE: "flip" - -defmethod print (o:OutputStream, d:Direction) : - print{o, _} $ - switch {d == _} : - INPUT : "input" - OUTPUT: "output" - -defmethod print (o:OutputStream, w:Width) : - print{o, _} $ - match(w) : - (w:UnknownWidth) : "?" - (w:IntWidth) : width(w) - -defmethod print (o:OutputStream, op:PrimOp) : - print{o, _} $ - switch {op == _} : - ADD-OP : "add" - SUB-OP : "sub" - MUL-OP : "mul" - DIV-OP : "div" - REM-OP : "rem" - LESS-OP : "lt" - LESS-EQ-OP : "leq" - GREATER-OP : "gt" - GREATER-EQ-OP : "geq" - EQUAL-OP : "eq" - NEQUAL-OP : "neq" - PAD-OP : "pad" - AS-UINT-OP : "asUInt" - AS-SINT-OP : "asSInt" - AS-CLOCK-OP : "asClock" - SHIFT-LEFT-OP : "shl" - SHIFT-RIGHT-OP : "shr" - DYN-SHIFT-LEFT-OP : "dshl" - DYN-SHIFT-RIGHT-OP : "dshr" - CONVERT-OP : "cvt" - NEG-OP : "neg" - NOT-OP : "not" - AND-OP : "and" - OR-OP : "or" - XOR-OP : "xor" - AND-REDUCE-OP : "andr" - OR-REDUCE-OP : "orr" - XOR-REDUCE-OP : "xorr" - CONCAT-OP : "cat" - BITS-SELECT-OP : "bits" - HEAD-OP : "head" - TAIL-OP : "tail" - -defmethod print (o:OutputStream, e:Expression) : - match(e) : - (e:Ref) : print(o, name(e)) - (e:SubField) : print-all(o, [exp(e) "." name(e)]) - (e:SubIndex) : print-all(o, [exp(e) "[" value(e) "]"]) - (e:SubAccess) : print-all(o, [exp(e) "[" index(e) "]"]) - (e:UIntValue) : - print-all(o, ["UInt<" width(e) ">(" value(e) ")"]) - (e:SIntValue) : print-all(o, ["SInt<" width(e) ">(" value(e) ")"]) - (e:DoPrim) : - print-all(o, [op(e) "("]) - print-all(o, join(concat(args(e), consts(e)), ", ")) - print(o, ")") - (e:Mux) : - print-all(o, ["mux(" cond(e) ", " tval(e) ", " fval(e) ")"]) - (e:ValidIf) : - print-all(o, ["validif(" cond(e) ", " value(e) ")"]) - print-debug(o,e) - -defmethod print (o:OutputStream, c:Stmt) : - val io = IndentedStream(o, 3) - match(c) : - (c:DefPoison) : - print-all(o,["poison " name(c) " : " type(c)]) - (c:DefWire) : - print-all(o,["wire " name(c) " : " type(c)]) - (c:DefRegister) : - print-all(o,["reg " name(c) " : " type(c) ", " clock(c) " with :"]) - print-all(io,["\nreset => (" reset(c) ", " init(c) ")"]) - (c:DefMemory) : - print-all(o,["mem " name(c) " : "]) - print-debug(o,c) - print-all(io,["\ndata-type => " data-type(c)]) - print-all(io,["\ndepth => " depth(c)]) - print-all(io,["\nwrite-latency => " write-latency(c)]) - print-all(io,["\nread-latency => " read-latency(c)]) - for r in readers(c) do : print-all(io,["\nreader => " r]) - for w in writers(c) do : print-all(io,["\nwriter => " w]) - for rw in readwriters(c) do : print-all(io,["\nreadwriter => " rw]) - (c:DefInstance) : - print-all(o,["inst " name(c) " of " module(c)]) - (c:DefNode) : - print-all(o,["node " name(c) " = " value(c)]) - (c:Conditionally) : - if conseq(c) typeof Begin : - print-all(o, ["when " pred(c) " :"]) - print-debug(o,c) - print(o,"\n") - print(io,conseq(c)) - else : - print-all(o, ["when " pred(c) " : " conseq(c)]) - print-debug(o,c) - if alt(c) not-typeof Empty: - print(o, "\nelse :") - print(io, "\n") - print(io,alt(c)) - (c:Begin) : - do(print{o,_}, join(body(c), "\n")) - (c:Connect) : - print-all(o, [loc(c) " <= " exp(c)]) - (c:IsInvalid) : - print-all(o, [exp(c) " is invalid"]) - (c:BulkConnect) : - print-all(o, [loc(c) " <- " exp(c)]) - (c:Empty) : - print(o, "skip") - (c:Stop) : - print-all(o, ["stop(" clk(c) ", " en(c) ", " ret(c) ")"]) - (c:Print) : - print-all(o, ["printf(" clk(c) ", " en(c) ", "]) ;" - print-all(o, join(List(escape(string(c)),args(c)), ", ")) - print(o, ")") - - if not c typeof Conditionally|Begin|Empty: print-debug(o,c) - -defmethod print (o:OutputStream, t:Type) : - match(t) : - (t:UnknownType) : - print(o, "?") - (t:ClockType) : - print(o, "Clock") - (t:UIntType) : - match(width(t)) : - (w:IntWidth) : print-all(o, ["UInt<" width(t) ">"]) - (w) : print-all(o, ["UInt"]) - (t:SIntType) : - match(width(t)) : - (w:IntWidth) : print-all(o, ["SInt<" width(t) ">"]) - (w) : print-all(o, ["SInt"]) - (t:BundleType) : - print(o, "{") - print-all(o, join(fields(t), ", ")) - print(o, "}") - (t:VectorType) : - print-all(o, [type(t) "[" size(t) "]"]) - print-debug(o,t) - -defmethod print (o:OutputStream, f:Field) : - print-all(o, [flip(f) " " name(f) " : " type(f)]) - print-debug(o,f) - -defmethod print (o:OutputStream, p:Port) : - print-all(o, [direction(p) " " name(p) " : " type(p)]) - print-debug(o,p) - -defmethod print (o:OutputStream, m:InModule) : - print-all(o, ["module " name(m) " :"]) - print-debug(o,m) - print(o,"\n") - val io = IndentedStream(o, 3) - for p in ports(m) do : - println(io,p) - print(io,body(m)) - -defmethod print (o:OutputStream, m:ExModule) : - print-all(o, ["extmodule " name(m) " :"]) - print-debug(o,m) - print(o,"\n") - val io = IndentedStream(o, 3) - for p in ports(m) do : - println(io,p) - -defmethod print (o:OutputStream, c:Circuit) : - print-all(o, ["circuit " main(c) " :"]) - print-debug(o,c) - print(o,"\n") - val io = IndentedStream(o, 3) - for m in modules(c) do : - println(io, m) - -;=================== MAPPERS =============================== -public defn map<?T> (f: Type -> Type, t:?T&Type) -> T : - val type = - match(t) : - (t:T&BundleType) : - BundleType $ - for p in fields(t) map : - Field(name(p), flip(p), f(type(p))) - (t:T&VectorType) : - VectorType(f(type(t)), size(t)) - (t) : - t - type as T&Type - -public defmulti map<?T> (f: Expression -> Expression, e:?T&Expression) -> T -defmethod map (f: Expression -> Expression, e:Expression) -> Expression : - match(e) : - (e:SubField) : SubField(f(exp(e)), name(e), type(e)) - (e:SubIndex) : SubIndex(f(exp(e)), value(e), type(e)) - (e:SubAccess) : SubAccess(f(exp(e)), f(index(e)), type(e)) - (e:DoPrim) : DoPrim(op(e), map(f, args(e)), consts(e), type(e)) - (e:Mux) : Mux(f(cond(e)),f(tval(e)),f(fval(e)),type(e)) - (e:ValidIf) : ValidIf(f(cond(e)),f(value(e)),type(e)) - (e) : e - -public defmulti map<?T> (f: Symbol -> Symbol, c:?T&Stmt) -> T -defmethod map (f: Symbol -> Symbol, c:Stmt) -> Stmt : - match(c) : - (c:DefWire) : DefWire(info(c),f(name(c)),type(c)) - (c:DefPoison) : DefPoison(info(c),f(name(c)),type(c)) - (c:DefRegister) : DefRegister(info(c),f(name(c)), type(c), clock(c), reset(c), init(c)) - (c:DefMemory) : DefMemory(info(c),f(name(c)), data-type(c), depth(c), write-latency(c), read-latency(c), readers(c), writers(c), readwriters(c)) - (c:DefNode) : DefNode(info(c),f(name(c)),value(c)) - (c:DefInstance) : DefInstance(info(c),f(name(c)), module(c)) - (c) : c - -public defmulti map<?T> (f: Expression -> Expression, c:?T&Stmt) -> T -defmethod map (f: Expression -> Expression, c:Stmt) -> Stmt : - match(c) : - (c:DefRegister) : DefRegister(info(c),name(c), type(c), f(clock(c)), f(reset(c)), f(init(c))) - (c:DefNode) : DefNode(info(c),name(c), f(value(c))) - ;(c:DefInstance) : DefInstance(info(c),name(c), f(module(c))) - (c:Conditionally) : Conditionally(info(c),f(pred(c)), conseq(c), alt(c)) - (c:Connect) : Connect(info(c),f(loc(c)), f(exp(c))) - (c:BulkConnect) : BulkConnect(info(c),f(loc(c)), f(exp(c))) - (c:IsInvalid) : IsInvalid(info(c),f(exp(c))) - (c:Stop) : Stop(info(c),ret(c),f(clk(c)),f(en(c))) - (c:Print) : Print(info(c),string(c),map(f,args(c)),f(clk(c)),f(en(c))) - (c) : c - -public defmulti map<?T> (f: Stmt -> Stmt, c:?T&Stmt) -> T -defmethod map (f: Stmt -> Stmt, c:Stmt) -> Stmt : - match(c) : - (c:Conditionally) : Conditionally(info(c),pred(c), f(conseq(c)), f(alt(c))) - (c:Begin) : Begin(map(f, body(c))) - (c) : c - -public defmulti map<?T> (f: Width -> Width, c:?T&Expression) -> T -defmethod map (f: Width -> Width, c:Expression) -> Expression : - match(c) : - (c:UIntValue) : UIntValue(value(c),f(width(c))) - (c:SIntValue) : SIntValue(value(c),f(width(c))) - (c) : c - -public defmulti map<?T> (f: Width -> Width, c:?T&Type) -> T -defmethod map (f: Width -> Width, c:Type) -> Type : - match(c) : - (c:UIntType) : UIntType(f(width(c))) - (c:SIntType) : SIntType(f(width(c))) - (c) : c - -public defmulti map<?T> (f: Type -> Type, c:?T&Expression) -> T -defmethod map (f: Type -> Type, c:Expression) -> Expression : - match(c) : - (c:Ref) : Ref(name(c),f(type(c))) - (c:SubField) : SubField(exp(c),name(c),f(type(c))) - (c:SubIndex) : SubIndex(exp(c),value(c),f(type(c))) - (c:SubAccess) : SubAccess(exp(c),index(c),f(type(c))) - (c:DoPrim) : DoPrim(op(c),args(c),consts(c),f(type(c))) - (c:Mux) : Mux(cond(c),tval(c),fval(c),f(type(c))) - (c:ValidIf) : ValidIf(cond(c),value(c),f(type(c))) - (c) : c - -public defmulti map<?T> (f: Type -> Type, c:?T&Stmt) -> T -defmethod map (f: Type -> Type, c:Stmt) -> Stmt : - match(c) : - (c:DefPoison) : DefPoison(info(c),name(c),f(type(c))) - (c:DefWire) : DefWire(info(c),name(c),f(type(c))) - (c:DefRegister) : DefRegister(info(c),name(c),f(type(c)),clock(c),reset(c),init(c)) - (c:DefMemory) : DefMemory(info(c),name(c), f(data-type(c)), depth(c), write-latency(c), read-latency(c), readers(c), writers(c), readwriters(c)) - (c) : c - -public defmulti mapr<?T> (f: Width -> Width, t:?T&Type) -> T -defmethod mapr (f: Width -> Width, t:Type) -> Type : - defn apply-t (t:Type) -> Type : - map{f,_} $ map(apply-t,t) - apply-t(t) - -public defmulti mapr<?T> (f: Width -> Width, s:?T&Stmt) -> T -defmethod mapr (f: Width -> Width, s:Stmt) -> Stmt : - defn apply-t (t:Type) -> Type : mapr(f,t) - defn apply-e (e:Expression) -> Expression : - map{f,_} $ map{apply-t,_} $ map(apply-e,e) - defn apply-s (s:Stmt) -> Stmt : - map{apply-t,_} $ map{apply-e,_} $ map(apply-s,s) - apply-s(s) - - -;================= HELPER FUNCTIONS USING MAP =================== -public defmulti do (f:Expression -> ?, e:Expression) -> False -defmethod do (f:Expression -> ?, e:Expression) -> False : - defn f* (x:Expression) : - f(x) - x - map(f*,e) - false - -public defmulti do (f:Expression -> ?, s:Stmt) -> False -defmethod do (f:Expression -> ?, s:Stmt) -> False : - defn f* (x:Expression) : - f(x) - x - map(f*,s) - false - -public defmulti do (f:Stmt -> ?, s:Stmt) -> False -defmethod do (f:Stmt -> ?, s:Stmt) -> False : - defn f* (x:Stmt) : - f(x) - x - map(f*,s) - false - -; Not well defined - usually use dor on fields of a recursive type -;public defmulti dor (f:Expression -> ?, e:Expression) -> False -;defmethod dor (f:Expression -> ?, e:Expression) -> False : -; f(e) -; for x in e map : -; dor(f,x) -; x -; false -; -;public defmulti dor (f:Expression -> ?, s:Stmt) -> False -;defmethod dor (f:Expression -> ?, s:Stmt) -> False : -; defn f* (x:Expression) : -; dor(f,x) -; x -; map(f*,s) -; false -; -;public defmulti dor (f:Stmt -> ?, s:Stmt) -> False -;defmethod dor (f:Stmt -> ?, s:Stmt) -> False : -; f(s) -; defn f* (x:Stmt) : -; dor(f,x) -; x -; map(f*,s) -; false -; -;public defmulti sub-exps (s:Expression|Stmt) -> List<Expression> -;defmethod sub-exps (e:Expression) -> List<Expression> : -; val l = Vector<Expression>() -; defn f (x:Expression) : add(l,x) -; do(f,e) -; to-list(l) -;defmethod sub-exps (e:Stmt) -> List<Expression> : -; val l = Vector<Expression>() -; defn f (x:Expression) : add(l,x) -; do(f,e) -; to-list(l) -; -;public defmulti sub-stmts (s:Stmt) -> List<Stmt> -;defmethod sub-stmts (s:Stmt) : -; val l = Vector<Stmt>() -; defn f (x:Stmt) : add(l,x) -; do(f,s) -; to-list(l) - -;=================== ADAM OPS =============================== -public defn split (s:String,c:Char) -> List<String> : - if not contains(to-list(s),c) : list(s) - else : - val index = label<Int> ret : - var i = 0 - for c* in to-list(s) do : - if c* == c : ret(i) - else : - i = i + 1 - ret(0) - val h = substring(s,0,index) - val t = substring(s,index + 1,length(s)) - List(h,split(t,c)) - -public defn contains (l:List<Char>, c:Char) : - label<True|False> myret : - for x in l do : - if x == c : myret(true) - false - -public defn merge!<?K,?V> (a:HashTable<?K,?V>, b:HashTable<K,V>) : - for e in b do : - a[key(e)] = value(e) - - - -;=================== VERILOG KEYWORDS ======================= - -public val v-keywords = HashTable<Symbol,True>(symbol-hash) -v-keywords[`alias] = true -v-keywords[`always] = true -v-keywords[`always_comb] = true -v-keywords[`always_ff] = true -v-keywords[`always_latch] = true -v-keywords[`and] = true -v-keywords[`assert] = true -v-keywords[`assign] = true -v-keywords[`assume] = true -v-keywords[`attribute] = true -v-keywords[`automatic] = true -v-keywords[`before] = true -v-keywords[`begin] = true -v-keywords[`bind] = true -v-keywords[`bins] = true -v-keywords[`binsof] = true -v-keywords[`bit] = true -v-keywords[`break] = true -v-keywords[`buf] = true -v-keywords[`bufif0] = true -v-keywords[`bufif1] = true -v-keywords[`byte] = true -v-keywords[`case] = true -v-keywords[`casex] = true -v-keywords[`casez] = true -v-keywords[`cell] = true -v-keywords[`chandle] = true -v-keywords[`class] = true -v-keywords[`clocking] = true -v-keywords[`cmos] = true -v-keywords[`config] = true -v-keywords[`const] = true -v-keywords[`constraint] = true -v-keywords[`context] = true -v-keywords[`continue] = true -v-keywords[`cover] = true -v-keywords[`covergroup] = true -v-keywords[`coverpoint] = true -v-keywords[`cross] = true -v-keywords[`deassign] = true -v-keywords[`default] = true -v-keywords[`defparam] = true -v-keywords[`design] = true -v-keywords[`disable] = true -v-keywords[`dist] = true -v-keywords[`do] = true -v-keywords[`edge] = true -v-keywords[`else] = true -v-keywords[`end] = true -v-keywords[`endattribute] = true -v-keywords[`endcase] = true -v-keywords[`endclass] = true -v-keywords[`endclocking] = true -v-keywords[`endconfig] = true -v-keywords[`endfunction] = true -v-keywords[`endgenerate] = true -v-keywords[`endgroup] = true -v-keywords[`endinterface] = true -v-keywords[`endmodule] = true -v-keywords[`endpackage] = true -v-keywords[`endprimitive] = true -v-keywords[`endprogram] = true -v-keywords[`endproperty] = true -v-keywords[`endspecify] = true -v-keywords[`endsequence] = true -v-keywords[`endtable] = true -v-keywords[`endtask] = true -v-keywords[`enum] = true -v-keywords[`event] = true -v-keywords[`expect] = true -v-keywords[`export] = true -v-keywords[`extends] = true -v-keywords[`extern] = true -v-keywords[`final] = true -v-keywords[`first_match] = true -v-keywords[`for] = true -v-keywords[`force] = true -v-keywords[`foreach] = true -v-keywords[`forever] = true -v-keywords[`fork] = true -v-keywords[`forkjoin] = true -v-keywords[`function] = true -v-keywords[`generate] = true -v-keywords[`genvar] = true -v-keywords[`highz0] = true -v-keywords[`highz1] = true -v-keywords[`if] = true -v-keywords[`iff] = true -v-keywords[`ifnone] = true -v-keywords[`ignore_bins] = true -v-keywords[`illegal_bins] = true -v-keywords[`import] = true -v-keywords[`incdir] = true -v-keywords[`include] = true -v-keywords[`initial] = true -v-keywords[`initvar] = true -v-keywords[`inout] = true -v-keywords[`input] = true -v-keywords[`inside] = true -v-keywords[`instance] = true -v-keywords[`int] = true -v-keywords[`integer] = true -v-keywords[`interconnect] = true -v-keywords[`interface] = true -v-keywords[`intersect] = true -v-keywords[`join] = true -v-keywords[`join_any] = true -v-keywords[`join_none] = true -v-keywords[`large] = true -v-keywords[`liblist] = true -v-keywords[`library] = true -v-keywords[`local] = true -v-keywords[`localparam] = true -v-keywords[`logic] = true -v-keywords[`longint] = true -v-keywords[`macromodule] = true -v-keywords[`matches] = true -v-keywords[`medium] = true -v-keywords[`modport] = true -v-keywords[`module] = true -v-keywords[`nand] = true -v-keywords[`negedge] = true -v-keywords[`new] = true -v-keywords[`nmos] = true -v-keywords[`nor] = true -v-keywords[`noshowcancelled] = true -v-keywords[`not] = true -v-keywords[`notif0] = true -v-keywords[`notif1] = true -v-keywords[`null] = true -v-keywords[`or] = true -v-keywords[`output] = true -v-keywords[`package] = true -v-keywords[`packed] = true -v-keywords[`parameter] = true -v-keywords[`pmos] = true -v-keywords[`posedge] = true -v-keywords[`primitive] = true -v-keywords[`priority] = true -v-keywords[`program] = true -v-keywords[`property] = true -v-keywords[`protected] = true -v-keywords[`pull0] = true -v-keywords[`pull1] = true -v-keywords[`pulldown] = true -v-keywords[`pullup] = true -v-keywords[`pulsestyle_onevent] = true -v-keywords[`pulsestyle_ondetect] = true -v-keywords[`pure] = true -v-keywords[`rand] = true -v-keywords[`randc] = true -v-keywords[`randcase] = true -v-keywords[`randsequence] = true -v-keywords[`rcmos] = true -v-keywords[`real] = true -v-keywords[`realtime] = true -v-keywords[`ref] = true -v-keywords[`reg] = true -v-keywords[`release] = true -v-keywords[`repeat] = true -v-keywords[`return] = true -v-keywords[`rnmos] = true -v-keywords[`rpmos] = true -v-keywords[`rtran] = true -v-keywords[`rtranif0] = true -v-keywords[`rtranif1] = true -v-keywords[`scalared] = true -v-keywords[`sequence] = true -v-keywords[`shortint] = true -v-keywords[`shortreal] = true -v-keywords[`showcancelled] = true -v-keywords[`signed] = true -v-keywords[`small] = true -v-keywords[`solve] = true -v-keywords[`specify] = true -v-keywords[`specparam] = true -v-keywords[`static] = true -v-keywords[`strength] = true -v-keywords[`string] = true -v-keywords[`strong0] = true -v-keywords[`strong1] = true -v-keywords[`struct] = true -v-keywords[`super] = true -v-keywords[`supply0] = true -v-keywords[`supply1] = true -v-keywords[`table] = true -v-keywords[`tagged] = true -v-keywords[`task] = true -v-keywords[`this] = true -v-keywords[`throughout] = true -v-keywords[`time] = true -v-keywords[`timeprecision] = true -v-keywords[`timeunit] = true -v-keywords[`tran] = true -v-keywords[`tranif0] = true -v-keywords[`tranif1] = true -v-keywords[`tri] = true -v-keywords[`tri0] = true -v-keywords[`tri1] = true -v-keywords[`triand] = true -v-keywords[`trior] = true -v-keywords[`trireg] = true -v-keywords[`type] = true -v-keywords[`typedef] = true -v-keywords[`union] = true -v-keywords[`unique] = true -v-keywords[`unsigned] = true -v-keywords[`use] = true -v-keywords[`var] = true -v-keywords[`vectored] = true -v-keywords[`virtual] = true -v-keywords[`void] = true -v-keywords[`wait] = true -v-keywords[`wait_order] = true -v-keywords[`wand] = true -v-keywords[`weak0] = true -v-keywords[`weak1] = true -v-keywords[`while] = true -v-keywords[`wildcard] = true -v-keywords[`wire] = true -v-keywords[`with] = true -v-keywords[`within] = true -v-keywords[`wor] = true -v-keywords[`xnor] = true -v-keywords[`xor] = true -v-keywords[`SYNTHESIS] = true -v-keywords[`PRINTF_COND] = true -v-keywords[`VCS] = true diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza deleted file mode 100644 index e9abaf74..00000000 --- a/src/main/stanza/passes.stanza +++ /dev/null @@ -1,2930 +0,0 @@ -;Copyright (c) 2014 - 2016 The Regents of the University of -;California (Regents). All Rights Reserved. Redistribution and use in -;source and binary forms, with or without modification, are permitted -;provided that the following conditions are met: -; * Redistributions of source code must retain the above -; copyright notice, this list of conditions and the following -; two paragraphs of disclaimer. -; * Redistributions in binary form must reproduce the above -; copyright notice, this list of conditions and the following -; two paragraphs of disclaimer in the documentation and/or other materials -; provided with the distribution. -; * Neither the name of the Regents nor the names of its contributors -; may be used to endorse or promote products derived from this -; software without specific prior written permission. -;IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, -;SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, -;ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF -;REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT -;LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -;A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF -;ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION -;TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR -;MODIFICATIONS. -defpackage firrtl/passes : - import core - import verse - import firrtl/ir2 - import firrtl/ir-utils - import firrtl/primops - import firrtl-main - import firrtl/errors - import bigint2 - -;============== Pass List ================ -public val standard-passes = to-list $ [ - CheckHighForm() - ToWorkingIR() - Resolve() - ResolveKinds() - InferTypes() - CheckTypes() - ResolveGenders() - CheckGenders() - InferWidths() - CheckWidths() - PullMuxes() - ExpandConnects() - RemoveAccesses() - ExpandWhens() - LowerTypes() - CheckInitialization() - ConstProp() - VerilogWrap() - SplitExp() - VerilogRename() - Resolve() -] -;=============== WORKING IR ================================ -public definterface Kind -public defstruct WireKind <: Kind -public defstruct PoisonKind <: Kind -public defstruct RegKind <: Kind -public defstruct InstanceKind <: Kind -public defstruct PortKind <: Kind -public defstruct NodeKind <: Kind -public defstruct MemKind <: Kind : - ports : List<Symbol> -public defstruct ExpKind <: Kind - -public definterface Gender -public val MALE = new Gender -public val FEMALE = new Gender -public val UNKNOWN-GENDER = new Gender -public val BI-GENDER = new Gender - -public defstruct WRef <: Expression : - name: Symbol - type: Type with: (as-method => true) - kind: Kind with: (as-method => true) - gender: Gender with: (as-method => true) -public defstruct WSubField <: Expression : - exp: Expression - name: Symbol - type: Type with: (as-method => true) - gender: Gender with: (as-method => true) -public defstruct WSubIndex <: Expression : - exp: Expression - value: Int - type: Type with: (as-method => true) - gender: Gender with: (as-method => true) -public defstruct WSubAccess <: Expression : - exp: Expression - index: Expression - type: Type with: (as-method => true) - gender: Gender with: (as-method => true) -public defstruct WVoid <: Expression -public defstruct WInvalid <: Expression -public defstruct WDefInstance <: Stmt : - info: FileInfo with: (as-method => true) - name: Symbol - module: Symbol - type: Type - -defmulti gender (e:Expression) -> Gender -defmethod gender (e:Expression) : - MALE - -defn get-gender (s:Stmt|Port) -> Gender : - match(s) : - (s:DefWire|DefRegister) : BI-GENDER - (s:WDefInstance|DefNode|DefInstance|DefPoison) : MALE - (s:Begin|Connect|BulkConnect|Stop|Print|Empty|IsInvalid) : UNKNOWN-GENDER - (s:DefMemory) : MALE - (p:Port) : - switch { _ == direction(p) } : - INPUT : MALE - OUTPUT : FEMALE - -public defmulti kind (e:Expression) -> Kind -defmethod kind (e:Expression) : - match(e) : - (e:WRef) : kind(e) - (e:WSubField) : kind(exp(e)) - (e:WSubIndex) : kind(exp(e)) - (e) : ExpKind() - -defmethod info (stmt:Begin) -> FileInfo : FileInfo() -defmethod info (stmt:Empty) -> FileInfo : FileInfo() - -defmethod type (exp:UIntValue) -> Type : UIntType(width(exp)) -defmethod type (exp:SIntValue) -> Type : SIntType(width(exp)) -defmethod type (exp:WVoid) -> Type : UnknownType() -defmethod type (exp:WInvalid) -> Type : UnknownType() - -defmethod get-type (s:WDefInstance) -> Type : type(s) - -defmethod equal? (e1:Expression,e2:Expression) -> True|False : - match(e1,e2) : - (e1:UIntValue,e2:UIntValue) : - if to-int(value(e1)) == to-int(value(e2)) : width(e1) == width(e2) - else : false - (e1:SIntValue,e2:SIntValue) : - if to-int(value(e1)) == to-int(value(e2)) : width(e1) == width(e2) - else : false - (e1:WRef,e2:WRef) : name(e1) == name(e2) - (e1:WSubField,e2:WSubField) : - (name(e1) == name(e2)) and (exp(e1) == exp(e2)) - (e1:WSubIndex,e2:WSubIndex) : - (value(e1) == value(e2)) and (exp(e1) == exp(e2)) - (e1:WSubAccess,e2:WSubAccess) : - (index(e1) == index(e2)) and (exp(e1) == exp(e2)) - (e1:WVoid,e2:WVoid) : true - (e1:WInvalid,e2:WInvalid) : true - (e1:DoPrim,e2:DoPrim) : - var are-equal? = op(e1) == op(e2) - for (x in args(e1),y in args(e2)) do : - if not x == y : - are-equal? = false - for (x in consts(e1),y in consts(e2)) do : - if not x == y : - are-equal? = false - are-equal? - (e1:Mux,e2:Mux) : - (cond(e1) == cond(e2)) and - (tval(e1) == tval(e2)) and - (fval(e1) == fval(e2)) - (e1:ValidIf,e2:ValidIf) : - (cond(e1) == cond(e2)) and - (value(e1) == value(e2)) - (e1,e2) : false - -; ================= PRINTERS =================== -defmethod print (o:OutputStream, g:Gender) : - print{o, _} $ - switch {g == _} : - MALE : "m" - FEMALE: "f" - BI-GENDER : "b" - UNKNOWN-GENDER: "u" - -;============== DEBUG STUFF ============================= -public var PRINT-TYPES : True|False = false -public var PRINT-KINDS : True|False = false -public var PRINT-WIDTHS : True|False = false -public var PRINT-TWIDTHS : True|False = false -public var PRINT-GENDERS : True|False = false -public var PRINT-CIRCUITS : True|False = false -public var PRINT-DEBUG : True|False = false -public var PRINT-INFO : True|False = false - -;========= TO TURN OFF =========== - -var old-PRINT-TYPES : True|False = false -var old-PRINT-KINDS : True|False = false -var old-PRINT-WIDTHS : True|False = false -var old-PRINT-TWIDTHS : True|False = false -var old-PRINT-GENDERS : True|False = false -var old-PRINT-CIRCUITS : True|False = false -var old-PRINT-DEBUG : True|False = false -var old-PRINT-INFO : True|False = false -defmethod turn-off-debug (x:False) : - old-PRINT-TYPES = PRINT-TYPES - old-PRINT-KINDS = PRINT-KINDS - old-PRINT-WIDTHS = PRINT-WIDTHS - old-PRINT-TWIDTHS = PRINT-TWIDTHS - old-PRINT-GENDERS = PRINT-GENDERS - old-PRINT-CIRCUITS = PRINT-CIRCUITS - old-PRINT-DEBUG = PRINT-DEBUG - old-PRINT-INFO = PRINT-INFO - PRINT-TYPES = false - PRINT-KINDS = false - PRINT-WIDTHS = false - PRINT-TWIDTHS = false - PRINT-GENDERS = false - PRINT-CIRCUITS = false - PRINT-DEBUG = false - PRINT-INFO = false - -defmethod turn-on-debug (x:False) : - PRINT-TYPES = old-PRINT-TYPES - PRINT-KINDS = old-PRINT-KINDS - PRINT-WIDTHS = old-PRINT-WIDTHS - PRINT-TWIDTHS = old-PRINT-TWIDTHS - PRINT-GENDERS = old-PRINT-GENDERS - PRINT-CIRCUITS = old-PRINT-CIRCUITS - PRINT-DEBUG = old-PRINT-DEBUG - PRINT-INFO = old-PRINT-INFO - -;=== ThePrinters === - -public defn println-all-debug (l:?) -> False : - if PRINT-DEBUG : println-all(l) - else : false - -public defn println-debug (s:?) -> False : - if PRINT-DEBUG : println(s) - else : false - -defmethod print (o:OutputStream, k:Kind) : - print{o, _} $ - match(k) : - (k:WireKind) : "wire" - (k:PoisonKind) : "poison" - (k:RegKind) : "reg" - (k:PortKind) : "port" - (k:MemKind) : "mem" - (k:NodeKind) : "node" - (k:InstanceKind) : "inst" - (k:ExpKind) : "exp" - -defn hasGender (e:?) : - e typeof Expression - -defn hasWidth (e:?) : - e typeof UIntType|SIntType|UIntValue|SIntValue - -defn hasType (e:?) : - e typeof Expression|DefWire|DefRegister|DefPoison - |VectorType|Port|UIntValue|SIntValue - -defn hasKind (e:?) : - e typeof Expression - -defn hasInfo (e:?) : - e typeof Stmt|Port|Circuit|Module - -defn any-debug? (e:?) : - (hasGender(e) and PRINT-GENDERS) or - (hasType(e) and PRINT-TYPES) or - (hasWidth(e) and PRINT-WIDTHS) or - (hasKind(e) and PRINT-KINDS) or - (hasInfo(e) and PRINT-INFO) - -defmethod print-debug (o:OutputStream, e:Expression|Stmt|Type|Port|Field|Module|Circuit) : - defn wipe-width (t:Type) -> Type : - match(t) : - (t:UIntType) : UIntType(UnknownWidth()) - (t:SIntType) : SIntType(UnknownWidth()) - (t) : map(wipe-width,t) - - if any-debug?(e) : print(o,"@") - if PRINT-KINDS and hasKind(e) : print-all(o,["<k:" kind(e as ?) ">"]) - if PRINT-TYPES and hasType(e) : print-all(o,["<t:" wipe-width(type(e as ?)) ">"]) - if PRINT-TWIDTHS and hasType(e): print-all(o,["<t:" type(e as ?) ">"]) - if PRINT-WIDTHS and hasWidth(e): print-all(o,["<w:" width(e as ?) ">"]) - if PRINT-GENDERS and hasGender(e): print-all(o,["<g:" gender(e as ?) ">"]) - if PRINT-INFO and hasInfo(e): print-all(o,["<i:" info(e as ?) ">"]) - -defmethod print (o:OutputStream, e:WRef) : - print(o,name(e)) - print-debug(o,e as ?) -defmethod print (o:OutputStream, e:WSubField) : - print-all(o,[exp(e) "." name(e)]) - print-debug(o,e as ?) -defmethod print (o:OutputStream, e:WSubIndex) : - print-all(o,[exp(e) "[" value(e) "]"]) - print-debug(o,e as ?) -defmethod print (o:OutputStream, e:WSubAccess) : - print-all(o,[exp(e) "[" index(e) "]"]) - print-debug(o,e as ?) -defmethod print (o:OutputStream, e:WVoid) : - print(o,"VOID") - print-debug(o,e as ?) -defmethod print (o:OutputStream, e:WInvalid) : - print(o,"INVALID") - print-debug(o,e as ?) -defmethod print (o:OutputStream, c:WDefInstance) : - print-all(o, ["inst " name(c) " of " module(c) " : " type(c)]) - print-debug(o,c as ?) - - -defmethod map (f: Expression -> Expression, e: WSubField) : - WSubField(f(exp(e)), name(e), type(e), gender(e)) -defmethod map (f: Expression -> Expression, e: WSubIndex) : - WSubIndex(f(exp(e)), value(e), type(e), gender(e)) -defmethod map (f: Expression -> Expression, e: WSubAccess) : - WSubAccess(f(exp(e)), f(index(e)), type(e), gender(e)) - -defmethod map (f: Type -> Type, e: WRef) : - WRef(name(e), f(type(e)), kind(e), gender(e)) -defmethod map (f: Type -> Type, e: WSubField) : - WSubField(exp(e), name(e), f(type(e)), gender(e)) -defmethod map (f: Type -> Type, e: WSubIndex) : - WSubIndex(exp(e), value(e), f(type(e)), gender(e)) -defmethod map (f: Type -> Type, e: WSubAccess) : - WSubAccess(exp(e), index(e), f(type(e)), gender(e)) - -defmethod map (f: Type -> Type, s: WDefInstance) : - WDefInstance(info(s),name(s),module(s),f(type(s))) -defmethod map (f: Symbol -> Symbol, s: WDefInstance) : - WDefInstance(info(s),f(name(s)),module(s),type(s)) - -;================ WIDTH LIBRARY ==================== - -public val ONE = IntWidth(1) -public defstruct VarWidth <: Width : - name: Symbol -public defstruct PlusWidth <: Width : - arg1 : Width - arg2 : Width -public defstruct MinusWidth <: Width : - arg1 : Width - arg2 : Width -public defstruct MaxWidth <: Width : - args : List<Width> -public defstruct MinWidth <: Width : - args : List<Width> -public defstruct ExpWidth <: Width : - arg1 : Width -val width-name-hash = HashTable<Symbol,Int>(symbol-hash) - -public defmulti map<?T> (f: Width -> Width, w:?T&Width) -> T -defmethod map (f: Width -> Width, w:Width) -> Width : - match(w) : - (w:MaxWidth) : MaxWidth(map(f,args(w))) - (w:MinWidth) : MinWidth(map(f,args(w))) - (w:PlusWidth) : PlusWidth(f(arg1(w)),f(arg2(w))) - (w:MinusWidth) : MinusWidth(f(arg1(w)),f(arg2(w))) - (w:ExpWidth) : ExpWidth(f(arg1(w))) - (w) : w - -public defmethod print (o:OutputStream, w:VarWidth) : - print(o,name(w)) -public defmethod print (o:OutputStream, w:MaxWidth) : - print-all(o,["max" args(w)]) -public defmethod print (o:OutputStream, w:MinWidth) : - print-all(o,["min" args(w)]) -public defmethod print (o:OutputStream, w:PlusWidth) : - print-all(o,[ "(" arg1(w) " + " arg2(w) ")"]) -public defmethod print (o:OutputStream, w:MinusWidth) : - print-all(o,[ "(" arg1(w) " - " arg2(w) ")"]) -public defmethod print (o:OutputStream, w:ExpWidth) : - print-all(o,[ "exp(" arg1(w) ")"]) - -defn remove-unknowns-w (w:Width) -> Width : - match(w) : - (w:UnknownWidth) : VarWidth(firrtl-gensym(`w,width-name-hash)) - (w) : w -defn remove-unknowns (t:Type) -> Type : mapr(remove-unknowns-w,t) - -defmethod equal? (w1:Width,w2:Width) -> True|False : - match(w1,w2) : - (w1:VarWidth,w2:VarWidth) : name(w1) == name(w2) - (w1:MaxWidth,w2:MaxWidth) : - label<True|False> ret : - if not length(args(w1)) == length(args(w2)) : ret(false) - else : - for w in args(w1) do : - if not contains?(args(w2),w) : ret(false) - ret(true) - (w1:MinWidth,w2:MinWidth) : - label<True|False> ret : - if not length(args(w1)) == length(args(w2)) : ret(false) - else : - for w in args(w1) do : - if not contains?(args(w2),w) : ret(false) - ret(true) - (w1:IntWidth,w2:IntWidth) : width(w1) == width(w2) - (w1:PlusWidth,w2:PlusWidth) : - (arg1(w1) == arg1(w2) and arg2(w1) == arg2(w2)) or (arg1(w1) == arg2(w2) and arg2(w1) == arg1(w2)) - (w1:MinusWidth,w2:MinusWidth) : - (arg1(w1) == arg1(w2) and arg2(w1) == arg2(w2)) or (arg1(w1) == arg2(w2) and arg2(w1) == arg1(w2)) - (w1:ExpWidth,w2:ExpWidth) : arg1(w1) == arg1(w2) - (w1:UnknownWidth,w2:UnknownWidth) : true - (w1,w2) : false -;================ WORKING IR UTILS ========================= -;defn plus (g1:Gender,g2:Gender) -> Gender : -; switch fn ([x,y]) : g1 == x and g2 == y : -; [FEMALE,MALE] : UNKNOWN-GENDER -; [MALE,FEMALE] : UNKNOWN-GENDER -; [MALE,MALE] : MALE -; [FEMALE,FEMALE] : FEMALE -; [BI-GENDER,MALE] : MALE -; [BI-GENDER,FEMALE] : FEMALE -; [MALE,BI-GENDER] : MALE -; [FEMALE,BI-GENDER] : FEMALE - -; These functions do not error, but return Unknown Type -defn module-type (m:Module) -> Type : - BundleType(for p in ports(m) map : to-field(p)) -defn field-type (v:Type,s:Symbol) -> Type : - match(v) : - (v:BundleType) : - val ft = for p in fields(v) find : name(p) == s - if ft != false : type(ft as Field) - else : UnknownType() - (v) : UnknownType() -defn sub-type (v:Type) -> Type : - match(v) : - (v:VectorType) : type(v) - (v) : UnknownType() -defn field-flip (v:Type,s:Symbol) -> Flip : - match(v) : - (v:BundleType) : - val ft = for p in fields(v) find : name(p) == s - if ft != false : flip(ft as Field) - else : DEFAULT ;This will get caught later - (v) : DEFAULT - -defn swap (g:Gender) -> Gender : - switch {_ == g} : - UNKNOWN-GENDER : UNKNOWN-GENDER - MALE : FEMALE - FEMALE : MALE - BI-GENDER : BI-GENDER -defn swap (d:Direction) -> Direction : - switch {_ == d} : - OUTPUT : INPUT - INPUT : OUTPUT - -public defn times (flip:Flip,d:Direction) -> Direction : - flip * d -public defn times (d:Direction,flip:Flip) -> Direction : - switch {_ == flip} : - DEFAULT : d - REVERSE : swap(d) -public defn times (g:Gender,flip:Flip) -> Gender : flip * g -public defn times (flip:Flip,g:Gender) -> Gender : - switch {_ == flip} : - DEFAULT : g - REVERSE : swap(g) -defn to-field (p:Port) -> Field : - if direction(p) == OUTPUT : Field(name(p),DEFAULT,type(p)) - else if direction(p) == INPUT : Field(name(p),REVERSE,type(p)) - else : error("Shouldn't be here") -defn to-dir (g:Gender) -> Direction : - switch {_ == g} : - MALE : INPUT - FEMALE : OUTPUT -defn to-gender (d:Direction) -> Gender : - switch {_ == d} : - INPUT: MALE - OUTPUT: FEMALE - -public defn mux-type-and-widths (e1:Expression,e2:Expression) -> Type : - mux-type-and-widths(type(e1),type(e2)) -public defn mux-type-and-widths (t1:Type,t2:Type) -> Type : - defn wmax (w1:Width,w2:Width) -> Width : - match(w1,w2) : - (w1:IntWidth,w2:IntWidth) : IntWidth(max(width(w1),width(w2))) - (w1,w2) : MaxWidth(list(w1,w2)) - if t1 == t2 : - match(t1,t2) : - (t1:UIntType,t2:UIntType) : UIntType(wmax(width(t1),width(t2))) - (t1:SIntType,t2:SIntType) : SIntType(wmax(width(t1),width(t2))) - (t1:VectorType,t2:VectorType) : VectorType(mux-type-and-widths(type(t1),type(t2)),size(t1)) - (t1:BundleType,t2:BundleType) : - BundleType $ for (f1 in fields(t1),f2 in fields(t2)) map : - Field(name(f1),flip(f1),mux-type-and-widths(type(f1),type(f2))) - else : UnknownType() - -;================= Remove Special Characters ======================== -; Returns a new Circuit where all names have all special characters -; removed, except _. -; -;public defstruct RemoveSpecialChars <: Pass -;public defmethod pass (b:RemoveSpecialChars) -> (Circuit -> Circuit) : remove-special-chars -;public defmethod name (b:RemoveSpecialChars) -> String : "Remove Special Characters" -;public defmethod short-name (b:RemoveSpecialChars) -> String : "rem-spec-chars" -; -;;------------ Helper Functions ------------- -; -;defn get-new-string (n:Char) -> String : -; switch {n == _} : -; '_' : "__" -; '~' : "$A" -; '!' : "$B" -; '@' : "$C" -; '#' : "$D" -; '$' : "$E" -; '%' : "$F" -; '^' : "$G" -; '*' : "$H" -; '-' : "$I" -; '+' : "$J" -; '=' : "$K" -; '?' : "$L" -; '/' : "$M" -; else : to-string(n) -; -;;------------ Pass ------------------ -; -;defn remove-special-chars (c:Circuit) : -; defn rename (n:Symbol) -> Symbol : -; val v = Vector<String>() -; for c in to-string(n) do : -; add(v,get-new-string(c)) -; val n* = symbol-join(v) -; if key?(v-keywords,n*) : -; symbol-join([n* `_]) -; else : -; n* -; defn rename-t (t:Type) -> Type : -; match(t) : -; (t:BundleType) : BundleType $ -; for f in fields(t) map : -; Field(rename(name(f)),flip(f),rename-t(type(f))) -; (t:VectorType) : VectorType(rename-t(type(t)),size(t)) -; (t) : t -; defn rename-e (e:Expression) -> Expression : -; match(e) : -; (e:Ref) : Ref(rename(name(e)),rename-t(type(e))) -; (e:Subfield) : Subfield(rename-e(exp(e)),rename(name(e)),rename-t(type(e))) -; (e:Index) : Index(rename-e(exp(e)),value(e),rename-t(type(e))) -; (e:DoPrim) : DoPrim{op(e),_,consts(e),rename-t(type(e))} $ for x in args(e) map : rename-e(x) -; (e:UIntValue) : e -; (e:SIntValue) : e -; defn rename-s (s:Stmt) -> Stmt : -; match(s) : -; (s:DefWire) : DefWire(info(s),rename(name(s)),rename-t(type(s))) -; (s:DefPoison) : DefPoison(info(s),rename(name(s)),rename-t(type(s))) -; (s:DefRegister) : DefRegister(info(s),rename(name(s)),rename-t(type(s)),rename-e(clock(s)),rename-e(reset(s))) -; (s:WDefInstance) : WDefInstance(info(s),rename(name(s)),rename-e(module(s))) -; (s:DefMemory) : DefMemory(info(s),rename(name(s)),rename-t(type(s)),seq?(s),rename-e(clock(s)),size(s)) -; (s:DefNode) : DefNode(info(s),rename(name(s)),rename-e(value(s))) -; (s:DefAccessor) : DefAccessor(info(s),rename(name(s)),rename-e(source(s)),rename-e(index(s)),acc-dir(s)) -; (s:Conditionally) : Conditionally(info(s),rename-e(pred(s)),rename-s(conseq(s)),rename-s(alt(s))) -; (s:Begin) : Begin $ for b in body(s) map : rename-s(b) -; (s:OnReset) : OnReset(info(s),rename-e(loc(s)),rename-e(exp(s))) -; (s:BulkConnect) : BulkConnect(info(s),rename-e(loc(s)),rename-e(exp(s))) -; (s:Connect) : Connect(info(s),rename-e(loc(s)),rename-e(exp(s))) -; (s:EmptyStmt) : s -; (s:StopStmt) : s -; (s:PrintfStmt) : PrintfStmt(info(s),string(s),map(rename-e,args(s))) -; -; Circuit(info(c),modules*, rename(main(c))) where : -; val modules* = -; for m in modules(c) map : -; match(m) : -; (m:InModule) : -; val ports* = for p in ports(m) map : -; Port(info(p),rename(name(p)),direction(p),rename-t(type(p))) -; InModule(info(m),rename(name(m)), ports*, rename-s(body(m))) -; (m:ExModule) : m - - -;================= Temporary Variable Elimination ======================== -; Returns a new Circuit where temporary variables are removed and returns -; the resulting nested expression -;public defstruct TempElimination <: Pass -;public defmethod pass (b:TempElimination) -> (Circuit -> Circuit) : temp-elimination -;public defmethod name (b:TempElimination) -> String : "Temp Elimination" -;public defmethod short-name (b:TempElimination) -> String : "temp-elim" -; -;defn temp-elimination (c:Circuit) : -; defn is-temp? (n:Symbol) -> True|False : -; to-string(n)[0] == 'T' -; defn temp-elim (m:InModule) : -; val h = HashTable<Symbol,Expression>(symbol-hash) -; defn temp-elim-e (e:Expression) : -; match(map(temp-elim-e,e)) : -; (e:Ref) : -; if key?(h,name(e)) : h[name(e)] -; else : e -; (e) : e -; defn temp-elim-s (s:Stmt) : -; match(map(temp-elim-e,s)) : -; (s:DefNode) : -; if is-temp?(name(s)) : -; h[name(s)] = value(s) -; EmptyStmt() -; else : s -; (s) : map(temp-elim-s,s) -; InModule(info(m),name(m), ports(m), temp-elim-s(body(m))) -; -; Circuit(info(c),modules*, main(c)) where : -; val modules* = -; for m in modules(c) map : -; match(m) : -; (m:InModule) : temp-elim(m) -; (m:ExModule) : m - -;================= Bring to Working IR ======================== -; Returns a new Circuit with Refs, Subfields, Indexes and DefAccessors -; replaced with IR-internal nodes that contain additional -; information (kind, gender) - -public defstruct ToWorkingIR <: Pass -public defmethod pass (b:ToWorkingIR) -> (Circuit -> Circuit) : to-working-ir -public defmethod name (b:ToWorkingIR) -> String : "Working IR" -public defmethod short-name (b:ToWorkingIR) -> String : "to-working-ir" - -defn to-working-ir (c:Circuit) : - defn to-exp (e:Expression) -> Expression : - match(map(to-exp,e)) : - (e:Ref) : WRef(name(e), type(e), NodeKind(), UNKNOWN-GENDER) - (e:SubField) : WSubField(exp(e), name(e), type(e), UNKNOWN-GENDER) - (e:SubIndex) : WSubIndex(exp(e), value(e), type(e), UNKNOWN-GENDER) - (e:SubAccess) : WSubAccess(exp(e), index(e), type(e), UNKNOWN-GENDER) - (e) : e - defn to-stmt (s:Stmt) -> Stmt : - match(map(to-exp,s)) : - (s:DefInstance) : WDefInstance(info(s),name(s),module(s),UnknownType()) - (s) : map(to-stmt,s) - - Circuit(info(c),modules*, main(c)) where : - val modules* = - for m in modules(c) map : - match(m) : - (m:InModule) : InModule(info(m),name(m), ports(m), to-stmt(body(m))) - (m:ExModule) : m - -;=============== Resolve Kinds ============================= -; It is useful for the compiler to know information about -; objects referenced. This information is stored in the kind -; field in WRef. This pass walks the graph and returns a new -; Circuit where all WRef kinds are resolved -public defstruct ResolveKinds <: Pass -public defmethod pass (b:ResolveKinds) -> (Circuit -> Circuit) : resolve-kinds -public defmethod name (b:ResolveKinds) -> String : "Resolve Kinds" -public defmethod short-name (b:ResolveKinds) -> String : "resolve-kinds" - -defn resolve-kinds (c:Circuit) : - defn resolve (body:Stmt, kinds:HashTable<Symbol,Kind>) : - defn resolve-stmt (s:Stmt) -> Stmt : - map{resolve-expr,_} $ - map(resolve-stmt,s) - - defn resolve-expr (e:Expression) -> Expression : - match(e) : - (e:WRef) : WRef(name(e),type(e),kinds[name(e)],gender(e)) - (e) : map(resolve-expr,e) - - resolve-stmt(body) - - defn find (m:Module, kinds:HashTable<Symbol,Kind>) : - defn find-stmt (s:Stmt) -> Stmt : - match(s) : - (s:DefWire) : kinds[name(s)] = WireKind() - (s:DefPoison) : kinds[name(s)] = PoisonKind() - (s:DefNode) : kinds[name(s)] = NodeKind() - (s:DefRegister) : kinds[name(s)] = RegKind() - (s:WDefInstance) : kinds[name(s)] = InstanceKind() - (s:DefMemory) : kinds[name(s)] = MemKind(append-all([readers(s) writers(s) readwriters(s)])) - (s) : false - map(find-stmt,s) - - for p in ports(m) do : - kinds[name(p)] = PortKind() - match(m) : - (m:InModule) : find-stmt(body(m)) - (m:ExModule) : false - - defn resolve-kinds (m:Module, c:Circuit) -> Module : - val kinds = HashTable<Symbol,Kind>(symbol-hash) - find(m,kinds) - match(m) : - (m:InModule) : - val body! = resolve(body(m),kinds) - InModule(info(m),name(m),ports(m),body!) - (m:ExModule) : ExModule(info(m),name(m),ports(m)) - - Circuit(info(c),modules*, main(c)) where : - val modules* = - for m in modules(c) map : - resolve-kinds(m,c) - -;============== INFER TYPES ================================ - -; ------------------ Utils ------------------------- - -defn set-type (s:Stmt,t:Type) -> Stmt : - match(s) : - (s:DefWire) : DefWire(info(s),name(s),t) - (s:DefRegister) : DefRegister(info(s),name(s),t,clock(s),reset(s),init(s)) - (s:DefMemory) : DefMemory(info(s),name(s),t,depth(s),write-latency(s),read-latency(s),readers(s),writers(s),readwriters(s)) - (s:DefNode) : s - (s:DefPoison) : DefPoison(info(s),name(s),t) - - -; ------------------ Pass ------------------------- -public defstruct InferTypes <: Pass -public defmethod pass (b:InferTypes) -> (Circuit -> Circuit) : infer-types -public defmethod name (b:InferTypes) -> String : "Infer Types" -public defmethod short-name (b:InferTypes) -> String : "infer-types" - -defn infer-types (c:Circuit) -> Circuit : - val module-types = HashTable<Symbol,Type>(symbol-hash) - defn infer-types (m:Module) -> Module : - val types = HashTable<Symbol,Type>(symbol-hash) - defn infer-types-e (e:Expression) -> Expression : - match(map(infer-types-e,e)) : - (e:ValidIf) : ValidIf(cond(e),value(e),type(value(e))) - (e:WRef) : WRef(name(e), types[name(e)],kind(e),gender(e)) - (e:WSubField) : WSubField(exp(e),name(e),field-type(type(exp(e)),name(e)),gender(e)) - (e:WSubIndex) : WSubIndex(exp(e),value(e),sub-type(type(exp(e))),gender(e)) - (e:WSubAccess) : WSubAccess(exp(e),index(e),sub-type(type(exp(e))),gender(e)) - (e:DoPrim) : set-primop-type(e) - (e:Mux) : Mux(cond(e),tval(e),fval(e),mux-type-and-widths(tval(e),fval(e))) - (e:UIntValue|SIntValue) : e - defn infer-types-s (s:Stmt) -> Stmt : - match(s) : - (s:DefRegister) : - val t = remove-unknowns(get-type(s)) - types[name(s)] = t - map(infer-types-e,set-type(s,t)) - (s:DefWire|DefPoison|DefNode) : - val s* = map(infer-types-e,s) - val t = remove-unknowns(get-type(s*)) - types[name(s*)] = t - set-type(s*,t) - (s:DefMemory) : - val t = remove-unknowns(get-type(s)) - types[name(s)] = t - val dt = remove-unknowns(data-type(s)) - set-type(s,dt) - (s:WDefInstance) : - types[name(s)] = module-types[module(s)] - WDefInstance(info(s),name(s),module(s),module-types[module(s)]) - (s) : map{infer-types-e,_} $ map(infer-types-s,s) - for p in ports(m) do : - types[name(p)] = type(p) - match(m) : - (m:InModule) : - InModule(info(m),name(m),ports(m),infer-types-s(body(m))) - (m:ExModule) : m - - ; MAIN - val modules* = - for m in modules(c) map : - val ports* = - for p in ports(m) map : - Port(info(p),name(p),direction(p),remove-unknowns(type(p))) - match(m) : - (m:InModule) : InModule(info(m),name(m),ports*,body(m)) - (m:ExModule) : ExModule(info(m),name(m),ports*) - - for m in modules* do : - module-types[name(m)] = module-type(m) - Circuit{info(c), _, main(c) } $ - for m in modules* map : - infer-types(m) - -;============= RESOLVE GENDER ============================ -; To ensure a proper circuit, we must ensure that assignments -; only work on expressions that can be assigned to. Similarly, -; we must ensure that only expressions that can be read from -; are used to assign from. This invariant requires each -; expression's gender to be inferred. -; Various elements can be bi-gender (e.g. wires) and can -; thus be treated as either female or male. Conversely, some -; elements are single-gender (e.g. accessors, ports). -public defstruct ResolveGenders <: Pass -public defmethod pass (b:ResolveGenders) -> (Circuit -> Circuit) : resolve-genders -public defmethod name (b:ResolveGenders) -> String : "Resolve Genders" -public defmethod short-name (b:ResolveGenders) -> String : "resolve-genders" - -defn resolve-genders (c:Circuit) : - defn resolve-e (e:Expression,g:Gender) -> Expression : - match(e) : - (e:WRef) : WRef(name(e),type(e),kind(e),g) - (e:WSubField) : - val exp* = - switch { _ == field-flip(type(exp(e)),name(e)) } : - DEFAULT : resolve-e(exp(e),g) - REVERSE : resolve-e(exp(e),swap(g)) - WSubField(exp*,name(e),type(e),g) - (e:WSubIndex) : - val exp* = resolve-e(exp(e),g) - WSubIndex(exp*,value(e),type(e),g) - (e:WSubAccess) : - val exp* = resolve-e(exp(e),g) - val index* = resolve-e(index(e),MALE) - WSubAccess(exp*,index*,type(e),g) - (e) : map(resolve-e{_,g},e) - - defn resolve-s (s:Stmt) -> Stmt : - match(s) : - (s:IsInvalid) : - val exp* = resolve-e(exp(s),FEMALE) - IsInvalid(info(s),exp*) - (s:Connect) : - val loc* = resolve-e(loc(s),FEMALE) - val exp* = resolve-e(exp(s),MALE) - Connect(info(s),loc*,exp*) - (s:BulkConnect) : - val loc* = resolve-e(loc(s),FEMALE) - val exp* = resolve-e(exp(s),MALE) - BulkConnect(info(s),loc*,exp*) - (s) : - map{resolve-s,_} $ map(resolve-e{_,MALE},s) - Circuit(info(c),modules*, main(c)) where : - val modules* = - for m in modules(c) map : - match(m) : - (m:InModule) : - val body* = resolve-s(body(m)) - InModule(info(m),name(m),ports(m),body*) - (m:ExModule) : m - -;============= Pull Muxes =============== - -public defstruct PullMuxes <: Pass -public defmethod pass (b:PullMuxes) -> (Circuit -> Circuit) : pull-muxes -public defmethod name (b:PullMuxes) -> String : "Pull Muxes" -public defmethod short-name (b:PullMuxes) -> String : "pull-muxes" - -defn pull-muxes (c:Circuit) -> Circuit : - defn pull-muxes-e (e:Expression) -> Expression : - map{pull-muxes-e,_} $ match(map(pull-muxes-e,e)) : - (e:WRef) : e - (e:WSubField) : - match(exp(e)) : - (e*:Mux) : Mux(cond(e*),WSubField(tval(e*),name(e),type(e),gender(e)),WSubField(fval(e*),name(e),type(e),gender(e)),type(e)) - (e*:ValidIf) : ValidIf(cond(e*),WSubField(value(e*),name(e),type(e),gender(e)),type(e)) - (e*) : e - (e:WSubIndex) : - match(exp(e)) : - (e*:Mux) : Mux(cond(e*),WSubIndex(tval(e*),value(e),type(e),gender(e)),WSubIndex(fval(e*),value(e),type(e),gender(e)),type(e)) - (e*:ValidIf) : ValidIf(cond(e*),WSubIndex(value(e*),value(e),type(e),gender(e)),type(e)) - (e*) : e - (e:WSubAccess) : - match(exp(e)) : - (e*:Mux) : Mux(cond(e*),WSubAccess(tval(e*),index(e),type(e),gender(e)),WSubAccess(fval(e*),index(e),type(e),gender(e)),type(e)) - (e*:ValidIf) : ValidIf(cond(e*),WSubAccess(value(e*),index(e),type(e),gender(e)),type(e)) - (e*) : e - (e:Mux) : e - (e:ValidIf) : e - (e) : e - - defn pull-muxes (s:Stmt) -> Stmt : - map(pull-muxes-e,map(pull-muxes,s)) - - Circuit{info(c),_,main(c)} $ - for m in modules(c) map : - match(m) : - (m:InModule) : InModule(info(m),name(m),ports(m),pull-muxes(body(m))) - (m:ExModule) : m - -;================ EXPAND CONNECTS ================== -public defstruct ExpandConnects <: Pass -public defmethod pass (b:ExpandConnects) -> (Circuit -> Circuit) : expand-connects -public defmethod name (b:ExpandConnects) -> String : "Expand Connects" -public defmethod short-name (b:ExpandConnects) -> String : "expand-connects" - -;---------------- UTILS ------------------ - -defn get-size (e:Expression) -> Int : get-size(type(e)) -defn get-flip (t:Type, i:Int, f:Flip) -> Flip : - if i >= get-size(t) : error("Shouldn't be here") - val x = match(t) : - (t:UIntType|SIntType|ClockType) : f - (t:BundleType) : label<Flip> ret : - var n = i - for x in fields(t) do : - if n < get-size(type(x)) : - ret(get-flip(type(x),n,flip(x) * f)) - else : - n = n - get-size(type(x)) - error("Shouldn't be here") - (t:VectorType) : label<Flip> ret : - var n = i - for j in 0 to size(t) do : - if n < get-size(type(t)) : - ret(get-flip(type(t),n,f)) - else : - n = n - get-size(type(t)) - error("Shouldn't be here") - x - -defn get-point (e:Expression) -> Int : - match(e) : - (e:WRef) : 0 - (e:WSubField) : - var i = 0 - for f in fields(type(exp(e)) as BundleType) find : - val b = name(f) == name(e) - if not b : i = i + get-size(type(f)) - b - i - (e:WSubIndex) : - value(e) * get-size(e) - (e:WSubAccess) : - get-point(exp(e)) - -defn create-exps (n:Symbol, t:Type) -> List<Expression> : - create-exps(WRef(n,t,ExpKind(),UNKNOWN-GENDER)) -defn create-exps (e:Expression) -> List<Expression> : - match(e) : - (e:Mux) : - for (e1 in create-exps(tval(e)), e2 in create-exps(fval(e))) map : - Mux(cond(e),e1,e2,mux-type-and-widths(e1,e2)) - (e:ValidIf) : - for e1 in create-exps(value(e)) map : - ValidIf(cond(e),e1,type(e1)) - (e) : - match(type(e)) : - (t:UIntType|SIntType|ClockType) : list(e) - (t:BundleType) : - for f in fields(t) map-append : - create-exps(WSubField(e,name(f),type(f),gender(e) * flip(f))) - (t:VectorType) : - for i in 0 to size(t) map-append : - create-exps(WSubIndex(e,i,type(t),gender(e))) - -defn gexp-hash (e:Expression) -> Int : - turn-off-debug(false) - val ls = to-list([mname `.... e `.... gender(e) `.... type(e)]) - ;val ls = to-list([e `.... gender(e) `.... type(e)]) - val i = symbol-hash(symbol-join(ls)) - ;val i = symbol-hash(to-symbol(to-string(e))) - turn-on-debug(false) - i -val hashed-create-exps = HashTable<Expression,List<Expression>>(gexp-hash) -defn fast-create-exps (n:Symbol, t:Type) -> List<Expression> : - fast-create-exps(WRef(n,t,ExpKind(),UNKNOWN-GENDER)) -defn fast-create-exps (e:Expression) -> List<Expression> : - if key?(hashed-create-exps,e) : - hashed-create-exps[e] - else : - match(e) : - (e:Mux) : - val x = for (e1 in create-exps(tval(e)), e2 in create-exps(fval(e))) map : - Mux(cond(e),e1,e2,mux-type-and-widths(e1,e2)) - hashed-create-exps[e] = x - x - (e:ValidIf) : - val x = for e1 in create-exps(value(e)) map : - ValidIf(cond(e),e1,type(e1)) - hashed-create-exps[e] = x - x - (e) : - val es = Vector<List<Expression>>() - match(type(e)) : - (t:UIntType|SIntType|ClockType) : add(es,list(e)) - (t:BundleType) : - for f in fields(t) do : - add(es,fast-create-exps(WSubField(e,name(f),type(f),gender(e) * flip(f)))) - (t:VectorType) : - for i in 0 to size(t) do : - add(es,fast-create-exps(WSubIndex(e,i,type(t),gender(e)))) - val x = append-all(es) - hashed-create-exps[e] = x - x - -;---------------- Pass --------------------- - -defn expand-connects (c:Circuit) -> Circuit : - defn expand-connects (m:InModule) -> InModule : - mname = name(m) - val genders = HashTable<Symbol,Gender>(symbol-hash) - defn expand-s (s:Stmt) -> Stmt : - defn set-gender (e:Expression) -> Expression : - match(map(set-gender,e)) : - (e:WRef) : WRef(name(e),type(e),kind(e),genders[name(e)]) - (e:WSubField) : - val f = {_ as Field} $ - for f in fields(type(exp(e)) as BundleType) find : - name(f) == name(e) - val gender* = gender(exp(e)) * flip(f) - WSubField(exp(e),name(e),type(e),gender*) - (e:WSubIndex) : WSubIndex(exp(e),value(e),type(e),gender(exp(e))) - (e:WSubAccess) : WSubAccess(exp(e),index(e),type(e),gender(exp(e))) - (e) : e - match(s) : - (s:DefWire|DefRegister) : - genders[name(s)] = BI-GENDER - s - (s:WDefInstance|DefMemory|DefPoison|DefNode) : - genders[name(s)] = MALE - s - (s:IsInvalid) : - val n = get-size(exp(s)) - val invalids = Vector<Stmt>() - val exps = create-exps(exp(s)) - for i in 0 to n do : - val exp* = exps[i] - val gexp* = set-gender(exp*) - switch { _ == gender(gexp*) } : - BI-GENDER : add(invalids,IsInvalid(info(s),exp*)) - FEMALE : add(invalids,IsInvalid(info(s),exp*)) - else : false - if length(invalids) == 0 : Empty() - else if length(invalids) == 1 : invalids[0] - else : Begin(to-list(invalids)) - (s:Connect) : - val n = get-size(loc(s)) - val connects = Vector<Stmt>() - val locs = create-exps(loc(s)) - val exps = create-exps(exp(s)) - for i in 0 to n do : - val loc* = locs[i] - val exp* = exps[i] - add{connects,_} $ - switch { _ == get-flip(type(loc(s)),i,DEFAULT) } : - DEFAULT : Connect(info(s),loc*,exp*) - REVERSE : Connect(info(s),exp*,loc*) - Begin(to-list(connects)) - (s:BulkConnect) : - val ls = get-valid-points(type(loc(s)),type(exp(s)),DEFAULT,DEFAULT) - val connects = Vector<Stmt>() - val locs = create-exps(loc(s)) - val exps = create-exps(exp(s)) - for x in ls do : - val loc* = locs[x[0]] - val exp* = exps[x[1]] - add{connects,_} $ - switch { _ == get-flip(type(loc(s)),x[0],DEFAULT) } : - DEFAULT : Connect(info(s),loc*,exp*) - REVERSE : Connect(info(s),exp*,loc*) - Begin(to-list(connects)) - (s) : map(expand-s,s) - - for p in ports(m) do : - genders[name(p)] = to-gender(direction(p)) - InModule(info(m),name(m),ports(m),expand-s(body(m))) - - Circuit(info(c),modules*, main(c)) where : - val modules* = - for m in modules(c) map : - match(m) : - (m:ExModule) : m - (m:InModule) : expand-connects(m) - - -;;;================ REPLACE INDEXERS ========================= -; This pass inlines all accessors to non-memory vector typed -; components. - -public defstruct RemoveAccesses <: Pass -public defmethod pass (b:RemoveAccesses) -> (Circuit -> Circuit) : remove-access -public defmethod name (b:RemoveAccesses) -> String : "Remove Accesses" -public defmethod short-name (b:RemoveAccesses) -> String : "remove-access" - -defstruct Location : - base : Expression - guard : Expression -defmethod print (o:OutputStream,x:Location) : - print-all(o,["[" base(x) " , " guard(x) "]"]) - -defn get-locations (e:Expression) -> List<Location> : - match(e) : - (e:WRef) : map(Location{_,one},create-exps(e)) - (e:WSubIndex|WSubField) : - val ls = get-locations(exp(e)) - val start = get-point(e) - val end = start + get-size(e) - val stride = get-size(exp(e)) - val ls* = Vector<Location>() - var c = 0 - for i in 0 to length(ls) do : - if (i % stride >= start and i % stride < end) : - add(ls*,ls[i]) - to-list(ls*) - (e:WSubAccess) : - val ls = get-locations(exp(e)) - val stride = get-size(e) - val wrap = size(type(exp(e)) as VectorType) - val ls* = Vector<Location>() - var c = 0 - for i in 0 to length(ls) do : - if c % wrap == 0 : c = 0 - val base* = base(ls[i]) - val guard* = AND(guard(ls[i]),EQV(uint(c),index(e))) - add(ls*,Location(base*,guard*)) - if (i + 1) % stride == 0 : c = c + 1 - to-list(ls*) - -defn has-access? (e:Expression) -> True|False : - var ret = false - defn rec-has-access (e:Expression) -> Expression : - match(e) : - (e:WSubAccess) : - ret = true - e - (e) : map(rec-has-access,e) - rec-has-access(e) - ret - -defn remove-access (c:Circuit) : - defn remove-m (m:InModule) -> InModule : - val sh = get-sym-hash(m,keys(v-keywords)) - mname = name(m) - defn remove-s (s:Stmt) -> Stmt : - val stmts = Vector<Stmt>() - defn create-temp (e:Expression) -> Expression : - val n = firrtl-gensym(`GEN,sh) - add(stmts,DefWire(info(s),n,type(e))) - WRef(n,type(e),kind(e),gender(e)) - defn remove-e (e:Expression) -> Expression : ;NOT RECURSIVE (except primops) INTENTIONALLY! - match(e) : - (e:DoPrim) : map(remove-e,e) - (e:Mux) : map(remove-e,e) - (e:ValidIf) : map(remove-e,e) - (e:UIntValue|SIntValue) : e - (e) : - if has-access?(e) : - val rs = get-locations(e) - val foo = for x in rs find : - (guard(x)) != one - if foo == false : error("Shouldn't be here") - else : - val temp = create-temp(e) - val temps = create-exps(temp) - defn get-temp (i:Int) : - temps[i % length(temps)] - for (x in rs, i in 0 to false) do : - if i < length(temps) : - add(stmts,Connect(info(s),get-temp(i),base(x))) - else : - add(stmts,Conditionally(info(s),guard(x),Connect(info(s),get-temp(i),base(x)),Empty())) - temp - else : e - val s* = match(s) : - (s:Connect) : - if has-access?(loc(s)) : - val ls = get-locations(loc(s)) - val loc* = - if length(ls) == 1 and guard(head(ls)) == one : loc(s) - else : - val temp = create-temp(loc(s)) - for x in ls do : - add(stmts,Conditionally(info(s),guard(x),Connect(info(s),base(x),temp),Empty())) - temp - Connect(info(s),loc*,remove-e(exp(s))) - else : - Connect(info(s),loc(s),remove-e(exp(s))) - (s) : map{remove-s,_} $ map(remove-e,s) - add(stmts,s*) - if length(stmts) != 1 : Begin(to-list(stmts)) - else : stmts[0] - - InModule(info(m),name(m),ports(m),remove-s(body(m))) - - Circuit(info(c),modules*, main(c)) where : - val modules* = - for m in modules(c) map : - match(m) : - (m:ExModule) : m - (m:InModule) : remove-m(m) - -;;================ EXPAND WHENS ============================= -; This pass does three things: remove last connect semantics, -; remove conditional blocks, and eliminate concept of scoping. - -public defstruct ExpandWhens <: Pass -public defmethod pass (b:ExpandWhens) -> (Circuit -> Circuit) : expand-whens -public defmethod name (b:ExpandWhens) -> String : "Expand Whens" -public defmethod short-name (b:ExpandWhens) -> String : "expand-whens" - -; ========== Expand When Utilz ========== - -defn get-entries (hash:HashTable<Expression,Expression>,exps:Streamable<Expression>) -> HashTable<Expression,Expression> : - val hash* = HashTable<Expression,Expression>(exp-hash) - for e in exps do : - val value = get?(hash,e,false) - match(value) : - (value:Expression) : hash*[e] = value - (value:False) : false - hash* -defn get-female-refs (n:Symbol,t:Type,g:Gender) -> List<Expression> : - val exps = create-exps(WRef(n,t,ExpKind(),g)) - val exps* = Vector<Expression>() - for i in 0 to length(exps) do : - switch { _ == get-gender(t,i,g)} : - BI-GENDER : add(exps*,exps[i]) - FEMALE : add(exps*,exps[i]) - else : false - to-list(exps*) -defn get-gender (t:Type, i:Int, g:Gender) -> Gender : - val f = get-flip(t,i,DEFAULT) - g * f -defn print-hash (h:HashTable<Expression,Expression>) : - for x in h do : - println(x) - -; ------------ Pass ------------------- -defn expand-whens (c:Circuit) -> Circuit : - defn void-all (m:InModule) -> InModule : - mname = name(m) - defn void-all-s (s:Stmt) -> Stmt : - match(s) : - (s:DefWire|DefRegister|WDefInstance|DefMemory) : - val voids = Vector<Stmt>() - for e in get-female-refs(name(s),get-type(s),get-gender(s)) do : - add(voids,Connect(info(s),e,WVoid())) - Begin(List(s,to-list(voids))) - (s) : map(void-all-s,s) - val voids = Vector<Stmt>() - for p in ports(m) do : - for e in get-female-refs(name(p),type(p),get-gender(p)) do : - add(voids,Connect(info(p),e,WVoid())) - val body* = void-all-s(body(m)) - InModule(info(m),name(m),ports(m),Begin(list(Begin(to-list(voids)),body*))) - - defn expand-whens (m:InModule) -> [HashTable<Expression,Expression> Vector<Stmt>] : - val simlist = Vector<Stmt>() - mname = name(m) - defn expand-whens (s:Stmt,netlist:HashTable<Expression,Expression>,p:Expression) -> Stmt : - match(s) : - (s:Connect) : netlist[loc(s)] = exp(s) - (s:IsInvalid) : netlist[exp(s)] = WInvalid() - (s:Conditionally) : - val exps = Vector<Expression>() - defn prefetch (s:Stmt) -> Stmt: - match(s) : - (s:Connect) : - add(exps,loc(s)) - s - (s) : map(prefetch,s) - prefetch(conseq(s)) - val c-netlist = get-entries(netlist,exps) - expand-whens(conseq(s),c-netlist,AND(p,pred(s))) - expand-whens(alt(s),netlist,AND(p,NOT(pred(s)))) - for lvalue in keys(c-netlist) do : - val value = get?(netlist,lvalue,false) - match(value) : - (value:Expression) : - val tv = c-netlist[lvalue] - val fv = value - val res = match(tv,fv) : - (tv:WInvalid,fv:WInvalid) : WInvalid() - (tv:WInvalid,fv) : ValidIf(NOT(pred(s)),fv,type(fv)) - (tv,fv:WInvalid) : ValidIf(pred(s),tv,type(tv)) - (tv,fv) : Mux(pred(s),tv,fv,mux-type-and-widths(tv,fv)) - netlist[lvalue] = res - (value:False) : - netlist[lvalue] = c-netlist[lvalue] - (s:Print) : - if p == one : add(simlist,s) - else : add(simlist,Print(info(s),string(s),args(s),clk(s),AND(p,en(s)))) - (s:Stop) : - if p == one : add(simlist,s) - else : add(simlist,Stop(info(s),ret(s),clk(s),AND(p,en(s)))) - (s) : map(expand-whens{_,netlist,p},s) - s - val netlist = HashTable<Expression,Expression>(exp-hash) - expand-whens(body(m),netlist,one) - - ;println("Netlist:") - ;println(netlist) - ;println("Simlist:") - ;println(simlist) - [ netlist simlist ] - - defn create-module (netlist:HashTable<Expression,Expression>,simlist:Vector<Stmt>,m:InModule) -> InModule : - mname = name(m) - val stmts = Vector<Stmt>() - val connections = Vector<Stmt>() - defn replace-void (e:Expression,rvalue:Expression) -> Expression : - match(rvalue) : - (rv:WVoid) : e - (rv) : map(replace-void{e,_},rv) - defn create (s:Stmt) -> Stmt : - match(s) : - (s:DefWire|DefRegister|WDefInstance|DefMemory) : - add(stmts,s) - for e in get-female-refs(name(s),get-type(s),get-gender(s)) do : - val rvalue = - if s typeof DefRegister : replace-void(e,netlist[e]) - else : netlist[e] - val con = match(rvalue) : - (rvalue:WInvalid) : IsInvalid(info(s),e) - (rvalue) : Connect(info(s),e,rvalue) - add(connections,con) - (s:DefPoison|DefNode) : - add(stmts,s) - (s) : map(create,s) - s - create(body(m)) - for p in ports(m) do : - for e in get-female-refs(name(p),type(p),get-gender(p)) do : - val rvalue = netlist[e] - val con = match(rvalue) : - (rvalue:WInvalid) : IsInvalid(info(p),e) - (rvalue) : Connect(info(p),e,rvalue) - add(connections,con) - for x in simlist do : - add(stmts,x) - InModule(info(m),name(m),ports(m),Begin(list(Begin(to-list(stmts)),Begin(to-list(connections))))) - - val voided-modules = - for m in modules(c) map : - match(m) : - (m:ExModule) : m - (m:InModule) : - val m* = void-all(m as InModule) - m* - val modules* = - for m in voided-modules map : - match(m) : - (m:ExModule) : m - (m:InModule) : - val [netlist simlist] = expand-whens(m) - create-module(netlist,simlist,m) - Circuit(info(c),modules*,main(c)) - -;;================ Module Duplication ================== -; Duplicates modules so that no module is instantiated -; more than once. - -;public defstruct ModuleDuplication <: Pass -;public defmethod pass (b:ModuleDuplication) -> (Circuit -> Circuit) : module-duplication -;public defmethod name (b:ModuleDuplication) -> String : "Module Duplication" -;public defmethod short-name (b:ModuleDuplication) -> String : "mod-dup" -; -;;------------ Helper Functions ------------- -; -;;------------ Pass ------------------ -; -;public defn module-duplication (c:Circuit) : -; val modules* = Vector<Module>() -; val m-names = HashTable<Symbol,Int>(symbol-hash) -; defn rename (n:Symbol) -> Symbol : -; val int = get?(m-names,n,0) -; m-names[n] = int + 1 -; val n* = symbol-join([n module-expand-delin int]) -; val m = for x in modules(c) find : name(x) == n -; match(m) : -; (m:InModule) : add(modules*,InModule(info(m),n*, ports(m), rename-s(body(m)))) -; (m:ExModule) : add(modules*,ExModule(info(m),n*, ports(m))) -; (m:False) : error("Shouldn't be here") -; n* -; -; defn rename-e (e:Expression) -> Expression : -; match(e) : -; (e:Ref) : Ref(rename(name(e)),type(e)) -; (e) : error("Shouldn't be here") -; defn rename-s (s:Stmt) -> Stmt : -; match(s) : -; (s:WDefInstance) : WDefInstance(info(s),name(s),rename-e(module(s))) -; (s) : map(rename-s,s) -; -; val top = for m in modules(c) find : name(m) == main(c) -; match(top) : -; (m:InModule) : add(modules*,InModule(info(m),name(m), ports(m), rename-s(body(m)))) -; (m:ExModule) : m -; (m:False) : error("Shouldn't be here") -; -; Circuit(info(c),to-list(modules*), main(c)) -; -; -;;;================ Deadcode Elimination =================== -;; Walks the circuit, starting from the outputs from the top -;; level module. All components that are not reached are -;; deleted -; -;public defstruct DeadcodeElimination <: Pass -;public defmethod pass (b:DeadcodeElimination) -> (Circuit -> Circuit) : deadcode-elimination -;public defmethod name (b:DeadcodeElimination) -> String : "Deadcode Elimination" -;public defmethod short-name (b:DeadcodeElimination) -> String : "deadcode-elim" -; -;;------------ Helper Functions ------------- -; -;;------------ Pass ------------------ -; -;public defn deadcode-elimination (c:Circuit) : c -; -;;;================ INFER WIDTHS ============================= -;; First, you replace all unknown widths with a unique width -;; variable. -;; Then, you collect all width constraints. -;; Then, you solve width constraints. -;; Finally, you replace all width variables with the solved -;; widths. -;; Low FIRRTL Pass. -public defstruct InferWidths <: Pass -public defmethod pass (b:InferWidths) -> (Circuit -> Circuit) : infer-widths -public defmethod name (b:InferWidths) -> String : "Infer Widths" -public defmethod short-name (b:InferWidths) -> String : "infer-widths" - -public definterface Constraint -public defstruct WGeq <: Constraint : - loc : Width - exp : Width -public defmethod print (o:OutputStream, c:WGeq) : - print-all(o,[ loc(c) " >= " exp(c)]) -defn apply (a:Int|False,b:Int|False, f: (Int,Int) -> Int) -> Int|False : - if a typeof Int and b typeof Int : f(a as Int, b as Int) - else : false - -defn solve-constraints (l:List<WGeq>) -> HashTable<Symbol,Width> : - defn contains? (n:Symbol,h:HashTable<Symbol,?>) -> True|False : key?(h,n) - defn make-unique (ls:List<WGeq>) -> HashTable<Symbol,Width> : - val h = HashTable<Symbol,Width>(symbol-hash) - for g in ls do : - match(loc(g)) : - (w:VarWidth) : - val n = name(w) - if contains?(n,h) : h[n] = MaxWidth(list(exp(g),h[n])) - else : h[n] = exp(g) - (w) : w - h - defn simplify (w:Width) -> Width : - match(map(simplify,w)) : - (w:MinWidth) : - val v = Vector<Width>() - for w* in args(w) do : - match(w*) : - (w*:MinWidth) : - for x in args(w*) do : add(v,x) - (w*) : add(v,w*) - MinWidth(unique(v)) - (w:MaxWidth) : - val v = Vector<Width>() - for w* in args(w) do : - match(w*) : - (w*:MaxWidth) : - for x in args(w*) do : add(v,x) - (w*) : add(v,w*) - MaxWidth(unique(v)) - (w:PlusWidth) : - match(arg1(w),arg2(w)) : - (w1:IntWidth,w2:IntWidth) : IntWidth(plus(width(w1),width(w2))) - (w1,w2) : w - (w:MinusWidth) : - match(arg1(w),arg2(w)) : - (w1:IntWidth,w2:IntWidth) : IntWidth(minus(width(w1),width(w2))) - (w1,w2) : w - (w:ExpWidth) : - match(arg1(w)) : - (w1:IntWidth) : IntWidth(pow(to-long(2),width(w1)) - to-long(1)) - (w1) : w - (w) : w - defn substitute (w:Width,h:HashTable<Symbol,Width>) -> Width : - ;println-all-debug(["Substituting for [" w "]"]) - val w* = simplify(w) - ;println-all-debug(["After Simplify: [" w* "]"]) - match(map(substitute{_,h},simplify(w))) : - (w:VarWidth) : - ;println-debug("matched varwidth!") - if contains?(name(w),h) : - ;println-debug("Contained!") - ;println-all-debug(["Width: " w]) - ;println-all-debug(["Accessed: " h[name(w)]]) - val t = simplify(substitute(h[name(w)],h)) - ;val t = h[name(w)] - ;println-all-debug(["Width after sub: " t]) - h[name(w)] = t - t - else : w - (w): - ;println-all-debug(["not varwidth!" w]) - w - defn b-sub (w:Width,h:HashTable<Symbol,Width>) -> Width: - match(map(b-sub{_,h},w)) : - (w:VarWidth) : - if key?(h,name(w)) : h[name(w)] - else : w - (w) : w - defn remove-cycle (n:Symbol,w:Width) -> Width : - ;println-all-debug(["Removing cycle for " n " inside " w]) - val w* = match(map(remove-cycle{n,_},w)) : - (w:MaxWidth) : MaxWidth(to-list(filter({_ != VarWidth(n)},args(w)))) - (w:MinusWidth) : - if arg1(w) == VarWidth(n) : arg1(w) - else : w - (w) : w - ;println-all-debug(["After removing cycle for " n ", returning " w*]) - w* - defn self-rec? (n:Symbol,w:Width) -> True|False : - var has? = false - defn look (w:Width) -> Width : - match(map(look,w)) : - (w:VarWidth) : if name(w) == n : has? = true - (w) : w - w - look(w) - has? - - ; Forward solve - ; Returns a solved list where each constraint undergoes: - ; 1) Continuous Solving (using triangular solving) - ; 2) Remove Cycles - ; 3) Move to solved if not self-recursive - val u = make-unique(l) - println-debug("======== UNIQUE CONSTRAINTS ========") - for x in u do : println-debug(x) - println-debug("====================================") - - val f = HashTable<Symbol,Width>(symbol-hash) - val o = Vector<Symbol>() - for x in u do : - println-debug("==== SOLUTIONS TABLE ====") - for x in f do : println-debug(x) - println-debug("=========================") - - val [n e] = [key(x) value(x)] - - val e-sub = substitute(e,f) - println-debug(["Solving " n " => " e]) - println-debug(["After Substitute: " n " => " e-sub]) - println-debug("==== SOLUTIONS TABLE (Post Substitute) ====") - for x in f do : println-debug(x) - println-debug("=========================") - val e* = remove-cycle{n,_} $ e-sub - ;println-debug(["After Remove Cycle: " n " => " e*]) - if not self-rec?(n,e*) : - ;println-all-debug(["Not rec!: " n " => " e*]) - ;println-all-debug(["Adding [" n "=>" e* "] to Solutions Table"]) - add(o,n) - f[n] = e* - - println-debug("Forward Solved Constraints") - for x in f do : println-debug(x) - - ; Backwards Solve - val b = HashTable<Symbol,Width>(symbol-hash) - for i in (length(o) - 1) through 0 by -1 do : - val n = o[i] - println-all-debug(["SOLVE BACK: [" n " => " f[n] "]"]) - println-debug("==== SOLUTIONS TABLE ====") - for x in b do : println-debug(x) - println-debug("=========================") - val e* = simplify(b-sub(f[n],b)) - println-all-debug(["BACK RETURN: [" n " => " e* "]"]) - b[n] = e* - println-debug("==== SOLUTIONS TABLE (Post backsolve) ====") - for x in b do : println-debug(x) - println-debug("=========================") - b - -public defn width! (t:Type) -> Width : - match(t) : - (t:UIntType) : width(t) - (t:SIntType) : width(t) - (t:ClockType) : IntWidth(1) - (t) : error("No width!") -public defn width! (e:Expression) -> Width : width!(type(e)) - -defn reduce-var-widths (c:Circuit,h:HashTable<Symbol,Width>) -> Circuit : - defn evaluate (w:Width) -> Width : - defn apply (a:Long|False,f:(Long) -> Long) -> Long|False : - if a typeof Long : f(a as Long) - else : false - defn apply (a:Long|False,b:Long|False, f: (Long,Long) -> Long) -> Long|False : - if a typeof Long and b typeof Long : f(a as Long, b as Long) - else : false - defn apply-l (l:List<Long|False>,f:(Long,Long) -> Long) -> Long|False : - if length(l) == 0 : to-long(0) - else : apply(head(l),apply-l(tail(l),f),f) - defn max (a:Long,b:Long) -> Long : - if a >= b : a - else : b - defn min (a:Long,b:Long) -> Long : - if a >= b : b - else : a - defn solve (w:Width) -> False|Long : - match(w) : - (w:VarWidth) : - val w* = get?(h,name(w),false) - match(w*) : - (w:VarWidth) : false - (w:False) : false - (w) : solve(w as Width) - (w:MaxWidth) : apply-l(map(solve,args(w)),max) - (w:MinWidth) : apply-l(map(solve,args(w)),min) - (w:PlusWidth) : apply(solve(arg1(w)),solve(arg2(w)),{plus(_,_)}) - (w:MinusWidth) : apply(solve(arg1(w)),solve(arg2(w)),{minus(_,_)}) - (w:ExpWidth) : apply(to-long(2),solve(arg1(w)),{minus(pow(_,_),to-long(1))}) - (w:IntWidth) : width(w) - (w) : - println(w) - error("Shouldn't be here") - - val s = solve(w) - match(s) : - (s:Long) : IntWidth(s) - (s) : w - - defn reduce-var-widths-w (w:Width) -> Width : - println-all-debug(["REPLACE: " w]) - val w* = evaluate(w) - println-all-debug(["WITH: " w*]) - w* - - val modules* = for m in modules(c) map : - val ports* = for p in ports(m) map : - Port(info(p),name(p),direction(p),mapr(reduce-var-widths-w,type(p))) - - match(m) : - (m:ExModule) : ExModule(info(m),name(m),ports*) - (m:InModule) : - mname = name(m) - InModule(info(m),name(m),ports*,mapr(reduce-var-widths-w,body(m))) - - Circuit(info(c),modules*,main(c)) - -defn infer-widths (c:Circuit) -> Circuit : - val v = Vector<WGeq>() - defn constrain (w1:Width,w2:Width) -> False : constrain(w1,w2,DEFAULT) - defn constrain (w1:Width,w2:Width,f:Flip) -> False : - switch { _ == f } : - DEFAULT : add(v,WGeq(w1,w2)) - REVERSE : add(v,WGeq(w2,w1)) - defn get-constraints (t1:Type,t2:Type,f:Flip) -> False : - match(t1,t2) : - (t1:UIntType,t2:UIntType) : constrain(width(t1),width(t2)) - (t1:SIntType,t2:SIntType) : constrain(width(t1),width(t2)) - (t1:BundleType,t2:BundleType) : - for (f1 in fields(t1),f2 in fields(t2)) do : - get-constraints(type(f1),type(f2),flip(f1) * f) - (t1:VectorType,t2:VectorType) : - get-constraints(type(t1),type(t2),f) - defn get-constraints-e (e:Expression) -> Expression : - match(map(get-constraints-e,e)) : - (e:Mux) : - constrain(width!(cond(e)),ONE) - constrain(ONE,width!(cond(e))) - e - (e) : e - defn get-constraints (s:Stmt) -> Stmt : - match(map(get-constraints-e,s)) : - (s:Connect) : - ;constrain(width!(loc(s)),width!(exp(s))) - ;s - val n = get-size(loc(s)) - val ce-loc = create-exps(loc(s)) - val ce-exp = create-exps(exp(s)) - for i in 0 to n do : - val loc* = ce-loc[i] - val exp* = ce-exp[i] - switch { _ == get-flip(type(loc(s)),i,DEFAULT) } : - DEFAULT : constrain(width!(loc*),width!(exp*)) - REVERSE : constrain(width!(exp*),width!(loc*)) - s - (s:BulkConnect) : - val ls = get-valid-points(type(loc(s)),type(exp(s)),DEFAULT,DEFAULT) - for x in ls do : - ;println(x) - ;println(create-exps(loc(s))) - ;println(create-exps(exp(s))) - val loc* = create-exps(loc(s))[x[0]] - val exp* = create-exps(exp(s))[x[1]] - switch { _ == get-flip(type(loc(s)),x[0],DEFAULT) } : - DEFAULT : constrain(width!(loc*),width!(exp*)) - REVERSE : constrain(width!(exp*),width!(loc*)) - s - (s:DefRegister) : - constrain(width!(reset(s)),ONE) - constrain(ONE,width!(reset(s))) - get-constraints(type(s),type(init(s)),DEFAULT) - s - (s:Conditionally) : - add(v,WGeq(width!(pred(s)),ONE)) - add(v,WGeq(ONE,width!(pred(s)))) - map(get-constraints,s) - (s) : map(get-constraints,s) - - for m in modules(c) do : - match(m) : - (m:InModule) : - mname = name(m) - get-constraints(body(m)) - (m) : false - println-debug("======== ALL CONSTRAINTS ========") - for x in v do : println-debug(x) - println-debug("=================================") - val h = solve-constraints(to-list(v)) - println-debug("======== SOLVED CONSTRAINTS ========") - for x in h do : println-debug(x) - println-debug("====================================") - reduce-var-widths(Circuit(info(c),modules(c),main(c)),h) - -; ================ All Resolving Passes ================ -public defstruct Resolve <: Pass -public defmethod pass (b:Resolve) -> (Circuit -> Circuit) : resolve -public defmethod name (b:Resolve) -> String : "Resolve" -public defmethod short-name (b:Resolve) -> String : "resolve" - -defn resolve (c:Circuit) -> Circuit : - check-width $ - infer-widths $ - check-genders $ - resolve-genders $ - check-types $ - infer-types $ - resolve-kinds $ - to-working-ir(c) - -;;================= Inline Instances ======================== -;; Inlines instances. Assumes module with same name as the -;; Circuit is the top level module -;public defstruct Inline <: Pass -;public defmethod pass (b:Inline) -> (Circuit -> Circuit) : inline-instances -;public defmethod name (b:Inline) -> String : "Inline Instances" -;public defmethod short-name (b:Inline) -> String : "inline-instances" -; -;defn inline-instances (c:Circuit) : -; val h = HashTable<Symbol,InModule>(symbol-hash) -; val h-s = HashTable<Symbol,Stmt>(symbol-hash) -; defn inline-inst (s:Stmt) -> Stmt : -; match(map(inline-inst,s)) : -; (s:WDefInstance) : -; val n = name(module(s) as WRef) -; val m = h[n] -; val body* = -; if key?(h-s,n) : h-s[n] -; else : -; val v = Vector<Stmt>() -; for p in ports(m) do : -; add(v,DefWire(info(s),name(p),type(p))) -; add(v,inline-inst(body(m))) -; Begin(to-list(v)) -; h-s[n] = body* -; rename-s(body*,name(s)) -; (s) : map(inline-inst-e,s) -; defn inline-inst-e (e:Expression) -> Expression : -; match(map(inline-inst-e,e)) : -; (e:WSubField) : -; match(kind(exp(e) as WRef)) : -; (k:InstanceKind) : -; WRef(symbol-join([name(exp(e) as WRef) inline-delin name(e)]),type(e),k,gender(e)) -; (k:MemKind) : e -; (e) : e -; defn rename (ref:Symbol,n:Symbol) -> Symbol : symbol-join([n inline-delin ref]) -; defn rename-e (e:Expression,n:Symbol) -> Expression : -; match(map(rename-e{_,n},e)) : -; (e:WRef) : WRef(rename(name(e),n),type(e),kind(e),gender(e)) -; (e:WSubField) : -; match(kind(exp(e) as WRef)) : -; (k:InstanceKind) : -; WRef(symbol-join([name(exp(e) as WRef) inline-delin name(e)]),type(e),k,gender(e)) -; (k:MemKind) : e -; (e) : e -; defn rename-s (s:Stmt,n:Symbol) -> Stmt : -; map{rename-e{_,n},_} $ match(map(rename-s{_,n},s)) : -; (s:DefWire) : DefWire(info(s),rename(name(s),n),type(s)) -; (s:DefPoison) : DefPoison(info(s),rename(name(s),n),type(s)) -; (s:DefRegister) : DefRegister(info(s),rename(name(s),n),type(s),clock(s),reset(s)) -; (s:WDefInstance) : error("Shouldn't be here") -; (s:DefMemory) : DefMemory(info(s),rename(name(s),n),type(s),seq?(s),clock(s),size(s)) -; (s:DefNode) : DefNode(info(s),rename(name(s),n),value(s)) -; (s) : s -; for m in modules(c) do : -; match(m) : -; (m:ExModule) : error("Cannot inline with external modules") -; (m:InModule) : h[name(m)] = m -; val top = (for m in modules(c) find : name(m) == main(c)) as InModule -; Circuit(info(c),list(InModule(info(top),name(top),ports(top),inline-inst(body(top)))),main(c)) - -;;================= Verilog Wrap ======================== - -; --------- Utils -------------- - -;---------- Pass --------------- -;; Intended to only work on low firrtl -public defstruct VerilogWrap <: Pass -public defmethod pass (b:VerilogWrap) -> (Circuit -> Circuit) : v-wrap -public defmethod name (b:VerilogWrap) -> String : "Verilog Wrap" -public defmethod short-name (b:VerilogWrap) -> String : "verilog-wrap" - -public definterface WPrimOp <: PrimOp -val ADDW-OP = new WPrimOp -val SUBW-OP = new WPrimOp - -defmethod print (o:OutputStream,op:WPrimOp) : - print{o, _} $ switch {op == _} : - ADDW-OP : "addw" - SUBW-OP : "subw" - -defn v-wrap-e (e:Expression) -> Expression : - match(map(v-wrap-e,e)) : - (e:DoPrim) : - defn a0 () : args(e)[0] - if op(e) == TAIL-OP : - match(a0()) : - (e0:DoPrim) : - if op(e0) == ADD-OP : - DoPrim(ADDW-OP,args(e0),list(),type(e)) - else if op(e0) == SUB-OP : - DoPrim(SUBW-OP,args(e0),list(),type(e)) - else : e - (e0) : e - else : e - (e) : e -defn v-wrap-s (s:Stmt) -> Stmt : - map{v-wrap-e,_} $ map(v-wrap-s,s) -defn v-wrap (c:Circuit) -> Circuit : - val modules* = for m in modules(c) map : - match(m) : - (m:InModule) : - mname = name(m) - InModule(info(m),name(m),ports(m),v-wrap-s(body(m))) - (m:ExModule) : m - Circuit(info(c),modules*,main(c)) - -;;================= Split Expressions ======================== - -;; Intended to only work on low firrtl -public defstruct SplitExp <: Pass -public defmethod pass (b:SplitExp) -> (Circuit -> Circuit) : split-exp -public defmethod name (b:SplitExp) -> String : "Split Expressions" -public defmethod short-name (b:SplitExp) -> String : "split-expressions" - -defn split-exp (m:InModule) -> InModule : - mname = name(m) - val v = Vector<Stmt>() - val sh = get-sym-hash(m,keys(v-keywords)) - defn split-exp-s (s:Stmt) -> Stmt : - val base = match(s) : - (s:Connect) : lowered-name(loc(s)) - (s:DefNode) : name(s) - (s:DefRegister) : name(s) - (s) : `F - defn split (e:Expression) -> Expression : - val n = firrtl-gensym(`GEN,sh) - add(v,DefNode(info(s),n,e)) - WRef(n,type(e),kind(e),gender(e)) - defn split-exp-e (e:Expression,i:Int) -> Expression : - match(map(split-exp-e{_,i + 1},e)) : - (e:DoPrim) : - if i > 0 : split(e) - else : e - (e) : e - match(s) : - (s:Begin) : map(split-exp-s,s) - (s:Print) : - val s* = map(split-exp-e{_,1},s) - add(v,s*) - s* - (s) : - val s* = map(split-exp-e{_,0},s) - add(v,s*) - s* - split-exp-s(body(m)) - InModule(info(m),name(m),ports(m),Begin(to-list(v))) - -defn split-exp (c:Circuit) -> Circuit : - val modules* = for m in modules(c) map : - match(m) : - (m:InModule) : split-exp(m) - (m:ExModule) : m - Circuit(info(c),modules*,main(c)) - - -;;================= Special Rename ======================== -;; Returns a new Circuit with only real IR nodes. -;public defstruct SpecialRename <: Pass : -; original-sym : Symbol -; new-sym : Symbol -;public defmethod pass (b:SpecialRename) -> (Circuit -> Circuit) : special-rename{original-sym(b),new-sym(b),_:Circuit} -;public defmethod name (b:SpecialRename) -> String : "Special Rename" -;public defmethod short-name (b:SpecialRename) -> String : "special-rename" -; -;public defn special-rename (original-sym:Symbol,new-sym:Symbol,c:Circuit) : -; defn rename (s:Symbol) -> Symbol : -; val y = Vector<String>() -; val os = to-string $ original-sym -; val ns = to-string $ new-sym -; defn rename (st:String) -> False : -; if st == os : -; add(y,ns) -; else if length(st) <= length(os) : -; add(y,st) -; else : -; if substring(st,0,length(os)) == os : -; add(y,ns) -; ;println(st) -; ;println(substring(st,length(os),length(st))) -; rename(substring(st,length(os),length(st))) -; else : -; add(y,substring(st,0,1)) -; rename(substring(st,1,length(st))) -; rename(to-string(s)) -; to-symbol $ string-join $ to-list(y) -; defn to-type (t:Type) -> Type : -; match(map(to-type,t)) : -; (t:BundleType) : BundleType $ -; for f in fields(t) map : Field(rename(name(f)),flip(f),type(f)) -; (t) : t -; defn to-exp (e:Expression) -> Expression : -; map{to-type,_} $ match(map(to-exp,e)) : -; (e:Ref) : Ref(rename(name(e)), type(e)) -; (e:Subfield) : Subfield(exp(e),rename(name(e)),type(e)) -; (e) : e -; defn to-stmt (s:Stmt) -> Stmt : -; map{to-type,_} $ match(map(to-exp,s)) : -; (s:DefWire) : DefWire(info(s),rename(name(s)),type(s)) -; (s:DefPoison) : DefPoison(info(s),rename(name(s)),type(s)) -; (s:DefRegister) : DefRegister(info(s),rename(name(s)),type(s),clock(s),reset(s)) -; (s:WDefInstance) : WDefInstance(info(s),rename(name(s)),module(s)) -; (s:DefMemory) : DefMemory(info(s),rename(name(s)),type(s),seq?(s),clock(s),size(s)) -; (s:DefNode) : DefNode(info(s),rename(name(s)),value(s)) -; (s:DefAccessor) : DefAccessor(info(s),rename(name(s)),source(s),index(s),acc-dir(s)) -; (s) : map(to-stmt,s) -; -; defn to-port (p:Port) -> Port : Port(info(p),rename(name(p)),direction(p),type(p)) -; -; Circuit(info(c),modules*, main(c)) where : -; val modules* = -; for m in modules(c) map : -; match(m) : -; (m:InModule) : InModule(info(m),name(m), map(to-port,ports(m)), to-stmt(body(m))) -; (m:ExModule) : m -; -; -;;========== Pad Widths ================== -; -;public defstruct Pad <: Pass -;public defmethod pass (b:Pad) -> (Circuit -> Circuit) : pad-widths -;public defmethod name (b:Pad) -> String : "Pad Widths" -; -;;------------ Helper Functions -------------- -;defn int-width! (t:Type) -> Long : -; match(width!(t)) : -; (w:IntWidth) : width(w) -; (w) : error("Non-int width") -; -;defn set-width (desired:Long,t:Type) -> Type : -; match(t) : -; (t:UIntType) : UIntType(IntWidth(desired)) -; (t:SIntType) : SIntType(IntWidth(desired)) -; (t) : error("Non-ground type") -; -;defn lmax (l1:Long, l2:Long) -> Long : -; if l1 > l2 : l1 -; else : l2 -; -;;------------- Pad Widths ------------------- -; -;defn pad-widths-e (desired:Long,e:Expression) -> Expression : -; defn trim (desired:Long, e:Expression) : -; ;; println-all(["TRIM " desired " e " e]) -; DoPrim(BITS-SELECT-OP,list(e),list(to-int(to-string(desired)) - 1, 0),set-width(desired,type(e))) -; defn pad (desired:Long, e:Expression) : -; ;; println-all(["PAD " desired " e " e]) -; DoPrim(PAD-OP,list(e),list(to-int $ to-string(desired)),set-width(desired,type(e))) -; defn trim-pad (desired:Long, e:Expression) : -; val i = int-width!(type(e)) -; if i > desired : trim(desired, e) -; else if i == desired : e -; else : pad(desired, e) -; defn self-pad-widths-e (e:Expression) -> Expression : -; pad-widths-e(int-width!(type(e)), e) -; ;; println-all(["PAD-E " desired " " e]) -; match(e) : -; (e:DoPrim) : -; val new-desired = reduce(lmax, to-long(0), map(int-width!{type(_)}, args(e))) -; ;; println-all([" NEW DESIRED " new-desired]) -; val e* = -; if contains?([CONCAT-OP, DYN-SHIFT-RIGHT-OP, DYN-SHIFT-LEFT-OP], op(e)) : -; DoPrim(op(e), map(self-pad-widths-e, args(e)), consts(e), type(e)) -; else if contains?([MUX-OP], op(e)) : -; DoPrim(op(e), list(pad-widths-e(to-long(1), args(e)[0]), pad-widths-e(new-desired, args(e)[1]), pad-widths-e(new-desired, args(e)[2])), consts(e), type(e)) -; else : -; map(pad-widths-e{new-desired,_},e) -; trim-pad(desired, e*) -; (e:Ref|Subfield|Index) : -; trim-pad(desired, e) -; (e:UIntValue) : -; val i = int-width!(type(e)) -; if i > desired : trim(desired, e) -; else : UIntValue(value(e),IntWidth(desired)) -; (e:SIntValue) : -; val i = int-width!(type(e)) -; if i > desired : trim(desired, e) -; else : SIntValue(value(e),IntWidth(desired)) -; (e) : error(to-string $ e) -; -;defn pad-widths-s (s:Stmt) -> Stmt : -; ;; println-all(["PAD-S " s]) -; match(map(pad-widths-s,s)) : -; (s:Connect) : -; val i = int-width!(type(loc(s))) -; val loc* = pad-widths-e(i,loc(s)) -; val exp* = pad-widths-e(i,exp(s)) -; Connect(info(s),loc*,exp*) -; (s:PrintfStmt) : -; val args* = for x in args(s) map : -; val i = int-width!(type(x)) -; pad-widths-e(i,x) -; PrintfStmt(info(s),string(s),args*) -; (s:DefNode) : -; val i = int-width!(type(value(s))) -; val exp* = pad-widths-e(i,value(s)) -; DefNode(info(s),name(s),exp*) -; (s:Conditionally) : -; val i = int-width!(type(pred(s))) -; val pred* = pad-widths-e(i,pred(s)) -; Conditionally(info(s),pred*,conseq(s),alt(s)) -; (s) : s -; -;public defn pad-widths (c:Circuit) -> Circuit : -; Circuit{info(c),_,main(c)} $ -; for m in modules(c) map : -; match(m) : -; (m:ExModule) : m -; (m:InModule) : InModule(info(m),name(m),ports(m),pad-widths-s(body(m))) -; -; - -;============== Common Subexpression Elimination =========== -;NOT DONE - -;public defstruct CSE <: Pass -;public defmethod pass (b:CSE) -> (Circuit -> Circuit) : const-prop -;public defmethod name (b:CSE) -> String : "Common Subexpression Elimination" -;public defmethod short-name (b:ConstProp) -> String : "cse" -; -;defn cse-m (m:InModule) -> InModule : -; val cse-hash = HashTable<Expression,Int>(exp-hash) -; val placed? = HashTable<Expression,True|False>(exp-hash) -; -; defn cse-s (s:Stmt) -> Stmt : -; val stmts = Vector<Stmt>() -; defn cse-e (e:Expression) -> Expression -; match(s) : -; -; defn build-e (e:Expression) -> Expression : -; match(e) : -; (e:DoPrim) : -; if key?(cse-hash,e) : -; cse-hash[e] = cse-hash[e] + 1 -; else : -; cse-hash[e] = 1 -; placed?[e] = false -; (e) : e -; defn build-s (s:Stmt) -> Stmt : map{build-s,_} $ map(build-e,s) -; -; build-s(body(m)) -; InModule(info(m),name(m),ports(m),cse-s(body(m))) -; -;public defn cse (c:Circuit) -> Circuit : -; Circuit{info(c),_,main(c)} $ -; for m in modules(c) map : -; match(m) : -; (m:ExModule) : m -; (m:InModule) : cse-m(m) - - - -;;============= Constant Propagation ================ -; -public defstruct ConstProp <: Pass -public defmethod pass (b:ConstProp) -> (Circuit -> Circuit) : const-prop -public defmethod name (b:ConstProp) -> String : "Constant Propagation" -public defmethod short-name (b:ConstProp) -> String : "const-prop" - -defn const-prop-e (e:Expression) -> Expression : - match(map(const-prop-e,e)) : - (e:DoPrim) : - switch {op(e) == _} : - ;DYN-SHIFT-RIGHT-OP : - ; match(args(e)[1]) : - ; (x:UIntValue|SIntValue) : - ; DoPrim(SHIFT-RIGHT-OP,list(args(e)[0]),list(to-int(value(x))),UnknownType()) - ; (x) : e - ;DYN-SHIFT-LEFT-OP : - ; match(args(e)[1]) : - ; (x:UIntValue|SIntValue) : - ; DoPrim(SHIFT-LEFT-OP,list(args(e)[0]),list(to-int(value(x))),UnknownType()) - ; (x) : e - SHIFT-RIGHT-OP : - match(args(e)[0]) : - (x:UIntValue) : - val b = rsh(value(x),consts(e)[0]) - UIntValue(b,width(type(e) as UIntType)) - (x:SIntValue) : - val b = rsh(value(x),consts(e)[0]) - SIntValue(b,width(type(e) as SIntType)) - (x) : e - BITS-SELECT-OP : - match(args(e)[0]) : - (x:UIntValue) : - val b = bits(value(x),consts(e)[0] + 1,consts(e)[1]) - UIntValue(b,width(type(e) as UIntType)) - (x) : - if long!(type(e)) == long!(type(x)) : - if type(x) typeof UIntType : x - else : DoPrim(AS-UINT-OP,list(x),list(),type(e)) - else : e - else : e - (e) : e - -defn const-prop-s (s:Stmt) -> Stmt : - map{const-prop-e,_} $ map(const-prop-s,s) - -public defn const-prop (c:Circuit) -> Circuit : - Circuit{info(c),_,main(c)} $ - for m in modules(c) map : - match(m) : - (m:ExModule) : m - (m:InModule) : - mname = name(m) - InModule(info(m),name(m),ports(m),const-prop-s(body(m))) - -;============= Condense Mems ================ -; -;public defstruct CondenseMems <: Pass -;public defmethod pass (b:CondenseMems) -> (Circuit -> Circuit) : condense-mems -;public defmethod name (b:CondenseMems) -> String : "Condense Mems" -;public defmethod short-name (b:CondenseMems) -> String : "condense-mems" -; -;;------------- Utils --------------- -; -;defn concat (es:List<Expression>) -> Expression : -; if length(es) == 1 : head(es) -; else : CAT(head(es),cat(tail(es))) -;defn cast (t:Type,e:Expression) -> Expression : -; match(t) : -; (t:UIntType) : e -; (t:SIntType) : DoPrim(AS-SINT-OP,list(e),list(),SIntType(get-width(t))) -;defn get-width-index (e:Expression) -> Long : -; match(e) : -; (e:WRef) : 0 -; (e:WSubField) : -; var w = get-width-index(exp(e)) -; var found? = false -; for f in fields(type(exp(e)) as BundleType) do : -; if name(f) == name(e) : -; found? = true -; if found? == false : -; w = w + get-width(type(f)) -; w -; (e:WSubIndex) : -; get-width-index(exp(e)) + get-width(type(e)) * value(e) -;defn root-ref (e:Expression) -> Expression : -; match(e) : -; (e:WRef) : e -; (e:WSubField|WSubIndex) : root-ref(e) -;defn flatten (e:Expression) -> Expression : -; match(e) : -; (e:WRef) : e -; (e:WSubField|WSubIndex) : -; val base = get-width-index(e) -; val off = get-width(type(e)) -; DoPrim(BITS-SELECT-OP,list(root-ref(e)),list(base,off),UIntType(IntWidth(off))) -; -;;------------- Pass ------------------ - -;defn condense-mems (m:InModule) -> InModule : -; val mem-assigns = HashTable<Expression,Expression>(exp-hash) -; defn collect-mems (s:Stmt) -> Stmt : -; match(s) : -; (s:Connect) : -; defn condense-mems-e (e:Expression) -> Expression : -; val e* = match(e) : -; (e:WRef|WSubField|WSubIndex) : -; if (kind(e) typeof MemKind) : cast(type(e),flatten(e)) -; else : e -; (e:UIntValue|SIntValue) : e -; (e:DoPrim) : map(condense-mems-e,e) -; defn condense-mems (s:Stmt) -> Stmt : -; match(s) : -; (s:DefMemory) : -; val stmts = Vector<Stmt>() -; val s* = map(flatten,s) -; add(stmts,s*) -; val mem = WRef(name(s),type(s),MemKind(),UNKNOWN-GENDER) -; for f in fields(type(s) as BundleType) do : -; val data-name = -; if contains?(writers(s),name(f)) : `data -; else if contains(readwriters(s),name(f)) : `wdata -; else : false -; match(data-name) : -; (f:False) : false -; (n:Symbol) : -; val port = WSubField(mem,name(f),type(f),UNKNOWN-GENDER) -; val es = create-exps(WSubField(port,n,field-type(type(port),n),UNKNOWN-GENDER)) -; val e* = concat $ for e in es map : -; map(condense-mems-e,mem-assigns[e]) -; add(stmts,Connect(info(s),WSubField(port,n,data-type(s*),UNKNOWN-GENDER),e*)) -; Begin(to-list(stmts)) -; (s:Connect) : -; if kind(loc(s)) typeof MemKind : EmptyStmt() -; else : map(condense-mems-e, s) -; (s) : map{condense-mems,_} $ map(condense-mems-e, s) -; InModule(info(m),name(m),ports(m),condense-mems(body(m))) -; -;defn condense-mems (c:Circuit) -> Circuit : -; Circuit{info(c),_,main(c)} $ -; for m in modules(c) map : -; match(m) : -; (m:ExModule) : m -; (m:InModule) : condense-mems(m) - - -;============= Lower Types ================ -; -public defstruct LowerTypes <: Pass -public defmethod pass (b:LowerTypes) -> (Circuit -> Circuit) : lower-types -public defmethod name (b:LowerTypes) -> String : "Lower Types" -public defmethod short-name (b:LowerTypes) -> String : "lower-types" - -;------------- Utils --------------- -defn is-ground? (t:Type) -> True|False : - match(t) : - (t:UIntType|SIntType) : true - (t) : false -defn data? (ex:Expression) -> True|False : - match(kind(ex)) : - (k:MemKind) : match(ex) : - (ex:WRef|WSubIndex) : false - (ex:WSubField) : - var yes? = switch { _ == name(ex) } : - `rdata : true - `data : true - `mask : true - else : false - yes? and match(exp(ex)) : - (e:WSubField) : - contains?(ports(kind(e) as MemKind),name(e)) and (exp(e) typeof WRef) - (e) : false - (ex) : false - (k) : false - -defn expand-name (e:Expression) -> List<Symbol> : - val names = Vector<Symbol>() - defn expand-name-e (e:Expression) -> Expression : - match(map(expand-name-e,e)) : - (e:WRef) : add(names,name(e)) - (e:WSubField) : add(names,name(e)) - (e:WSubIndex) : add(names,to-symbol(value(e))) - e - expand-name-e(e) - to-list(names) - - -defn lower-other-mem (e:Expression, dt:Type) -> List<Expression> : - val names = expand-name(e) - if length(names) < 3 : error("Shouldn't be here") - for x in create-exps(names[0],dt) map : - var base = lowered-name(x) - for (x in names,i in 0 to false) do : - if i >= 3 : base = symbol-join([base `_ x]) - val m = WRef(base, UnknownType(), kind(e), UNKNOWN-GENDER) - val p = WSubField(m,to-symbol(names[1]),UnknownType(),UNKNOWN-GENDER) - WSubField(p,to-symbol(names[2]),UnknownType(),UNKNOWN-GENDER) - -defn lower-data-mem (e:Expression) -> Expression : - val names = expand-name(e) - if length(names) < 3 : error("Shouldn't be here") - else : - var base = names[0] - for (x in names,i in 0 to false) do : - if i >= 3 : base = symbol-join([base `_ x]) - val m = WRef(base, UnknownType(), kind(e), UNKNOWN-GENDER) - val p = WSubField(m,to-symbol(names[1]),UnknownType(),UNKNOWN-GENDER) - WSubField(p,to-symbol(names[2]),UnknownType(),UNKNOWN-GENDER) - -defn merge (a:Symbol,b:Symbol,x:Symbol) -> Symbol : symbol-join([a x b]) -val hashed-lowered-name = HashTable<Expression,Symbol>(gexp-hash) -defn fast-lowered-name (e:Expression) -> Symbol : - val x = get?(hashed-lowered-name,e,false) - match(x) : - (x:Symbol) : x - (x:False) : - match(e) : - (e:WRef) : name(e) - (e:WSubField) : merge(fast-lowered-name(exp(e)),name(e),`_) - (e:WSubIndex) : merge(fast-lowered-name(exp(e)),to-symbol(value(e)),`_) -defn lowered-name (e:Expression) -> Symbol : - match(e) : - (e:WRef) : name(e) - (e:WSubField) : merge(lowered-name(exp(e)),name(e),`_) - (e:WSubIndex) : merge(lowered-name(exp(e)),to-symbol(value(e)),`_) -defn root-ref (e:Expression) -> WRef : - match(e) : - (e:WRef) : e - (e:WSubField|WSubIndex|WSubAccess) : root-ref(exp(e)) - -;------------- Pass ------------------ - -defn lower-types (m:Module) -> Module : - val mdt = HashTable<Symbol,Type>(symbol-hash) - mname = name(m) - defn lower-types (s:Stmt) -> Stmt : - defn lower-mem (e:Expression) -> List<Expression> : - val names = expand-name(e) - if contains?([`data `mask `rdata],names[2]) : - list(lower-data-mem(e)) - else : - lower-other-mem(e,mdt[name(root-ref(e))]) - defn lower-types-e (e:Expression) -> Expression : - match(e) : - (e:WRef|UIntValue|SIntValue) : e - (e:WSubField|WSubIndex) : - match(kind(e)) : - (k:InstanceKind) : - val names = expand-name(e) - var n = names[1] - for (x in names,i in 0 to false) do : - if i > 1 : n = symbol-join([n `_ x]) - WSubField(root-ref(e),n,type(e),gender(e)) - (k:MemKind) : - if not gender(e) == FEMALE : - lower-mem(e)[0] - else : e - (k) : WRef(lowered-name(e),type(e),kind(e),gender(e)) - (e:DoPrim) : map(lower-types-e,e) - (e:Mux) : map(lower-types-e,e) - (e:ValidIf) : map(lower-types-e,e) - match(s) : - (s:DefWire|DefPoison) : - if is-ground?(type(s)) : s - else : - val es = create-exps(name(s),type(s)) - Begin $ for (e in es, i in 0 to false) map : - defn replace-type (t:Type) -> Type : type(e) - defn replace-name (n:Symbol) -> Symbol : lowered-name(e) - map{replace-name,_} $ map(replace-type,s) - (s:DefRegister) : - if is-ground?(type(s)) : s - else : - val es = create-exps(name(s),type(s)) - Begin $ for (e in es, i in 0 to false) map : - val init = lower-types-e(create-exps(init(s))[i]) - DefRegister(info(s),lowered-name(e),type(e),clock(s),reset(s),init) - (s:WDefInstance) : - val fields* = for f in fields(type(s) as BundleType) map-append : - val es = create-exps(WRef(name(f),type(f),ExpKind(),flip(f) * MALE)) - for e in es map : - switch { _ == gender(e) } : - MALE : Field(lowered-name(e),DEFAULT,type(f)) - FEMALE : Field(lowered-name(e),REVERSE,type(f)) - WDefInstance(info(s),name(s),module(s),BundleType(fields*)) - (s:DefMemory) : - mdt[name(s)] = data-type(s) - if is-ground?(data-type(s)) : s - else : - val es = create-exps(name(s),data-type(s)) - Begin $ for e in es map : - DefMemory(info(s),lowered-name(e),type(e),depth(s),write-latency(s),read-latency(s),readers(s),writers(s),readwriters(s)) - (s:IsInvalid) : - val s* = map(lower-types-e,s) - if kind(exp(s*)) typeof MemKind : - val es = lower-mem(exp(s*)) - Begin $ for e in es map : - IsInvalid(info(s*),e) - else : s* - (s:Connect) : - val s* = map(lower-types-e,s) - if kind(loc(s*)) typeof MemKind : - val es = lower-mem(loc(s*)) - Begin $ for e in es map : - Connect(info(s*),e,exp(s*)) - else : s* - (s:DefNode) : - val locs = create-exps(name(s),type(value(s))) - val n = length(locs) - val nodes = Vector<Stmt>() - val exps = create-exps(value(s)) - for i in 0 to n do : - val loc* = locs[i] - val exp* = exps[i] - add(nodes,DefNode(info(s),lowered-name(loc*),lower-types-e(exp*))) - if n == 1 : nodes[0] - else : Begin(to-list(nodes)) - (s) : map(lower-types-e,map(lower-types,s)) - - val ports* = for p in ports(m) map-append : - val es = create-exps(WRef(name(p),type(p),PortKind(),to-gender(direction(p)))) - for e in es map : - Port(info(p),lowered-name(e),to-dir(gender(e)),type(e)) - match(m) : - (m:ExModule) : ExModule(info(m),name(m),ports*) - (m:InModule) : InModule(info(m),name(m),ports*,lower-types(body(m))) - -defn lower-types (c:Circuit) -> Circuit : - Circuit{info(c),_,main(c)} $ - for m in modules(c) map : lower-types(m) - - - -;============ RENAME VERILOG KEYWORDS ============= - -public defstruct VerilogRename <: Pass -public defmethod pass (b:VerilogRename) -> (Circuit -> Circuit) : verilog-rename -public defmethod name (b:VerilogRename) -> String : "Verilog Rename" -public defmethod short-name (b:VerilogRename) -> String : "verilog-rename" - -defn verilog-rename (c:Circuit) -> Circuit : - defn verilog-rename-n (n:Symbol) -> Symbol : - if key?(v-keywords,n) : symbol-join([n `$]) - else : n - defn verilog-rename-e (e:Expression) -> Expression : - match(e) : - (e:WRef) : WRef(verilog-rename-n(name(e)),type(e),kind(e),gender(e)) - (e) : map(verilog-rename-e,e) - defn verilog-rename-s (s:Stmt) -> Stmt : - map{verilog-rename-n,_} $ - map{verilog-rename-e,_} $ - map(verilog-rename-s,s) - - Circuit{info(c),_,main(c)} $ - for m in modules(c) map : - val ports* = for p in ports(m) map : - Port(info(p),verilog-rename-n(name(p)),direction(p),type(p)) - match(m) : - (m:InModule) : InModule(info(m),name(m),ports*,verilog-rename-s(body(m))) - (m:ExModule) : m - -;============ VERILOG ============== - -public defstruct Verilog <: Pass : - with-output: (() -> False) -> False -public defmethod pass (b:Verilog) -> (Circuit -> Circuit) : emit-verilog{with-output(b),_} -public defmethod name (b:Verilog) -> String : "To Verilog" -public defmethod short-name (b:Verilog) -> String : "to-verilog" - -;============ Utilz ============= -defstruct VIndent -defstruct VRandom -val tab = " " -val ran = VRandom() -defn wref (n:Symbol,t:Type) : WRef(n,t,ExpKind(),UNKNOWN-GENDER) -defn escape (s:String) -> String : - val s* = Vector<String>() - add(s*,"\"");" - var percent = false - for c in s do : - if c == '\n' : - add(s*,"\\n") - else if c == '"' : - add(s*, "\\\"") - else : - if c == 'x' and percent : - add(s*,"h") - else : add(s*,to-string(c)) - percent = c == '%' - add(s*,"\"");" - string-join(s*) -defn remove-root (ex:Expression) -> Expression : - match(exp(ex as WSubField)) : - (e:WSubField) : remove-root(e) - (e:WRef) : WRef(name(ex as WSubField),type(ex),InstanceKind(),UNKNOWN-GENDER) -defn !empty? (s:Vector) -> True|False : - if length(s) == 0 : false - else : true -defn long! (t:Type) -> Long : - match(t) : - (t:UIntType|SIntType) : width(width(t) as IntWidth) - (t:BundleType) : - var w = to-long(0) - for f in fields(t) do : - w = w + long!(type(f)) - w - (t:VectorType) : to-long(size(t)) * long!(type(t)) - (t:ClockType) : to-long(1) - -defn rand-string (t:Type) -> Streamable : - val w* = ((long!(t) + to-long(31)) / to-long(32)) - ["{" w* "{" ran "}}"] -defn emit (x:?) : emit(x,0) -defn emit (x:?, top:Int) : - defn cast (e:Expression) -> ? : - match(type(e)) : - (t:UIntType) : e - (t:SIntType) : ["$signed(" e ")"] - match(x) : - (e:Expression) : - turn-off-debug(false) - match(e) : - (e:DoPrim) : emit(op-stream(e), top + 1) - (e:Mux) : emit([cond(e) " ? " cast(tval(e)) " : " cast(fval(e))],top + 1) - (e:ValidIf) : emit([cast(value(e))],top + 1) - (e:WRef) : print(e) - (e:WSubField) : print(lowered-name(e)) - (e:WSubAccess) : print-all([lowered-name(exp(e)) "[" lowered-name(index(e)) "]"]) - (e:WSubIndex) : print(e) - (e:UIntValue|SIntValue) : v-print(e) - turn-on-debug(false) - (t:Type) : - match(t) : - (t:UIntType|SIntType) : - val w = long!(t) - to-long(1) - if w > to-long(0) : print-all(["[" w ":0]"]) - else : print("");" - (t:ClockType) : print("");" - (t:VectorType) : - emit(type(t), top + 1) - print-all(["[" size(t) - 1 ":0]"]) - (t) : println(t) - - (p:Direction) : - switch {_ == p} : - INPUT : print("input") - OUTPUT : print("output") - (s:Symbol) : print(s) - (i:Int) : print(i) - (i:Long) : print(i) - (s:String) : print(s) - (t:VIndent) : print(" ") - (r:VRandom) : print("$random") - (s:Streamable) : - for x in s do : - emit(x, top + 1) - if top == 0 : print("\n") - -;------------- PASS ----------------- -defn v-print (e:UIntValue|SIntValue) : - val str = to-string(value(e)) - val out = substring(str,1,length(str) - 1) - print $ string-join $ match(e) : - (e:UIntValue) : [long!(type(e)) "'" out] - (e:SIntValue) : [long!(type(e)) "'s" out] -defn op-stream (doprim:DoPrim) -> Streamable : - defn cast-if (e:Expression) -> ? : - val signed? = for x in args(doprim) any? : type(x) typeof SIntType - if not signed? : e - else : match(type(e)) : - (t:SIntType) : ["$signed(" e ")"] - (t:UIntType) : ["$signed({1'b0," e "})"] - defn cast (e:Expression) -> ? : - match(type(doprim)) : - (t:UIntType) : e - (t:SIntType) : ["$signed(" e ")"] - defn cast-as (e:Expression) -> ? : - match(type(e)) : - (t:UIntType) : e - (t:SIntType) : ["$signed(" e ")"] - defn a0 () -> Expression : args(doprim)[0] - defn a1 () -> Expression : args(doprim)[1] - defn a2 () -> Expression : args(doprim)[2] - defn c0 () -> Int : consts(doprim)[0] - defn c1 () -> Int : consts(doprim)[1] - - switch {_ == op(doprim)} : - ADD-OP : [cast-if(a0()) " + " cast-if(a1())] - ADDW-OP : [cast-if(a0()) " + " cast-if(a1())] - SUB-OP : [cast-if(a0()) " - " cast-if(a1())] - SUBW-OP : [cast-if(a0()) " - " cast-if(a1())] - MUL-OP : [cast-if(a0()) " * " cast-if(a1()) ] - DIV-OP : [cast-if(a0()) " / " cast-if(a1()) ] - REM-OP : [cast-if(a0()) " % " cast-if(a1()) ] - LESS-OP : [cast-if(a0()) " < " cast-if(a1())] - LESS-EQ-OP : [cast-if(a0()) " <= " cast-if(a1())] - GREATER-OP : [cast-if(a0()) " > " cast-if(a1())] - GREATER-EQ-OP : [cast-if(a0()) " >= " cast-if(a1())] - EQUAL-OP : [cast-if(a0()) " == " cast-if(a1())] - NEQUAL-OP : [cast-if(a0()) " != " cast-if(a1())] - PAD-OP : - val w = long!(type(a0())) - val diff = (to-long(c0()) - w) - if w == to-long(0) : [ a0() ] - else : match(type(doprim)) : - (t:SIntType) : ["{{" diff "{" a0() "[" w - to-long(1) "]}}, " a0() " }"] - (t) : ["{{" diff "'d0 }, " a0() " }"] - AS-UINT-OP : ["$unsigned(" a0() ")"] - AS-SINT-OP : ["$signed(" a0() ")"] - AS-CLOCK-OP : ["$unsigned(" a0() ")"] - DYN-SHIFT-LEFT-OP : [cast(a0()) " << " a1()] - DYN-SHIFT-RIGHT-OP : - match(type(doprim)) : - (t:SIntType) : [cast(a0()) " >>> " a1()] - (t) : [cast(a0()) " >> " a1()] - SHIFT-LEFT-OP : [cast(a0()) " << " c0()] - SHIFT-RIGHT-OP : [a0() "[" long!(type(a0())) - to-long(1) ":" c0() "]"] - NEG-OP : ["-{" cast(a0()) "}"] - CONVERT-OP : - match(type(a0())) : - (t:UIntType) : ["{1'b0," cast(a0()) "}"] - (t:SIntType) : [cast(a0())] - NOT-OP : ["~ " a0()] - AND-OP : [cast-as(a0()) " & " cast-as(a1())] - OR-OP : [cast-as(a0()) " | " cast-as(a1())] - XOR-OP : [cast-as(a0()) " ^ " cast-as(a1())] - AND-REDUCE-OP : - val v = Vector<Streamable>() - for b in 0 to to-int(long!(type(doprim))) do : - add(v,[cast(a0()) "[" b "]"]) - join(v," & ") - OR-REDUCE-OP : - val v = Vector<Streamable>() - for b in 0 to to-int(long!(type(doprim))) do : - add(v,[cast(a0() ) "[" b "]"]) - join(v," | ") - XOR-REDUCE-OP : - val v = Vector<Streamable>() - for b in 0 to to-int(long!(type(doprim))) do : - add(v,[cast(a0() ) "[" b "]"]) - join(v," ^ ") - CONCAT-OP : ["{" cast(a0()) "," cast(a1()) "}"] - BITS-SELECT-OP : - if c0() == c1() : [a0() "[" c0() "]"] - else : [a0() "[" c0() ":" c1() "]"] - HEAD-OP : - val w = long!(type(a0())) - val high = w - to-long(1) - val low = w - to-long(c0()) - [a0() "[" high ":" low "]"] - TAIL-OP : - val w = long!(type(a0())) - val low = w - to-long(c0()) - to-long(1) - [a0() "[" low ":" 0 "]"] - -defn emit-verilog (m:InModule) -> Module : - mname = name(m) - val netlist = HashTable<Expression,Expression>(exp-hash) - val simlist = Vector<Stmt>() - val namehash = get-sym-hash(m,keys(v-keywords)) - defn build-netlist (s:Stmt) -> Stmt : - match(s) : - (s:Connect) : netlist[loc(s)] = exp(s) - (s:IsInvalid) : - val n = firrtl-gensym(`GEN,namehash) - val e = wref(n,type(exp(s))) - netlist[exp(s)] = e - (s:Conditionally) : add(simlist,s) - (s:DefNode) : - val e = WRef(name(s),get-type(s),NodeKind(),MALE) - netlist[e] = value(s) - (s) : map(build-netlist,s) - s - - val portdefs = Vector<Streamable>() - val declares = Vector<Streamable>() - val instdeclares = Vector<Streamable>() - val assigns = Vector<Streamable>() - val at-clock = HashTable<Expression,Vector<Streamable>>(exp-hash) - val initials = Vector<Streamable>() - val simulates = Vector<Streamable>() - defn declare (b:Symbol,n:Symbol,t:Type) : - match(t) : - (t:VectorType) : add(declares,[b " " type(t) " " n " [0:" size(t) - 1 "];"]) - (t) : add(declares,[b " " t " " n ";"]) - defn assign (e:Expression,value:Expression) : - add(assigns,["assign " e " = " value ";"]) - defn update-and-reset (r:Expression,clk:Expression,reset?:Expression,init:Expression) : - if not key?(at-clock,clk) : at-clock[clk] = Vector<Streamable>() - defn add-update (e:Expression,tabs:String) : - match(e) : - (e:Mux) : - add(at-clock[clk],[tabs "if(" cond(e) ") begin"]) - add-update(tval(e),string-join([tabs tab])) - add(at-clock[clk],[tabs "end else begin"]) - add-update(fval(e),string-join([tabs tab])) - add(at-clock[clk],[tabs "end"]) - (e) : - if e == r : add(at-clock[clk],[tabs ";"]) - else : add(at-clock[clk],[tabs r " <= " e ";"]) - val tv = init - val fv = netlist[r] - add-update(Mux(reset?,tv,fv,mux-type-and-widths(tv,fv)),"");" - defn update (e:Expression,value:Expression,clk:Expression,en:Expression) : - if not key?(at-clock,clk) : - at-clock[clk] = Vector<Streamable>() - if en == one : - add(at-clock[clk],[e " <= " value ";"]) - else : - add(at-clock[clk],["if(" en ") begin"]) - add(at-clock[clk],[tab e " <= " value ";"]) - add(at-clock[clk],["end"]) - defn initialize (e:Expression) : - add(initials,[e " = " rand-string(type(e)) ";"]) - defn initialize-mem (n:Symbol,i:Int,t:Type) : - add(initials,["for (initvar = 0; initvar < " i "; initvar = initvar+1)"]) - val index = WRef(`initvar,UnknownType(),ExpKind(),UNKNOWN-GENDER) - add(initials,[tab WSubAccess(wref(n,t),index,UnknownType(),FEMALE), " = " rand-string(t) ";"]) - defn instantiate (n:Symbol,m:Symbol,es:List<Expression>) : - add(instdeclares,[m " " n " ("]) - for (e in es,i in 0 to false) do : - val s = [tab "." remove-root(e) "(" lowered-name(e) ")"] - if i != length(es) - 1 : add(instdeclares,[s ","]) - else : add(instdeclares,s) - add(instdeclares,[");"]) - for e in es do : - declare(`wire,lowered-name(e),type(e)) - val e* = WRef(lowered-name(e),type(e),kind(e),gender(e)) - if (gender(e) == FEMALE) : assign(e*,netlist[e]) - defn simulate (clk:Expression,en:Expression,s:Streamable) : - if not key?(at-clock,clk) : - at-clock[clk] = Vector<Streamable>() - add(at-clock[clk],["`ifndef SYNTHESIS"]) - add(at-clock[clk],[tab "if(" en ") begin"]) - add(at-clock[clk],[tab tab s]) - add(at-clock[clk],[tab "end"]) - add(at-clock[clk],["`endif"]) - defn stop (ret:Int) -> Streamable : - ["$fdisplay(32'h80000002,\"" ret "\");$finish;"] - defn printf (str:String,args:List<Expression>) -> Streamable : - val str* = join(List(escape(str),args),",") - ["$fwrite(32'h80000002," str* ");"] - defn delay (e:Expression, n:Int, clk:Expression) -> Expression : - var e* = e - for i in 0 to n do : - val name = firrtl-gensym(`GEN,namehash) - declare(`reg,name,type(e)) - val e** = WRef(name,type(e),ExpKind(),UNKNOWN-GENDER) - update(e**,e*,clk,one) - e* = e** - e* - defn build-ports () : - for (p in ports(m),i in 0 to false) do : - var end = ",\n" - if length(ports(m)) - 1 == i : - end = "\n);\n" - switch {_ == direction(p)} : - INPUT : - add(portdefs,[direction(p) " " type(p) " " name(p) ]) - OUTPUT : - add(portdefs,[direction(p) " " type(p) " " name(p) ]) - val e* = WRef(name(p),type(p),PortKind(),FEMALE) - assign(e*,netlist[e*]) - if length(ports(m)) == 0 : print(");\n") - defn build-streams (s:Stmt) -> Stmt : - match(s) : - (s:Connect) : s - (s:DefWire) : - declare(`wire,name(s),type(s)) - val e = wref(name(s),type(s)) - assign(e,netlist[e]) - (s:DefRegister) : - declare(`reg,name(s),type(s)) - val e = wref(name(s),type(s)) - update-and-reset(e,clock(s),reset(s),init(s)) - initialize(e) - (s:IsInvalid) : - val wref = netlist[exp(s)] as WRef - declare(`reg,name(wref),type(exp(s))) - initialize(wref) - (s:DefPoison) : - val n = name(s) - val e = wref(n,type(s)) - declare(`reg,n,type(e)) - initialize(e) - (s:DefNode) : - declare(`wire,name(s),type(value(s))) - assign(WRef(name(s),type(value(s)),NodeKind(),MALE),value(s)) - (s:Stop) : simulate(clk(s),en(s),stop(ret(s))) - (s:Print) : simulate(clk(s),en(s),printf(string(s),args(s))) - (s:WDefInstance) : - val es = create-exps(WRef(name(s),type(s),InstanceKind(),MALE)) - instantiate(name(s),module(s),es) - (s:DefMemory) : - val mem = WRef(name(s),get-type(s),MemKind(append-all([readers(s) writers(s) readwriters(s)])),UNKNOWN-GENDER) - defn mem-exp (p:Symbol,f:Symbol) : - val t1 = field-type(type(mem),p) - val t2 = field-type(t1,f) - WSubField{_,f,t2,UNKNOWN-GENDER} $ - WSubField{_,p,t1,UNKNOWN-GENDER} $ - mem - - declare(`reg,name(s),VectorType(data-type(s),depth(s))) - initialize-mem(name(s),depth(s),data-type(s)) - for r in readers(s) do : - val data = mem-exp(r,`data) - val addr = mem-exp(r,`addr) - val en = mem-exp(r,`en) - val clk = mem-exp(r,`clk) - - declare(`wire,lowered-name(data),type(data)) - declare(`wire,lowered-name(addr),type(addr)) - declare(`wire,lowered-name(en),type(en)) - declare(`wire,lowered-name(clk),type(clk)) - - ; Read port - assign(addr,netlist[addr]) ;Connects value to m.r.addr - assign(en,netlist[en]) ;Connects value to m.r.en - assign(clk,netlist[clk]) ;Connects value to m.r.clk - val addr* = delay(addr,read-latency(s),clk) - val en* = delay(en,read-latency(s),clk) - val mem-port = WSubAccess(mem,addr*,UnknownType(),UNKNOWN-GENDER) - assign(data,mem-port) - - for w in writers(s) do : - val data = mem-exp(w,`data) - val addr = mem-exp(w,`addr) - val mask = mem-exp(w,`mask) - val en = mem-exp(w,`en) - val clk = mem-exp(w,`clk) - - declare(`wire,lowered-name(data),type(data)) - declare(`wire,lowered-name(addr),type(addr)) - declare(`wire,lowered-name(mask),type(mask)) - declare(`wire,lowered-name(en),type(en)) - declare(`wire,lowered-name(clk),type(clk)) - - ; Write port - assign(data,netlist[data]) - assign(addr,netlist[addr]) - assign(mask,netlist[mask]) - assign(en,netlist[en]) - assign(clk,netlist[clk]) - - val data* = delay(data,write-latency(s) - 1,clk) - val addr* = delay(addr,write-latency(s) - 1,clk) - val mask* = delay(mask,write-latency(s) - 1,clk) - val en* = delay(en,write-latency(s) - 1,clk) - val mem-port = WSubAccess(mem,addr*,UnknownType(),UNKNOWN-GENDER) - update(mem-port,data*,clk,AND(en*,mask*)) - - for rw in readwriters(s) do : - val wmode = mem-exp(rw,`wmode) - val rdata = mem-exp(rw,`rdata) - val data = mem-exp(rw,`data) - val mask = mem-exp(rw,`mask) - val addr = mem-exp(rw,`addr) - val en = mem-exp(rw,`en) - val clk = mem-exp(rw,`clk) - - declare(`wire,lowered-name(wmode),type(wmode)) - declare(`wire,lowered-name(rdata),type(rdata)) - declare(`wire,lowered-name(data),type(data)) - declare(`wire,lowered-name(mask),type(mask)) - declare(`wire,lowered-name(addr),type(addr)) - declare(`wire,lowered-name(en),type(en)) - declare(`wire,lowered-name(clk),type(clk)) - - ; Assigned to lowered wires of each - assign(clk,netlist[clk]) - assign(addr,netlist[addr]) - assign(data,netlist[data]) - assign(addr,netlist[addr]) - assign(mask,netlist[mask]) - assign(en,netlist[en]) - assign(wmode,netlist[wmode]) - - ; Delay new signals by latency - val raddr* = delay(addr,read-latency(s),clk) - val waddr* = delay(addr,write-latency(s) - 1,clk) - val en* = delay(en,write-latency(s) - 1,clk) - val rmod* = delay(wmode,write-latency(s) - 1,clk) - val data* = delay(data,write-latency(s) - 1,clk) - val mask* = delay(mask,write-latency(s) - 1,clk) - - ; Write - - val rmem-port = WSubAccess(mem,raddr*,UnknownType(),UNKNOWN-GENDER) - assign(rdata,rmem-port) - val wmem-port = WSubAccess(mem,waddr*,UnknownType(),UNKNOWN-GENDER) - update(wmem-port,data*,clk,AND(AND(en*,mask*),wmode)) - (s:Begin) : map(build-streams,s) - s - - defn emit-streams () : - emit(["module " name(m) "("]) - if !empty?(portdefs) : - for (x in portdefs, i in 0 to false) do : - if i != length(portdefs) - 1 : emit([tab x ","]) - else : emit([tab x]) - emit([");"]) - - if !empty?(declares) : - for x in declares do : emit([tab x]) - - if !empty?(instdeclares) : - for x in instdeclares do : emit([tab x]) - - if !empty?(assigns) : - for x in assigns do : emit([tab x]) - - if !empty?(initials) : - emit(["`ifndef SYNTHESIS"]) - emit([" integer initvar;"]) - emit([" initial begin"]) - emit([" #0.002;"]) - for x in initials do : - emit([tab x]) - emit([" end"]) - emit(["`endif"]) - - for clk-stream in at-clock do : - if !empty?(value(clk-stream)) : - emit([tab "always @(posedge " key(clk-stream) ") begin"]) - for x in value(clk-stream) do : - emit([tab tab x]) - emit([tab "end"]) - - emit(["endmodule"]) - - build-netlist(body(m)) - build-ports() - build-streams(body(m)) - emit-streams() - m - -defn emit-verilog (with-output:(() -> False) -> False, c:Circuit) : - with-output $ fn () : - for m in modules(c) do : - match(m) : - (m:InModule) : emit-verilog(m) - (m:ExModule) : false - c - - -;============ LoFIRRTLToVERILOG ============== - -public defstruct LoToVerilog <: Pass : - with-output: (() -> False) -> False -public defmethod pass (b:LoToVerilog) -> (Circuit -> Circuit) : lo-to-verilog{with-output(b),_} -public defmethod name (b:LoToVerilog) -> String : "Lo To Verilog" -public defmethod short-name (b:LoToVerilog) -> String : "lo-to-verilog" - -defn lo-to-verilog (with-output:(() -> False) -> False, c:Circuit) : - val c1 = to-working-ir(c) - ;println(c1) - val c2 = resolve(c1) - ;println(c2) - val c3 = v-wrap(c2) - ;println(c3) - val c4 = split-exp(c3) - ;println(c4) - val c5 = verilog-rename(c4) - ;println(c5) - emit-verilog(with-output,c5) - - diff --git a/src/main/stanza/primop.stanza b/src/main/stanza/primop.stanza deleted file mode 100644 index f6aa0de5..00000000 --- a/src/main/stanza/primop.stanza +++ /dev/null @@ -1,280 +0,0 @@ -;Copyright (c) 2014 - 2016 The Regents of the University of -;California (Regents). All Rights Reserved. Redistribution and use in -;source and binary forms, with or without modification, are permitted -;provided that the following conditions are met: -; * Redistributions of source code must retain the above -; copyright notice, this list of conditions and the following -; two paragraphs of disclaimer. -; * Redistributions in binary form must reproduce the above -; copyright notice, this list of conditions and the following -; two paragraphs of disclaimer in the documentation and/or other materials -; provided with the distribution. -; * Neither the name of the Regents nor the names of its contributors -; may be used to endorse or promote products derived from this -; software without specific prior written permission. -;IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, -;SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, -;ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF -;REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT -;LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -;A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF -;ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION -;TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR -;MODIFICATIONS. -defpackage firrtl/primops : - import core - import verse - import firrtl/ir2 - import firrtl/ir-utils - import firrtl/passes - - -public defn set-primop-type (e:DoPrim) -> DoPrim : - ;println-all(["Inferencing primop type: " e]) - defn PLUS (w1:Width,w2:Width) -> Width : PlusWidth(w1,w2) - defn MAX (w1:Width,w2:Width) -> Width : MaxWidth(list(w1,w2)) - defn MINUS (w1:Width,w2:Width) -> Width : MinusWidth(w1,w2) - defn POW (w1:Width) -> Width : ExpWidth(w1) - defn MIN (w1:Width,w2:Width) -> Width : MinWidth(list(w1,w2)) - val o = op(e) - val a = args(e) - val c = consts(e) - defn t1 () : type(a[0]) - defn t2 () : type(a[1]) - defn t3 () : type(a[2]) - defn w1 () : width!(type(a[0])) - defn w2 () : width!(type(a[1])) - defn w3 () : width!(type(a[2])) - defn c1 () : IntWidth(c[0]) - defn c2 () : IntWidth(c[1]) - switch {op(e) == _} : - ADD-OP : DoPrim{o,a,c,_} $ - match(t1(),t2()) : - (t1:UIntType, t2:UIntType) : UIntType(PLUS(MAX(w1(),w2()),ONE)) - (t1:UIntType, t2:SIntType) : SIntType(PLUS(MAX(w1(),w2()),ONE)) - (t1:SIntType, t2:UIntType) : SIntType(PLUS(MAX(w1(),w2()),ONE)) - (t1:SIntType, t2:SIntType) : SIntType(PLUS(MAX(w1(),w2()),ONE)) - (t1, t2) : UnknownType() - SUB-OP : DoPrim{o,a,c,_} $ - match(t1(),t2()) : - (t1:UIntType, t2:UIntType) : SIntType(PLUS(MAX(w1(),w2()),ONE)) - (t1:UIntType, t2:SIntType) : SIntType(PLUS(MAX(w1(),w2()),ONE)) - (t1:SIntType, t2:UIntType) : SIntType(PLUS(MAX(w1(),w2()),ONE)) - (t1:SIntType, t2:SIntType) : SIntType(PLUS(MAX(w1(),w2()),ONE)) - (t1, t2) : UnknownType() - MUL-OP : DoPrim{o,a,c,_} $ - match(t1(),t2()) : - (t1:UIntType, t2:UIntType) : UIntType(PLUS(w1(),w2())) - (t1:UIntType, t2:SIntType) : SIntType(PLUS(w1(),w2())) - (t1:SIntType, t2:UIntType) : SIntType(PLUS(w1(),w2())) - (t1:SIntType, t2:SIntType) : SIntType(PLUS(w1(),w2())) - (t1, t2) : UnknownType() - DIV-OP : DoPrim{o,a,c,_} $ - match(t1(),t2()) : - (t1:UIntType, t2:UIntType) : UIntType(w1()) - (t1:UIntType, t2:SIntType) : SIntType(PLUS(w1(),ONE)) - (t1:SIntType, t2:UIntType) : SIntType(w1()) - (t1:SIntType, t2:SIntType) : SIntType(PLUS(w1(),ONE)) - (t1, t2) : UnknownType() - REM-OP : DoPrim{o,a,c,_} $ - match(t1(),t2()) : - (t1:UIntType, t2:UIntType) : UIntType(MIN(w1(),w2())) - (t1:UIntType, t2:SIntType) : UIntType(MIN(w1(),w2())) - (t1:SIntType, t2:UIntType) : SIntType(MIN(w1(),PLUS(w2(),ONE))) - (t1:SIntType, t2:SIntType) : SIntType(MIN(w1(),w2())) - (t1, t2) : UnknownType() - LESS-OP : DoPrim{o,a,c,_} $ - match(t1(),t2()) : - (t1:UIntType|SIntType, t2:UIntType|SIntType) : BoolType() - (t1, t2) : UnknownType() - LESS-EQ-OP : DoPrim{o,a,c,_} $ - match(t1(),t2()) : - (t1:UIntType|SIntType, t2:UIntType|SIntType) : BoolType() - (t1, t2) : UnknownType() - GREATER-OP : DoPrim{o,a,c,_} $ - match(t1(),t2()) : - (t1:UIntType|SIntType, t2:UIntType|SIntType) : BoolType() - (t1, t2) : UnknownType() - GREATER-EQ-OP : DoPrim{o,a,c,_} $ - match(t1(),t2()) : - (t1:UIntType|SIntType, t2:UIntType|SIntType) : BoolType() - (t1, t2) : UnknownType() - EQUAL-OP : DoPrim{o,a,c,_} $ - match(t1(),t2()) : - (t1:UIntType|SIntType, t2:UIntType|SIntType) : BoolType() - (t1, t2) : UnknownType() - NEQUAL-OP : DoPrim{o,a,c,_} $ - match(t1(),t2()) : - (t1:UIntType|SIntType, t2:UIntType|SIntType) : BoolType() - (t1, t2) : UnknownType() - PAD-OP : DoPrim{o,a,c,_} $ - match(t1()) : - (t1:UIntType) : UIntType(MAX(w1(),c1())) - (t1:SIntType) : SIntType(MAX(w1(),c1())) - (t1) : UnknownType() - AS-UINT-OP : DoPrim{o,a,c,_} $ - match(t1()) : - (t1:UIntType) : UIntType(w1()) - (t1:SIntType) : UIntType(w1()) - (t1:ClockType) : UIntType(ONE) - (t1) : UnknownType() - AS-SINT-OP : DoPrim{o,a,c,_} $ - match(t1()) : - (t1:UIntType) : SIntType(w1()) - (t1:SIntType) : SIntType(w1()) - (t1:ClockType) : SIntType(ONE) - (t1) : UnknownType() - AS-CLOCK-OP : DoPrim{o,a,c,_} $ - match(t1()) : - (t1:UIntType) : ClockType() - (t1:SIntType) : ClockType() - (t1:ClockType) : ClockType() - (t1) : UnknownType() - SHIFT-LEFT-OP : DoPrim{o,a,c,_} $ - match(t1()) : - (t1:UIntType) : UIntType(PLUS(w1(),c1())) - (t1:SIntType) : SIntType(PLUS(w1(),c1())) - (t1) : UnknownType() - SHIFT-RIGHT-OP : DoPrim{o,a,c,_} $ - match(t1()) : - (t1:UIntType) : UIntType(MINUS(w1(),c1())) - (t1:SIntType) : SIntType(MINUS(w1(),c1())) - (t1) : UnknownType() - DYN-SHIFT-LEFT-OP : DoPrim{o,a,c,_} $ - match(t1()) : - (t1:UIntType) : UIntType(PLUS(w1(),POW(w2()))) - (t1:SIntType) : SIntType(PLUS(w1(),POW(w2()))) - (t1) : UnknownType() - DYN-SHIFT-RIGHT-OP : DoPrim{o,a,c,_} $ - match(t1()) : - (t1:UIntType) : UIntType(w1()) - (t1:SIntType) : SIntType(w1()) - (t1) : UnknownType() - CONVERT-OP : DoPrim{o,a,c,_} $ - match(t1()) : - (t1:UIntType) : SIntType(PLUS(w1(),ONE)) - (t1:SIntType) : SIntType(w1()) - (t1) : UnknownType() - NEG-OP : DoPrim{o,a,c,_} $ - match(t1()) : - (t1:UIntType) : SIntType(PLUS(w1(),ONE)) - (t1:SIntType) : SIntType(PLUS(w1(),ONE)) - (t1) : UnknownType() - NOT-OP : DoPrim{o,a,c,_} $ - match(t1()) : - (t1:UIntType|SIntType) : UIntType(w1()) - (t1) : UnknownType() - AND-OP : DoPrim{o,a,c,_} $ - match(t1(),t2()) : - (t1:UIntType|SIntType, t2:UIntType|SIntType) : UIntType(MAX(w1(),w2())) - (t1,t2) : UnknownType() - OR-OP : DoPrim{o,a,c,_} $ - match(t1(),t2()) : - (t1:UIntType|SIntType, t2:UIntType|SIntType) : UIntType(MAX(w1(),w2())) - (t1,t2) : UnknownType() - XOR-OP : DoPrim{o,a,c,_} $ - match(t1(),t2()) : - (t1:UIntType|SIntType, t2:UIntType|SIntType) : UIntType(MAX(w1(),w2())) - (t1,t2) : UnknownType() - AND-REDUCE-OP : DoPrim{o,a,c,_} $ - match(t1()) : - (t1:UIntType|SIntType) : BoolType() - (t1) : UnknownType() - OR-REDUCE-OP : DoPrim{o,a,c,_} $ - match(t1()) : - (t1:UIntType|SIntType) : BoolType() - (t1) : UnknownType() - XOR-REDUCE-OP : DoPrim{o,a,c,_} $ - match(t1()) : - (t1:UIntType|SIntType) : BoolType() - (t1) : UnknownType() - CONCAT-OP : DoPrim{o,a,c,_} $ - match(t1(),t2()) : - (t1:UIntType|SIntType, t2:UIntType|SIntType) : UIntType(PLUS(w1(),w2())) - (t1, t2) : UnknownType() - BITS-SELECT-OP : DoPrim{o,a,c,_} $ - match(t1()) : - (t1:UIntType|SIntType) : UIntType(PLUS(MINUS(c1(),c2()),ONE)) - (t1) : UnknownType() - HEAD-OP : DoPrim{o,a,c,_} $ - match(t1()) : - (t1:UIntType|SIntType) : UIntType(c1()) - (t1) : UnknownType() - TAIL-OP : DoPrim{o,a,c,_} $ - match(t1()) : - (t1:UIntType|SIntType) : UIntType(MINUS(w1(),c1())) - (t1) : UnknownType() - -;public defn primop-gen-constraints (e:DoPrim,v:Vector<WGeq>) -> Type : -; defn get-max (i0:Int,i1:Int) -> Width : get-max(list(i0,i1)) -; defn get-max (ls:List<Int>) -> Width : -; MaxWidth $ for i in ls map : width!(args(e)[i]) -; defn all-max () -> Width : -; MaxWidth $ for x in args(e) map : width!(x) -; -; println-all-debug(["Looking at " op(e) " with inputs " args(e)]) -; val w* = switch {op(e) == _} : -; ADD-OP : PlusWidth(get-max(0,1),IntWidth(1)) -; SUB-OP : PlusWidth(get-max(0,1),IntWidth(1)) -; MUL-OP : PlusWidth(get-max(0,1),get-max(0,1)) -; DIV-OP : -; match(type(args(e)[0]),type(args(e)[1])) : -; (t0:UIntType,t1:SIntType) : PlusWidth(width!(args(e)[0]),IntWidth(1)) -; (t0:SIntType,t1:SIntType) : PlusWidth(width!(args(e)[0]),IntWidth(1)) -; (t0,t1) : width!(args(e)[0]) -; REM-OP : -; match(type(args(e)[0]),type(args(e)[1])) : -; (t0:SIntType,t1:UIntType) : PlusWidth(width!(args(e)[1]),IntWidth(1)) -; (t0,t1) : width!(args(e)[1]) -; QUO-OP : -; match(type(args(e)[0]),type(args(e)[1])) : -; (t0:UIntType,t1:SIntType) : PlusWidth(width!(args(e)[0]),IntWidth(1)) -; (t0:SIntType,t1:SIntType) : PlusWidth(width!(args(e)[0]),IntWidth(1)) -; (t0,t1) : width!(args(e)[0]) -; REM-OP : -; match(type(args(e)[0]),type(args(e)[1])) : -; (t0:SIntType,t1:UIntType) : PlusWidth(width!(args(e)[1]),IntWidth(1)) -; (t0,t1) : width!(args(e)[1]) -; ADD-WRAP-OP : get-max(0,1) -; SUB-WRAP-OP : get-max(0,1) -; LESS-OP : IntWidth(1) -; LESS-EQ-OP : IntWidth(1) -; GREATER-OP : IntWidth(1) -; GREATER-EQ-OP : IntWidth(1) -; EQUAL-OP : IntWidth(1) -; NEQUAL-OP : IntWidth(1) -; EQUIV-OP : IntWidth(1) -; NEQUIV-OP : IntWidth(1) -; MUX-OP : -; add(v,WGeq(IntWidth(1),width!(args(e)[0]))) -; add(v,WGeq(width!(args(e)[0]),IntWidth(1))) -; get-max(1,2) -; PAD-OP : IntWidth(consts(e)[0]) -; AS-UINT-OP : width!(args(e)[0]) -; AS-SINT-OP : width!(args(e)[0]) -; SHIFT-LEFT-OP : PlusWidth(width!(args(e)[0]),IntWidth(consts(e)[0])) -; SHIFT-RIGHT-OP : MinusWidth(width!(args(e)[0]),IntWidth(consts(e)[0])) -; DYN-SHIFT-LEFT-OP : PlusWidth(width!(args(e)[0]),ExpWidth(width!(args(e)[1]))) -; DYN-SHIFT-RIGHT-OP : width!(args(e)[0]) -; CONVERT-OP : -; match(type(args(e)[0])) : -; (t0:UIntType) : PlusWidth(width!(args(e)[0]),IntWidth(1)) -; (t0:SIntType) : width!(args(e)[0]) -; NEG-OP : PlusWidth(width!(args(e)[0]),IntWidth(1)) -; BIT-NOT-OP : width!(args(e)[0]) -; BIT-AND-OP : get-max(0,1) -; BIT-OR-OP : get-max(0,1) -; BIT-XOR-OP : get-max(0,1) -; BIT-AND-REDUCE-OP : all-max() -; BIT-OR-REDUCE-OP : all-max() -; BIT-XOR-REDUCE-OP : all-max() -; CONCAT-OP : PlusWidth(width!(args(e)[0]),width!(args(e)[1])) -; BIT-SELECT-OP : IntWidth(1) -; BITS-SELECT-OP : IntWidth(consts(e)[0] - consts(e)[1] + 1) -; -; match(type(e)) : -; (t:UIntType) : UIntType(w*) -; (t:SIntType) : SIntType(w*) -; (t) : error("Shouldn't be here") -; diff --git a/src/main/stanza/symbolic-value.stanza b/src/main/stanza/symbolic-value.stanza deleted file mode 100644 index 3d073f1b..00000000 --- a/src/main/stanza/symbolic-value.stanza +++ /dev/null @@ -1,95 +0,0 @@ -;Copyright (c) 2014 - 2016 The Regents of the University of -;California (Regents). All Rights Reserved. Redistribution and use in -;source and binary forms, with or without modification, are permitted -;provided that the following conditions are met: -; * Redistributions of source code must retain the above -; copyright notice, this list of conditions and the following -; two paragraphs of disclaimer. -; * Redistributions in binary form must reproduce the above -; copyright notice, this list of conditions and the following -; two paragraphs of disclaimer in the documentation and/or other materials -; provided with the distribution. -; * Neither the name of the Regents nor the names of its contributors -; may be used to endorse or promote products derived from this -; software without specific prior written permission. -;IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, -;SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, -;ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF -;REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT -;LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -;A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF -;ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION -;TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR -;MODIFICATIONS. -defpackage firrtl/symbolic-value : - import core - import verse - import firrtl/ir2 - import firrtl/ir-utils - -; ======= Symbolic Value Library ========== -public definterface SymbolicValue -public defstruct SVExp <: SymbolicValue : - exp : Expression -public defstruct SVMux <: SymbolicValue : - pred : Expression - conseq : SymbolicValue - alt : SymbolicValue -public defstruct SVNul <: SymbolicValue - -defmethod print (o:OutputStream, sv:SymbolicValue) : - match(sv) : - (sv: SVExp) : print(o, exp(sv)) - (sv: SVMux) : print-all(o, ["(" pred(sv) " ? " conseq(sv) " : " alt(sv) ")"]) - (sv: SVNul) : print(o, "SVNUL") - -defn map (f: Expression -> Expression, sv:SymbolicValue) -> SymbolicValue : - match(sv) : - (sv:SVMux) : SVMux(f(pred(sv)),conseq(sv),alt(sv)) - (sv:SVExp) : SVExp(f(exp(sv))) - (sv:SVNul) : sv - -defmulti map<?T> (f: SymbolicValue -> SymbolicValue, sv:?T&SymbolicValue) -> T -defmethod map (f: SymbolicValue -> SymbolicValue, sv:SymbolicValue) -> SymbolicValue : - match(sv) : - (sv: SVMux) : SVMux(pred(sv),f(conseq(sv)),f(alt(sv))) - (sv) : sv - -defn do (f:SymbolicValue -> ?, s:SymbolicValue) -> False : - defn f* (sv:SymbolicValue) -> SymbolicValue : - f(sv) - sv - map(f*,s) - false - -defn dor (f:SymbolicValue -> ?, e:SymbolicValue) -> False : - do(f,e) - defn f* (x:SymbolicValue) -> SymbolicValue : - dor(f,x) - x - map(f*,e) - false - -defmethod equal? (a:SymbolicValue,b:SymbolicValue) -> True|False : - match(a,b) : - (a:SVNul,b:SVNul) : true - (a:SVExp,b:SVExp) : exp(a) == exp(b) - (a:SVMux,b:SVMux) : pred(a) == pred(b) and conseq(a) == conseq(b) and alt(a) == alt(b) - (a,b) : false - -;TODO add invert to primop -defn optimize (sv:SymbolicValue) -> SymbolicValue : - match(map(optimize,sv)) : - (sv:SVMux) : - if conseq(sv) == alt(sv) : conseq(sv) - else : - match(conseq(sv),alt(sv)) : - (c:SVExp,a:SVExp) : - if exp(c) == one and exp(a) == zero : SVExp(pred(sv)) - else if exp(c) == zero and exp(a) == one : SVExp(NOT(pred(sv))) - else if exp(c) == exp(a) : c - else : sv - (c,a) : sv - (sv) : sv - diff --git a/src/main/stanza/widthsolver.stanza b/src/main/stanza/widthsolver.stanza deleted file mode 100644 index b3f72f03..00000000 --- a/src/main/stanza/widthsolver.stanza +++ /dev/null @@ -1,322 +0,0 @@ -;Copyright (c) 2014 - 2016 The Regents of the University of -;California (Regents). All Rights Reserved. Redistribution and use in -;source and binary forms, with or without modification, are permitted -;provided that the following conditions are met: -; * Redistributions of source code must retain the above -; copyright notice, this list of conditions and the following -; two paragraphs of disclaimer. -; * Redistributions in binary form must reproduce the above -; copyright notice, this list of conditions and the following -; two paragraphs of disclaimer in the documentation and/or other materials -; provided with the distribution. -; * Neither the name of the Regents nor the names of its contributors -; may be used to endorse or promote products derived from this -; software without specific prior written permission. -;IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, -;SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, -;ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF -;REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT -;LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -;A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF -;ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION -;TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR -;MODIFICATIONS. -;Define the STANDALONE flag to run STANDALONE -#if-defined(STANDALONE) : - #include<"core/stringeater.stanza"> - #include<"compiler/lexer.stanza"> - -defpackage widthsolver : - import core - import verse - import stz/lexer - -;============= Language of Constraints ====================== -public definterface WConstraint -public defstruct WidthEqual <: WConstraint : - name: Symbol - value: Exp -public defstruct WidthGreater <: WConstraint : - name: Symbol - value: Exp - -defmethod print (o:OutputStream, c:WConstraint) : - print-all{o, _} $ - match(c) : - (c:WidthEqual) : [name(c) " = " value(c)] - (c:WidthGreater) : [name(c) " >= " value(c)] - -defn construct-eqns (cs: Streamable<WConstraint>) : - val eqns = HashTable<Symbol, False|Exp>(symbol-hash) - val lower-bounds = HashTable<Symbol, List<Exp>>(symbol-hash) - for c in cs do : - match(c) : - (c:WidthEqual) : - eqns[name(c)] = value(c) - (c:WidthGreater) : - lower-bounds[name(c)] = - List(value(c), - get?(lower-bounds, name(c), List())) - - ;Create minimum expressions for lower-bounds - for entry in lower-bounds do : - val v = key(entry) - val exps = value(entry) - if not key?(eqns, v) : - eqns[v] = reduce(EMax, ELit(0), exps) - - ;Return equations - eqns -;============================================================ - -;============= Language of Expressions ====================== -public definterface Exp -public defstruct EVar <: Exp : - name: Symbol -public defstruct EMax <: Exp : - a: Exp - b: Exp -public defstruct EPlus <: Exp : - a: Exp - b: Exp -public defstruct EMinus <: Exp : - a: Exp - b: Exp -public defstruct ELit <: Exp : - width: Int - -defmethod print (o:OutputStream, e:Exp) : - match(e) : - (e:EVar) : print(o, name(e)) - (e:EMax) : print-all(o, ["max(" a(e) ", " b(e) ")"]) - (e:EPlus) : print-all(o, [a(e) " + " b(e)]) - (e:EMinus) : print-all(o, [a(e) " - " b(e)]) - (e:ELit) : print(o, width(e)) - -defn map (f: (Exp) -> Exp, e: Exp) -> Exp : - match(e) : - (e:EMax) : EMax(f(a(e)), f(b(e))) - (e:EPlus) : EPlus(f(a(e)), f(b(e))) - (e:EMinus) : EMinus(f(a(e)), f(b(e))) - (e:Exp) : e - -defn children (e: Exp) -> List<Exp> : - match(e) : - (e:EMax) : list(a(e), b(e)) - (e:EPlus) : list(a(e), b(e)) - (e:EMinus) : list(a(e), b(e)) - (e:Exp) : list() -;============================================================ - -;================== Reading from File ======================= -defn read-exp (x) : - match(unwrap-token(x)) : - (x:Symbol) : - EVar(x) - (x:Int) : - ELit(x) - (x:List) : - val tag = unwrap-token(x[1]) - switch {tag == _} : - `plus : EPlus(read-exp(x[2]), read-exp(x[3])) - `minus : EMinus(read-exp(x[2]), read-exp(x[3])) - `max : EMax(read-exp(x[2]), read-exp(x[3])) - else : error $ string-join $ - ["Improper expression: " x] - -defn read (filename: String) : - var form:List = lex-file(filename) - val cs = Vector<WConstraint>() - while not empty?(form) : - val x = unwrap-token(form[0]) - val op = form[1] - val e = read-exp(form[2]) - form = tailn(form, 3) - add{cs, _} $ - switch {unwrap-token(op) == _} : - `= : WidthEqual(x, e) - `>= : WidthGreater(x, e) - else : error $ string-join $ ["Unsupported Operator: " op] - cs -;============================================================ - -;============ Operations on Expressions ===================== -defn occurs? (v: Symbol, exp: Exp) : - match(exp) : - (exp: EVar) : name(exp) == v - (exp: Exp) : any?(occurs?{v, _}, children(exp)) - -defn freevars (exp: Exp) : - to-list $ generate<Symbol> : - defn loop (exp: Exp) : - match(exp) : - (exp: EVar) : yield(name(exp)) - (exp: Exp) : do(loop, children(exp)) - loop(exp) - -defn contains-only-max? (exp: Exp) : - match(exp) : - (exp:EVar|EMax|ELit) : all?(contains-only-max?, children(exp)) - (exp) : false - -defn simplify (exp: Exp) : - match(map(simplify,exp)) : - (exp: EPlus) : - match(a(exp), b(exp)) : - (a: ELit, b: ELit) : - ELit(width(a) + width(b)) - (a: ELit, b) : - if width(a) == 0 : b - else : exp - (a, b: ELit) : - if width(b) == 0 : a - else : exp - (a, b) : - exp - (exp: EMinus) : - match(a(exp), b(exp)) : - (a: ELit, b: ELit) : - ELit(width(a) - width(b)) - (a, b: ELit) : - if width(b) == 0 : a - else : exp - (a, b) : - exp - (exp: EMax) : - match(a(exp), b(exp)) : - (a: ELit, b: ELit) : - ELit(max(width(a), width(b))) - (a: ELit, b) : - if width(a) == 0 : b - else : exp - (a, b: ELit) : - if width(b) == 0 : a - else : exp - (a, b) : - exp - (exp: Exp) : - exp - -defn eval (exp: Exp, state: HashTable<Symbol,Int>) -> Int : - defn loop (e: Exp) -> Int : - match(e) : - (e: EVar) : state[name(e)] - (e: EMax) : max(loop(a(e)), loop(b(e))) - (e: EPlus) : loop(a(e)) + loop(b(e)) - (e: EMinus) : loop(a(e)) - loop(b(e)) - (e: ELit) : width(e) - loop(exp) -;============================================================ - - -;================ Constraint Solver ========================= -defn substitute (solns: HashTable<Symbol, Exp>, exp: Exp) : - match(exp) : - (exp: EVar) : - match(get?(solns, name(exp), false)) : - (s:Exp) : substitute(solns, s) - (f:False) : exp - (exp) : - map(substitute{solns, _}, exp) - -defn dataflow (eqns: HashTable<Symbol, False|Exp>, solns: HashTable<Symbol,Exp>) : - var progress?:True|False = false - for entry in eqns do : - if value(entry) != false : - val v = key(entry) - val exp = simplify(substitute(solns, value(entry) as Exp)) - if occurs?(v, exp) : - eqns[v] = exp - else : - eqns[v] = false - solns[v] = exp - progress? = true - progress? - -defn fixpoint (eqns: HashTable<Symbol, False|Exp>, solns: HashTable<Symbol,Exp>) : - label<False|True> break : - for v in keys(eqns) do : - if eqns[v] != false : - val fix-eqns = fixpoint-eqns(v, eqns) - val has-fixpoint? = all?(contains-only-max?{value(_)}, fix-eqns) - if has-fixpoint? : - val soln = solve-fixpoint(fix-eqns) - for s in soln do : - solns[key(s)] = ELit(value(s)) - eqns[key(s)] = false - break(true) - false - -defn fixpoint-eqns (v: Symbol, eqns: HashTable<Symbol,False|Exp>) : - val vs = HashTable<Symbol,Exp>(symbol-hash) - defn loop (v: Symbol) : - if not key?(vs, v) : - val eqn = eqns[v] as Exp - vs[v] = eqn - do(loop, freevars(eqn)) - loop(v) - to-list(vs) - -defn solve-fixpoint (eqns: List<KeyValue<Symbol,Exp>>) : - ;Solve for fixpoint - val sol = HashTable<Symbol,Int>(symbol-hash) - do({sol[key(_)] = 0}, eqns) - defn loop () : - var progress?:True|False = false - for eqn in eqns do : - val v = key(eqn) - val x = eval(value(eqn), sol) - if x != sol[v] : - sol[v] = x - progress? = true - progress? - while loop() : false - - ;Return solutions - to-list(sol) - -defn backsubstitute (vs:Streamable<Symbol>, solns: HashTable<Symbol,Exp>) : - val widths = HashTable<Symbol,False|Int>(symbol-hash) - defn get-width (v:Symbol) : - if key?(solns, v) : - val vs = freevars(solns[v]) - ;Calculate dependencies - for v in vs do : - if not key?(widths, v) : - widths[v] = get-width(v) - ;Compute value - if none?({widths[_] == false}, vs) : - eval(solns[v], widths as HashTable<Symbol,Int>) - - ;Compute all widths - for v in vs do : - widths[v] = get-width(v) - - ;Return widths - to-list $ generate<WidthEqual> : - for entry in widths do : - if value(entry) != false : - yield $ WidthEqual(key(entry), ELit(value(entry) as Int)) - -public defn solve-widths (cs: Streamable<WConstraint>) : - ;Copy to new hashtable - val eqns = construct-eqns(cs) - val solns = HashTable<Symbol,Exp>(symbol-hash) - defn loop () : - dataflow(eqns, solns) or - fixpoint(eqns, solns) - while loop() : false - backsubstitute(keys(eqns), solns) - -;================= Main ===================================== -#if-defined(STANDALONE) : - defn main () : - val input = lex(commandline-arguments()) - error("No input file!") when length(input) < 2 - val cs = read(to-string(input[1])) - do(println, solve-widths(cs)) - - main() -;============================================================ - diff --git a/test/chirrtl/infer-mport-dir.fir b/test/chirrtl/infer-mport-dir.fir deleted file mode 100644 index 50baeff2..00000000 --- a/test/chirrtl/infer-mport-dir.fir +++ /dev/null @@ -1,22 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; CHECK: Done! -circuit top : - module top : - input clk : Clock - wire p : UInt - wire q : UInt - cmem m : {a:UInt<4>,b:UInt<4>}[10] - p <= UInt(1) - q <= UInt(1) - wire x : {a:UInt<4>,b:UInt<4>} - x.a <= UInt(1) - x.b <= UInt(1) - when p : - infer mport a = m[UInt(3)],clk - infer mport b = m[UInt(3)],clk - infer mport c = m[UInt(3)],clk - when q : - a <= x - x <= b - c <= x - x <= c diff --git a/test/chirrtl/mask-bug.fir b/test/chirrtl/mask-bug.fir deleted file mode 100644 index b580c075..00000000 --- a/test/chirrtl/mask-bug.fir +++ /dev/null @@ -1,20 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; CHECK: Done! -circuit top : - module top : - input clk : Clock - wire p : UInt - wire q : UInt - cmem m : {a:UInt<4>,b:{c: UInt<4>,d:UInt<4>}}[10] - p <= UInt(1) - q <= UInt(1) - wire x : {a:UInt<4>,b:{c: UInt<4>,d:UInt<4>}} - x.a <= UInt(1) - x.b.c <= UInt(1) - x.b.d <= UInt(1) - when p : - write mport a = m[UInt(3)],clk - when q : - a <- x - - diff --git a/test/chirrtl/wacc-wdc.fir b/test/chirrtl/wacc-wdc.fir deleted file mode 100644 index 3cb5141d..00000000 --- a/test/chirrtl/wacc-wdc.fir +++ /dev/null @@ -1,54 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -circuit top : - module top : - input clk : Clock - wire p : UInt - wire q : UInt - cmem m : {a:UInt<4>,b:UInt<4>}[10] - p <= UInt(1) - q <= UInt(1) - wire x : {a:UInt<4>,b:UInt<4>} - x.a <= UInt(1) - x.b <= UInt(1) - when p : - write mport a = m[UInt(3)],clk - when q : - a <= x - - -; CHECK: Remove CHIRRTL - -; CHECK: circuit top : -; CHECK: module top : -; CHECK: input clk : Clock -; CHECK: wire p : UInt -; CHECK: wire q : UInt -; CHECK: mem m : -; CHECK: data-type => { a : UInt<4>, b : UInt<4>} -; CHECK: depth => 10 -; CHECK: write-latency => 1 -; CHECK: read-latency => 0 -; CHECK: writer => a -; CHECK: m.a.addr is invalid -; CHECK: m.a.clk <= clk -; CHECK: m.a.en <= UInt<1>("h0") -; CHECK: m.a.data is invalid -; CHECK: m.a.mask.a <= UInt<1>("h0") -; CHECK: m.a.mask.b <= UInt<1>("h0") -; CHECK: p <= UInt<1>("h1") -; CHECK: q <= UInt<1>("h1") -; CHECK: wire x : { a : UInt<4>, b : UInt<4>} -; CHECK: x.a <= UInt<1>("h1") -; CHECK: x.b <= UInt<1>("h1") -; CHECK: when p : -; CHECK: m.a.addr <= UInt<2>("h3") -; CHECK: m.a.en <= UInt<1>("h1") -; CHECK: when q : -; CHECK: m.a.data <= x -; CHECK: m.a.mask.a <= UInt<1>("h1") -; CHECK: m.a.mask.b <= UInt<1>("h1") - -; CHECK: Finished Remove CHIRRTL -; CHECK: Done! - - diff --git a/test/custom/when-coverage/gcd.fir b/test/custom/when-coverage/gcd.fir deleted file mode 100644 index b07c313b..00000000 --- a/test/custom/when-coverage/gcd.fir +++ /dev/null @@ -1,52 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilute -s coverage -s when-scope -p c 2>&1 | tee %s.out | FileCheck %s -; XFAIL: * - -;CHECK: Verilog -circuit top : - module subtracter : - input x : UInt - input y : UInt - output q : UInt - q <= subw(x, y) - module gcd : - input a : UInt<16> - input b : UInt<16> - input e : UInt<1> - input clk : Clock - input reset : UInt<1> - output z : UInt<16> - output v : UInt<1> - reg x : UInt,clk,reset - reg y : UInt,clk,reset - onreset x <= UInt(0) - onreset y <= UInt(42) - when gt(x, y) : - inst s of subtracter - s.x <= x - s.y <= y - x <= s.q - else : - inst s2 of subtracter - s2.x <= x - s2.y <= y - y <= s2.q - when e : - x <= a - y <= b - v <= eqv(v, UInt(0)) - z <= x - module top : - input a : UInt<16> - input b : UInt<16> - input clk : Clock - input reset : UInt<1> - output z : UInt - inst i of gcd - i.a <= a - i.b <= b - i.e <= UInt(1) - i.clk <= clk - i.reset <= reset - z <= i.z -;CHECK: Done! - diff --git a/test/errors/gender/BulkWrong.fir b/test/errors/gender/BulkWrong.fir deleted file mode 100644 index c9b24aa2..00000000 --- a/test/errors/gender/BulkWrong.fir +++ /dev/null @@ -1,26 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; CHECK: Expression in is used as a sink but can only be used as a source. -; CHECK: Expression out.y is used as a sink but can only be used as a source. -; CHECK: Expression in.y.z is used as a sink but can only be used as a source. -; CHECK: Expression in.y.z is used as a sink but can only be used as a source. - -circuit BTB : - module BTB : - input in : {x : UInt<1>, flip y : {flip z : UInt<1>}} - output out : {x : UInt<1>, flip y : {flip z : UInt<1>}} - - in <- out - out.y <- in.y - out.y.z <- in.y.z - - wire w : {x : UInt<1>, flip y : {flip z : UInt<1>}} - w <- in - in.y <- w.y - in.y.z <- w.y.z - - w.x <= add(in.x,in.y.z) - - out <- in - in.y <- out.y - in.y.z <- out.y.z - diff --git a/test/errors/gender/InstancePorts.fir b/test/errors/gender/InstancePorts.fir deleted file mode 100644 index 3f5ae8c7..00000000 --- a/test/errors/gender/InstancePorts.fir +++ /dev/null @@ -1,17 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; CHECK-NOT: Expression queue.in is used as a sink but can only be used as a source. -; CHECK: Done! - -circuit BTB : - module Queue : - input in : UInt<1> - output out : UInt<1> - out <= in - module BTB : - input time : UInt<1> - output out : UInt<1> - - inst queue of Queue - queue.in <= time - out <= queue.in - diff --git a/test/errors/gender/ReadOutput.fir b/test/errors/gender/ReadOutput.fir deleted file mode 100644 index f9e8f7b4..00000000 --- a/test/errors/gender/ReadOutput.fir +++ /dev/null @@ -1,12 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; CHECK: Expression out is used as a source but can only be used as a sink. - -circuit BTB : - module BTB : - output out : {x : UInt<1>, flip y : UInt<1>} - - wire w : {x : UInt<1>, flip y : UInt<1>} - w.x <= UInt(1) - w.y <= UInt(1) - out.x <= UInt(1) - w <- out diff --git a/test/errors/gender/bad_bulk_connect.fir b/test/errors/gender/bad_bulk_connect.fir deleted file mode 100644 index 984d8da0..00000000 --- a/test/errors/gender/bad_bulk_connect.fir +++ /dev/null @@ -1,328 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; CHECK: Expression out.grant is used as a sink but can only be used as a source. - -circuit ClientTileLinkIOWrapper_49 : - module ClientTileLinkIOWrapper_49 : - input clock : Clock - input reset : UInt<1> - input in : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}} - output out : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}} - - in.grant.bits.g_type <= UInt<1>("h00") - in.grant.bits.is_builtin_type <= UInt<1>("h00") - in.grant.bits.manager_xact_id <= UInt<1>("h00") - in.grant.bits.client_xact_id <= UInt<1>("h00") - in.grant.bits.data <= UInt<1>("h00") - in.grant.bits.addr_beat <= UInt<1>("h00") - in.grant.valid <= UInt<1>("h00") - in.acquire.ready <= UInt<1>("h00") - out.release.bits.voluntary <= UInt<1>("h00") - out.release.bits.r_type <= UInt<1>("h00") - out.release.bits.data <= UInt<1>("h00") - out.release.bits.addr_beat <= UInt<1>("h00") - out.release.bits.client_xact_id <= UInt<1>("h00") - out.release.bits.addr_block <= UInt<1>("h00") - out.release.valid <= UInt<1>("h00") - out.probe.ready <= UInt<1>("h00") - out.grant.ready <= UInt<1>("h00") - out.acquire.bits.union <= UInt<1>("h00") - out.acquire.bits.a_type <= UInt<1>("h00") - out.acquire.bits.is_builtin_type <= UInt<1>("h00") - out.acquire.bits.data <= UInt<1>("h00") - out.acquire.bits.addr_beat <= UInt<1>("h00") - out.acquire.bits.client_xact_id <= UInt<1>("h00") - out.acquire.bits.addr_block <= UInt<1>("h00") - out.acquire.valid <= UInt<1>("h00") - - wire T_173394 : UInt<2>[2] - T_173394[0] <= UInt<2>("h01") - T_173394[1] <= UInt<2>("h02") - wire T_173397 : UInt<2>[2] - T_173397[0] <= UInt<2>("h01") - T_173397[1] <= UInt<2>("h02") - wire T_173399 : UInt<2>[1] - T_173399[0] <= UInt<2>("h02") - wire T_173439 : UInt<2>[2] - T_173439[0] <= UInt<2>("h01") - T_173439[1] <= UInt<2>("h02") - wire T_173442 : UInt<2>[2] - T_173442[0] <= UInt<2>("h01") - T_173442[1] <= UInt<2>("h02") - wire T_173444 : UInt<2>[1] - T_173444[0] <= UInt<2>("h02") - wire T_173483 : UInt<2>[2] - T_173483[0] <= UInt<2>("h01") - T_173483[1] <= UInt<2>("h02") - wire T_173486 : UInt<2>[2] - T_173486[0] <= UInt<2>("h01") - T_173486[1] <= UInt<2>("h02") - wire T_173488 : UInt<2>[1] - T_173488[0] <= UInt<2>("h02") - wire T_173537 : UInt<2>[2] - T_173537[0] <= UInt<2>("h01") - T_173537[1] <= UInt<2>("h02") - wire T_173540 : UInt<2>[2] - T_173540[0] <= UInt<2>("h01") - T_173540[1] <= UInt<2>("h02") - wire T_173542 : UInt<2>[1] - T_173542[0] <= UInt<2>("h02") - wire T_173588 : UInt<2>[2] - T_173588[0] <= UInt<2>("h01") - T_173588[1] <= UInt<2>("h02") - wire T_173591 : UInt<2>[2] - T_173591[0] <= UInt<2>("h01") - T_173591[1] <= UInt<2>("h02") - wire T_173593 : UInt<2>[1] - T_173593[0] <= UInt<2>("h02") - wire T_173639 : UInt<2>[2] - T_173639[0] <= UInt<2>("h01") - T_173639[1] <= UInt<2>("h02") - wire T_173642 : UInt<2>[2] - T_173642[0] <= UInt<2>("h01") - T_173642[1] <= UInt<2>("h02") - wire T_173644 : UInt<2>[1] - T_173644[0] <= UInt<2>("h02") - wire T_173692 : UInt<2>[2] - T_173692[0] <= UInt<2>("h01") - T_173692[1] <= UInt<2>("h02") - wire T_173695 : UInt<2>[2] - T_173695[0] <= UInt<2>("h01") - T_173695[1] <= UInt<2>("h02") - wire T_173697 : UInt<2>[1] - T_173697[0] <= UInt<2>("h02") - wire T_173742 : UInt<2>[2] - T_173742[0] <= UInt<2>("h01") - T_173742[1] <= UInt<2>("h02") - wire T_173745 : UInt<2>[2] - T_173745[0] <= UInt<2>("h01") - T_173745[1] <= UInt<2>("h02") - wire T_173747 : UInt<2>[1] - T_173747[0] <= UInt<2>("h02") - wire T_173795 : UInt<2>[2] - T_173795[0] <= UInt<2>("h01") - T_173795[1] <= UInt<2>("h02") - wire T_173798 : UInt<2>[2] - T_173798[0] <= UInt<2>("h01") - T_173798[1] <= UInt<2>("h02") - wire T_173800 : UInt<2>[1] - T_173800[0] <= UInt<2>("h02") - wire T_173845 : UInt<2>[2] - T_173845[0] <= UInt<2>("h01") - T_173845[1] <= UInt<2>("h02") - wire T_173848 : UInt<2>[2] - T_173848[0] <= UInt<2>("h01") - T_173848[1] <= UInt<2>("h02") - wire T_173850 : UInt<2>[1] - T_173850[0] <= UInt<2>("h02") - wire T_173895 : UInt<2>[2] - T_173895[0] <= UInt<2>("h01") - T_173895[1] <= UInt<2>("h02") - wire T_173898 : UInt<2>[2] - T_173898[0] <= UInt<2>("h01") - T_173898[1] <= UInt<2>("h02") - wire T_173900 : UInt<2>[1] - T_173900[0] <= UInt<2>("h02") - wire T_173939 : UInt<2>[2] - T_173939[0] <= UInt<2>("h01") - T_173939[1] <= UInt<2>("h02") - wire T_173942 : UInt<2>[2] - T_173942[0] <= UInt<2>("h01") - T_173942[1] <= UInt<2>("h02") - wire T_173944 : UInt<2>[1] - T_173944[0] <= UInt<2>("h02") - wire T_173993 : UInt<2>[2] - T_173993[0] <= UInt<2>("h01") - T_173993[1] <= UInt<2>("h02") - wire T_173996 : UInt<2>[2] - T_173996[0] <= UInt<2>("h01") - T_173996[1] <= UInt<2>("h02") - wire T_173998 : UInt<2>[1] - T_173998[0] <= UInt<2>("h02") - wire T_174044 : UInt<2>[2] - T_174044[0] <= UInt<2>("h01") - T_174044[1] <= UInt<2>("h02") - wire T_174047 : UInt<2>[2] - T_174047[0] <= UInt<2>("h01") - T_174047[1] <= UInt<2>("h02") - wire T_174049 : UInt<2>[1] - T_174049[0] <= UInt<2>("h02") - wire T_174095 : UInt<2>[2] - T_174095[0] <= UInt<2>("h01") - T_174095[1] <= UInt<2>("h02") - wire T_174098 : UInt<2>[2] - T_174098[0] <= UInt<2>("h01") - T_174098[1] <= UInt<2>("h02") - wire T_174100 : UInt<2>[1] - T_174100[0] <= UInt<2>("h02") - wire T_174148 : UInt<2>[2] - T_174148[0] <= UInt<2>("h01") - T_174148[1] <= UInt<2>("h02") - wire T_174151 : UInt<2>[2] - T_174151[0] <= UInt<2>("h01") - T_174151[1] <= UInt<2>("h02") - wire T_174153 : UInt<2>[1] - T_174153[0] <= UInt<2>("h02") - wire T_174198 : UInt<2>[2] - T_174198[0] <= UInt<2>("h01") - T_174198[1] <= UInt<2>("h02") - wire T_174201 : UInt<2>[2] - T_174201[0] <= UInt<2>("h01") - T_174201[1] <= UInt<2>("h02") - wire T_174203 : UInt<2>[1] - T_174203[0] <= UInt<2>("h02") - wire T_174251 : UInt<2>[2] - T_174251[0] <= UInt<2>("h01") - T_174251[1] <= UInt<2>("h02") - wire T_174254 : UInt<2>[2] - T_174254[0] <= UInt<2>("h01") - T_174254[1] <= UInt<2>("h02") - wire T_174256 : UInt<2>[1] - T_174256[0] <= UInt<2>("h02") - wire T_174301 : UInt<2>[2] - T_174301[0] <= UInt<2>("h01") - T_174301[1] <= UInt<2>("h02") - wire T_174304 : UInt<2>[2] - T_174304[0] <= UInt<2>("h01") - T_174304[1] <= UInt<2>("h02") - wire T_174306 : UInt<2>[1] - T_174306[0] <= UInt<2>("h02") - wire T_174351 : UInt<2>[2] - T_174351[0] <= UInt<2>("h01") - T_174351[1] <= UInt<2>("h02") - wire T_174354 : UInt<2>[2] - T_174354[0] <= UInt<2>("h01") - T_174354[1] <= UInt<2>("h02") - wire T_174356 : UInt<2>[1] - T_174356[0] <= UInt<2>("h02") - wire T_174395 : UInt<2>[2] - T_174395[0] <= UInt<2>("h01") - T_174395[1] <= UInt<2>("h02") - wire T_174398 : UInt<2>[2] - T_174398[0] <= UInt<2>("h01") - T_174398[1] <= UInt<2>("h02") - wire T_174400 : UInt<2>[1] - T_174400[0] <= UInt<2>("h02") - wire T_174449 : UInt<2>[2] - T_174449[0] <= UInt<2>("h01") - T_174449[1] <= UInt<2>("h02") - wire T_174452 : UInt<2>[2] - T_174452[0] <= UInt<2>("h01") - T_174452[1] <= UInt<2>("h02") - wire T_174454 : UInt<2>[1] - T_174454[0] <= UInt<2>("h02") - wire T_174500 : UInt<2>[2] - T_174500[0] <= UInt<2>("h01") - T_174500[1] <= UInt<2>("h02") - wire T_174503 : UInt<2>[2] - T_174503[0] <= UInt<2>("h01") - T_174503[1] <= UInt<2>("h02") - wire T_174505 : UInt<2>[1] - T_174505[0] <= UInt<2>("h02") - wire T_174551 : UInt<2>[2] - T_174551[0] <= UInt<2>("h01") - T_174551[1] <= UInt<2>("h02") - wire T_174554 : UInt<2>[2] - T_174554[0] <= UInt<2>("h01") - T_174554[1] <= UInt<2>("h02") - wire T_174556 : UInt<2>[1] - T_174556[0] <= UInt<2>("h02") - wire T_174604 : UInt<2>[2] - T_174604[0] <= UInt<2>("h01") - T_174604[1] <= UInt<2>("h02") - wire T_174607 : UInt<2>[2] - T_174607[0] <= UInt<2>("h01") - T_174607[1] <= UInt<2>("h02") - wire T_174609 : UInt<2>[1] - T_174609[0] <= UInt<2>("h02") - wire T_174654 : UInt<2>[2] - T_174654[0] <= UInt<2>("h01") - T_174654[1] <= UInt<2>("h02") - wire T_174657 : UInt<2>[2] - T_174657[0] <= UInt<2>("h01") - T_174657[1] <= UInt<2>("h02") - wire T_174659 : UInt<2>[1] - T_174659[0] <= UInt<2>("h02") - wire T_174707 : UInt<2>[2] - T_174707[0] <= UInt<2>("h01") - T_174707[1] <= UInt<2>("h02") - wire T_174710 : UInt<2>[2] - T_174710[0] <= UInt<2>("h01") - T_174710[1] <= UInt<2>("h02") - wire T_174712 : UInt<2>[1] - T_174712[0] <= UInt<2>("h02") - wire T_174757 : UInt<2>[2] - T_174757[0] <= UInt<2>("h01") - T_174757[1] <= UInt<2>("h02") - wire T_174760 : UInt<2>[2] - T_174760[0] <= UInt<2>("h01") - T_174760[1] <= UInt<2>("h02") - wire T_174762 : UInt<2>[1] - T_174762[0] <= UInt<2>("h02") - wire T_174807 : UInt<2>[2] - T_174807[0] <= UInt<2>("h01") - T_174807[1] <= UInt<2>("h02") - wire T_174810 : UInt<2>[2] - T_174810[0] <= UInt<2>("h01") - T_174810[1] <= UInt<2>("h02") - wire T_174812 : UInt<2>[1] - T_174812[0] <= UInt<2>("h02") - wire T_174856 : UInt<2>[2] - T_174856[0] <= UInt<2>("h01") - T_174856[1] <= UInt<2>("h02") - wire T_174859 : UInt<2>[2] - T_174859[0] <= UInt<2>("h01") - T_174859[1] <= UInt<2>("h02") - wire T_174861 : UInt<2>[1] - T_174861[0] <= UInt<2>("h02") - wire T_174902 : UInt<2>[2] - T_174902[0] <= UInt<2>("h01") - T_174902[1] <= UInt<2>("h02") - wire T_174905 : UInt<2>[2] - T_174905[0] <= UInt<2>("h01") - T_174905[1] <= UInt<2>("h02") - wire T_174907 : UInt<2>[1] - T_174907[0] <= UInt<2>("h02") - wire T_174951 : UInt<2>[2] - T_174951[0] <= UInt<2>("h01") - T_174951[1] <= UInt<2>("h02") - wire T_174954 : UInt<2>[2] - T_174954[0] <= UInt<2>("h01") - T_174954[1] <= UInt<2>("h02") - wire T_174956 : UInt<2>[1] - T_174956[0] <= UInt<2>("h02") - wire T_174997 : UInt<2>[2] - T_174997[0] <= UInt<2>("h01") - T_174997[1] <= UInt<2>("h02") - wire T_175000 : UInt<2>[2] - T_175000[0] <= UInt<2>("h01") - T_175000[1] <= UInt<2>("h02") - wire T_175002 : UInt<2>[1] - T_175002[0] <= UInt<2>("h02") - wire T_175043 : UInt<2>[2] - T_175043[0] <= UInt<2>("h01") - T_175043[1] <= UInt<2>("h02") - wire T_175046 : UInt<2>[2] - T_175046[0] <= UInt<2>("h01") - T_175046[1] <= UInt<2>("h02") - wire T_175048 : UInt<2>[1] - T_175048[0] <= UInt<2>("h02") - wire T_175096 : UInt<2>[2] - T_175096[0] <= UInt<2>("h01") - T_175096[1] <= UInt<2>("h02") - wire T_175099 : UInt<2>[2] - T_175099[0] <= UInt<2>("h01") - T_175099[1] <= UInt<2>("h02") - wire T_175101 : UInt<2>[1] - T_175101[0] <= UInt<2>("h02") - wire T_175146 : UInt<2>[2] - T_175146[0] <= UInt<2>("h01") - T_175146[1] <= UInt<2>("h02") - wire T_175149 : UInt<2>[2] - T_175149[0] <= UInt<2>("h01") - T_175149[1] <= UInt<2>("h02") - wire T_175151 : UInt<2>[1] - T_175151[0] <= UInt<2>("h02") - out.acquire <- in.acquire - out.grant <- in.grant - out.probe.ready <= UInt<1>("h01") - out.release.valid <= UInt<1>("h00") diff --git a/test/errors/high-form/Flip-Mem.fir b/test/errors/high-form/Flip-Mem.fir deleted file mode 100644 index a8cb67ca..00000000 --- a/test/errors/high-form/Flip-Mem.fir +++ /dev/null @@ -1,12 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; CHECK: Memory mc cannot be a bundle type with flips. - -circuit Flip-Mem : - module Flip-Mem : - input clk : Clock - mem mc : - depth => 10 - data-type => {x : UInt<3>, flip y : UInt<5>} - write-latency => 1 - read-latency => 0 - ;smem ms : {x : UInt<3>, flip y : UInt<5>}[10], clk diff --git a/test/errors/high-form/Flip-Poison.fir b/test/errors/high-form/Flip-Poison.fir deleted file mode 100644 index 278d3b74..00000000 --- a/test/errors/high-form/Flip-Poison.fir +++ /dev/null @@ -1,8 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; CHECK: Poison p cannot be a bundle type with flips. - -circuit Flip-Poison : - module Flip-Poison : - input clk : Clock - poison p : {x : UInt<10>, flip y : UInt<10>} - diff --git a/test/errors/high-form/InstanceNotModule.fir b/test/errors/high-form/InstanceNotModule.fir deleted file mode 100644 index aa49b26b..00000000 --- a/test/errors/high-form/InstanceNotModule.fir +++ /dev/null @@ -1,8 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; CHECK: Module Top2 is not defined. - -circuit Top : - module Top : - wire x : UInt<1> - inst t of Top2 - diff --git a/test/errors/high-form/InvalidLOC.fir b/test/errors/high-form/InvalidLOC.fir deleted file mode 100644 index 8329cc02..00000000 --- a/test/errors/high-form/InvalidLOC.fir +++ /dev/null @@ -1,12 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; CHECK: Invalid connect to an expression that is not a reference or a WritePort. -; CHECK: Invalid connect to an expression that is not a reference or a WritePort. -; CHECK: Invalid connect to an expression that is not a reference or a WritePort. - -circuit Top : - module Top : - wire x : UInt - add(x,x) <= UInt(1) - UInt(1) <= UInt(1) - SInt(1) <= UInt(1) - diff --git a/test/errors/high-form/InvalidSubexp.fir b/test/errors/high-form/InvalidSubexp.fir deleted file mode 100644 index d0ad34c0..00000000 --- a/test/errors/high-form/InvalidSubexp.fir +++ /dev/null @@ -1,9 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; CHECK: Invalid access to non-reference. -; CHECK: Invalid access to non-reference. - -circuit Top : - module Top : - wire x : UInt<4> - add(x,x)[10] <= UInt(1) - add(x,x).x <= UInt(1) diff --git a/test/errors/high-form/NegUInt.fir b/test/errors/high-form/NegUInt.fir deleted file mode 100644 index 8249f791..00000000 --- a/test/errors/high-form/NegUInt.fir +++ /dev/null @@ -1,7 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; CHECK: UIntValue cannot be negative. - -circuit Top : - module Top : - wire x : UInt<4> - x <= UInt(-2) diff --git a/test/errors/high-form/NegVecSize.fir b/test/errors/high-form/NegVecSize.fir deleted file mode 100644 index 8a89d4e6..00000000 --- a/test/errors/high-form/NegVecSize.fir +++ /dev/null @@ -1,7 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; CHECK: Vector type size cannot be negative - -circuit Top : - module Top : - wire x : UInt<3>[-5] - diff --git a/test/errors/high-form/NegWidth.fir b/test/errors/high-form/NegWidth.fir deleted file mode 100644 index 1eb54a34..00000000 --- a/test/errors/high-form/NegWidth.fir +++ /dev/null @@ -1,7 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; CHECK: Width cannot be negative or zero. - -circuit Top : - module Top : - wire x : UInt<-3> - diff --git a/test/errors/high-form/NumArgs.fir b/test/errors/high-form/NumArgs.fir deleted file mode 100644 index 7db78509..00000000 --- a/test/errors/high-form/NumArgs.fir +++ /dev/null @@ -1,9 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; CHECK: Primop add requires 2 expression arguments. -; CHECK: Primop bits requires 2 integer arguments. - -circuit Top : - module Top : - node y = add(SInt(1),UInt(1),UInt(1)) - node z = bits(UInt(1),1,2,3) - diff --git a/test/errors/high-form/Prefix.fir b/test/errors/high-form/Prefix.fir deleted file mode 100644 index ba4a28a2..00000000 --- a/test/errors/high-form/Prefix.fir +++ /dev/null @@ -1,9 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; CHECK: Symbol x$z$y is a prefix. - -circuit Top : - module Top : - wire x : UInt<2> - wire x$z$y : UInt<1> - - diff --git a/test/errors/high-form/Printf.fir b/test/errors/high-form/Printf.fir deleted file mode 100644 index 5580182b..00000000 --- a/test/errors/high-form/Printf.fir +++ /dev/null @@ -1,16 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s - -circuit Top : - module Top : - input x : {y : UInt<1>} - input p : UInt<1> - input clk : Clock - printf(clk,p,"Hello World%!\n",x) - printf(clk,p,"Hello World%") - printf(clk,p,"Hello World%d %s %h %x",x,x,x) - -;CHECK: Bad printf format: "%!" -;CHECK: Bad printf format: trailing "%" -;CHECK: Bad printf format: incorrect number of arguments -;CHECK: Bad printf format: "%h" -;CHECK: Bad printf format: incorrect number of arguments diff --git a/test/errors/high-form/RemoveChar.fir b/test/errors/high-form/RemoveChar.fir deleted file mode 100644 index aa5e8227..00000000 --- a/test/errors/high-form/RemoveChar.fir +++ /dev/null @@ -1,12 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; CHECK: Done! - -circuit Top : - module Top : - wire x_1 : UInt<1> - x_1 <= UInt(1) - wire x : UInt<1> - x <= add(add(UInt(1),UInt(1)),UInt(1)) - - - diff --git a/test/errors/high-form/RemoveScope.fir b/test/errors/high-form/RemoveScope.fir deleted file mode 100644 index 63dfb4de..00000000 --- a/test/errors/high-form/RemoveScope.fir +++ /dev/null @@ -1,18 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; XFAIL: * -; CHECK: Done! - -circuit Top : - module Top : - wire x : UInt<1> - node p = UInt(1) - when p : - wire x : UInt<1> - x <= UInt(1) - node y = add(x,UInt(1)) - else : - wire x : UInt<1> - x <= UInt(1) - node z = add(x,UInt(1)) - x <= UInt(1) - node w = add(x,UInt(1)) diff --git a/test/errors/high-form/SpecialChars.fir b/test/errors/high-form/SpecialChars.fir deleted file mode 100644 index 85911c06..00000000 --- a/test/errors/high-form/SpecialChars.fir +++ /dev/null @@ -1,35 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; CHECK: Done! - -circuit Top : - module Top : - wire x : UInt<1> - x <= UInt(1) - wire x~y : UInt<2> - x~y <= UInt(1) - wire x!y : UInt<2> - x!y <= UInt(1) - wire x@y : UInt<2> - x@y <= UInt(1) - wire x#y : UInt<2> - x#y <= UInt(1) - wire x%y : UInt<2> - x%y <= UInt(1) - wire x^y : UInt<2> - x^y <= UInt(1) - wire x*y : UInt<2> - x*y <= UInt(1) - wire x-y : UInt<2> - x-y <= UInt(1) - wire x_y : UInt<2> - x_y <= UInt(1) - wire x+y : UInt<2> - x+y <= UInt(1) - wire x=y : UInt<2> - x=y <= UInt(1) - wire x?y : UInt<2> - x?y <= UInt(1) - wire x/y : UInt<2> - x/y <= UInt(1) - - diff --git a/test/errors/high-form/Top.fir b/test/errors/high-form/Top.fir deleted file mode 100644 index ddeb9c3b..00000000 --- a/test/errors/high-form/Top.fir +++ /dev/null @@ -1,9 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s - -; CHECK: A single module must be named Top. - -circuit Top : - module Top1 : - wire x : UInt<1> - module Top2 : - wire x : UInt<1> diff --git a/test/errors/high-form/Unique.fir b/test/errors/high-form/Unique.fir deleted file mode 100644 index 60201b92..00000000 --- a/test/errors/high-form/Unique.fir +++ /dev/null @@ -1,16 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s - -; CHECK: Reference x does not have a unique name. -; CHECK: Reference p does not have a unique name. -; CHECK-NOT: Reference q does not have a unique name. - -circuit Top : - module Top : - wire x : UInt<1> - wire x : UInt<2> - wire p : UInt<3> - wire q : UInt<3> - when p : - wire p : UInt<4> - module Other : - wire q : UInt<3> diff --git a/test/errors/init/Output.fir b/test/errors/init/Output.fir deleted file mode 100644 index 0b7a7f80..00000000 --- a/test/errors/init/Output.fir +++ /dev/null @@ -1,10 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; CHECK: Reference y is not fully initialized. - -circuit Top : - module Top : - input clk : Clock - wire y : UInt<1> - - when UInt(0) : - y <= UInt(1) diff --git a/test/errors/parser/InstanceNotRef.fir b/test/errors/parser/InstanceNotRef.fir deleted file mode 100644 index 0760f168..00000000 --- a/test/errors/parser/InstanceNotRef.fir +++ /dev/null @@ -1,8 +0,0 @@ -; RUN: firrtl -i %s -o %s.flo -x X -p c | tee %s.out | FileCheck %s -; CHECK: FIRRTL Parsing Error: Expected a statement here. - -circuit Top : - module Top : - wire x : UInt<1> - inst t of add(UInt(1),UInt(1)) - diff --git a/test/errors/parser/Nested-Module.fir b/test/errors/parser/Nested-Module.fir deleted file mode 100644 index 3f06db76..00000000 --- a/test/errors/parser/Nested-Module.fir +++ /dev/null @@ -1,6 +0,0 @@ -; RUN: firrtl -i %s -o %s.flo -x X -p c | tee %s.out | FileCheck %s -; CHECK: FIRRTL Parsing Error: Expected a statement here. - -circuit Nested-Module : - module Top : - module Child : diff --git a/test/errors/parser/Statements-in-Circuit.fir b/test/errors/parser/Statements-in-Circuit.fir deleted file mode 100644 index 5f675e82..00000000 --- a/test/errors/parser/Statements-in-Circuit.fir +++ /dev/null @@ -1,5 +0,0 @@ -; RUN: firrtl -i %s -o %s.flo -x X -p c | tee %s.out | FileCheck %s -; CHECK: FIRRTL Parsing Error: Expected a module declaration here. - -circuit Statement-in-Circuit : - node x : UInt(1) diff --git a/test/errors/type/AccessIndexUInt.fir b/test/errors/type/AccessIndexUInt.fir deleted file mode 100644 index d47bb7c6..00000000 --- a/test/errors/type/AccessIndexUInt.fir +++ /dev/null @@ -1,8 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: AccessIndexUInt.fir@8.4: [module Top] Access index must be a UInt type. -circuit Top : - module Top : - input b : UInt<32>[62] - input a : SInt<8> - output c : UInt<32> - c <= b[a] diff --git a/test/errors/type/BulkConnect.fir b/test/errors/type/BulkConnect.fir deleted file mode 100644 index 26f5c156..00000000 --- a/test/errors/type/BulkConnect.fir +++ /dev/null @@ -1,32 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: BulkConnect.fir@10.4: [module Top] Type mismatch. -;CHECK: BulkConnect.fir@14.4: [module Top] Type mismatch. -;CHECK: BulkConnect.fir@26.4: [module Top] Type mismatch. -;CHECK: BulkConnect.fir@30.4: [module Top] Type mismatch. -circuit Top : - module Top : - wire a : { w : UInt<42>} - wire b : { w : SInt<42>} - a <- b - - wire c : { w : UInt<10>} - wire d : { flip w : UInt<12> } - c <- d - - wire e : { w : UInt<10>} - wire f : { x : UInt<12> } - e <- f - - wire g : { w : { y : UInt<10> }} - wire h : { w : { x : UInt<12> }} - g <- h - - wire i : { w : { flip y : UInt<10> }} - wire j : { w : { y : UInt<12> }} - i <- j - - wire k : { w : { y : SInt<10> }} - wire l : { w : { y : UInt<12> }} - k <- l - - diff --git a/test/errors/type/MuxWithFlips.fir b/test/errors/type/MuxWithFlips.fir deleted file mode 100644 index 9a8b2170..00000000 --- a/test/errors/type/MuxWithFlips.fir +++ /dev/null @@ -1,12 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; CHECK: [module Top] Must mux between passive types. -; CHECK: [module Top] A mux condition must be of type UInt. - -circuit Top : - module Top : - input c : SInt<1> - input x : {x : UInt, flip y : UInt} - input y : {x : UInt, flip y : UInt} - output z : {x : UInt, flip y : UInt} - z <= mux(c,x,y) - diff --git a/test/errors/type/NodeWithFlips.fir b/test/errors/type/NodeWithFlips.fir deleted file mode 100644 index 2030955f..00000000 --- a/test/errors/type/NodeWithFlips.fir +++ /dev/null @@ -1,8 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; CHECK: Node must be a passive type. - -circuit Top : - module Top : - wire x : {x : UInt, flip y : UInt} - node z = x - diff --git a/test/errors/type/Primop.fir b/test/errors/type/Primop.fir deleted file mode 100644 index dcf19935..00000000 --- a/test/errors/type/Primop.fir +++ /dev/null @@ -1,13 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; CHECK: Must mux between equivalent types. -; CHECK: Primop add cannot operate on non-ground types. -; CHECK: A mux condition must be of type UInt. - -circuit Top : - module Top : - node x = mux(UInt(1),SInt(1),UInt(1)) - wire a : { q : UInt<1> } - node y = add(a,a) - node z = bits(SInt<10>(-1),1,2) - node zz = mux(SInt(1),UInt(1),UInt(1)) - diff --git a/test/errors/width/Conservative.fir b/test/errors/width/Conservative.fir deleted file mode 100644 index 43aa648f..00000000 --- a/test/errors/width/Conservative.fir +++ /dev/null @@ -1,6 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p ciwT 2>&1 | tee %s.out | FileCheck %s -; CHECK: Width too small for UIntValue. - -circuit Top : - module Top : - node bar = UInt<1>("h1111") diff --git a/test/errors/width/NegWidth.fir b/test/errors/width/NegWidth.fir deleted file mode 100644 index e02884a8..00000000 --- a/test/errors/width/NegWidth.fir +++ /dev/null @@ -1,9 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p ciwT 2>&1 | tee %s.out | FileCheck %s -; CHECK: Width cannot be negative or zero. - -circuit Top : - module Top : - output y : UInt - - wire x : UInt<2> - y <= shr(x,4) diff --git a/test/errors/width/SmallWidth.fir b/test/errors/width/SmallWidth.fir deleted file mode 100644 index 0885ba52..00000000 --- a/test/errors/width/SmallWidth.fir +++ /dev/null @@ -1,12 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p ciwT 2>&1 | tee %s.out | FileCheck %s -; CHECK: Width too small for UIntValue. - -circuit Top : - module Top : - output z : UInt - - z <= add(UInt<4>("h121"),UInt<3>("h13333")) - - - - diff --git a/test/errors/width/UninferredWidth.fir b/test/errors/width/UninferredWidth.fir deleted file mode 100644 index d4cff841..00000000 --- a/test/errors/width/UninferredWidth.fir +++ /dev/null @@ -1,12 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p ciwTd 2>&1 | tee %s.out | FileCheck %s -; CHECK: Uninferred width. - -circuit Top : - module Top : - input z : UInt - - - - - - diff --git a/test/features/BigInt.fir b/test/features/BigInt.fir deleted file mode 100644 index 9060d705..00000000 --- a/test/features/BigInt.fir +++ /dev/null @@ -1,10 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p cT 2>&1 | tee %s.out | FileCheck %s -circuit Top : - module Top : - node x = UInt("h2") - node y = UInt("h100000") - node z = UInt("h00") - -;CHECK: node x = UInt<2>("h2") -;CHECK: node z = UInt<1>("h0") -;CHECK: Done! diff --git a/test/features/BulkConnect.fir b/test/features/BulkConnect.fir deleted file mode 100644 index 1b68bbdc..00000000 --- a/test/features/BulkConnect.fir +++ /dev/null @@ -1,39 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: Expand Connects -circuit Top : - module Top : - wire a : { w : UInt} - a.w <= UInt(1) - wire b : { w : UInt<42>, x : UInt<20>} - b.w <= UInt(1) - b.x <= UInt(1) - a <- b - ; CHECK: a.w <= b.w - ; CHECK-NOT: a.x <= b.x - ; CHECK-NOT: a.y <= b.y - ; CHECK-NOT: b.y <= a.y - ; CHECK-NOT: a.z <= b.z - - - wire c : { x : { y : UInt<1>, z : UInt<1>}}[4] - c[0].x.z <= UInt(1) - c[1].x.z <= UInt(1) - c[2].x.y <= UInt(1) - c[2].x.z <= UInt(1) - c[3].x.y <= UInt(1) - c[3].x.z <= UInt(1) - wire d : { x : { y : UInt<1>}}[2] - d[0].x.y <= UInt(1) - d[1].x.y <= UInt(1) - c <- d - ; CHECK: c[0].x.y <= d[0].x.y - ; CHECK: c[1].x.y <= d[1].x.y - ; CHECK-NOT: c[2].x.y <= d[2].x.y - ; CHECK-NOT: c[3].x.y <= d[3].x.y - ; CHECK-NOT: c[0].x.z <= d[0].x.z - ; CHECK-NOT: c[1].x.z <= d[1].x.z - ; CHECK-NOT: c[2].x.z <= d[2].x.z - ; CHECK-NOT: c[3].x.z <= d[3].x.z - -;CHECK: Finished Expand Connects -;CHECK: Done! diff --git a/test/features/DeadCodeElimination.fir b/test/features/DeadCodeElimination.fir deleted file mode 100644 index e67deebf..00000000 --- a/test/features/DeadCodeElimination.fir +++ /dev/null @@ -1,10 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; XFAIL: * - -circuit top : - module top : - input clk : Clock - input reset : UInt<1> - wire x : UInt<1> - -; CHECK: Done! diff --git a/test/features/EmptyStmt.fir b/test/features/EmptyStmt.fir deleted file mode 100644 index 5fb265c0..00000000 --- a/test/features/EmptyStmt.fir +++ /dev/null @@ -1,11 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: Done! -circuit Top : - module Top : - skip - when UInt(1) : - skip - else : - skip - skip - diff --git a/test/features/ExModule.fir b/test/features/ExModule.fir deleted file mode 100644 index b31c77c9..00000000 --- a/test/features/ExModule.fir +++ /dev/null @@ -1,14 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -circuit Top : - module Top : - output z : UInt<4> - inst i of BlackBox - i.x <= UInt(1) - i.y <= UInt(2) - z <= i.z - extmodule BlackBox : - input x : UInt<4> - input y : UInt<4> - output z : UInt<4> - -;CHECK: Done! diff --git a/test/features/InitAccessor.fir b/test/features/InitAccessor.fir deleted file mode 100644 index 6261ec01..00000000 --- a/test/features/InitAccessor.fir +++ /dev/null @@ -1,13 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p cT 2>&1 | tee %s.out | FileCheck %s - -;CHECK: Done! -circuit Top : - module Top : - input in : UInt<1> - wire b : UInt<1>[3] - b[0] <= UInt(1) - b[1] <= UInt(1) - b[2] <= UInt(1) - node c = UInt(1) - when in : - b[c] <= UInt(1) diff --git a/test/features/InitializeVec.fir b/test/features/InitializeVec.fir deleted file mode 100644 index 1cc44daf..00000000 --- a/test/features/InitializeVec.fir +++ /dev/null @@ -1,21 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s - -;CHECK: Done! -circuit Tst : - module Tst : - input in : {valid : UInt<1>, flip ready : UInt<1>, bits : UInt<8>} - output outs : {valid : UInt<1>, flip ready : UInt<1>, bits : UInt<8>}[4] - - in.ready <= UInt<1>(1) - outs[0].valid <= UInt<1>(0) - outs[0].bits <= UInt<1>(0) - outs[1].valid <= UInt<1>(0) - outs[1].bits <= UInt<1>(0) - outs[2].valid <= UInt<1>(0) - outs[2].bits <= UInt<1>(0) - outs[3].valid <= UInt<1>(0) - outs[3].bits <= UInt<1>(0) - in.ready <= UInt<1>(1) - when outs[in.bits].ready : - outs[in.bits].bits <= UInt<7>(99) - outs[in.bits].valid <= UInt<1>(1) diff --git a/test/features/IsInvalid.fir b/test/features/IsInvalid.fir deleted file mode 100644 index dc7c56b4..00000000 --- a/test/features/IsInvalid.fir +++ /dev/null @@ -1,74 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -circuit Top : - module Top : - input clk : Clock - input reset : UInt<1> - input a : { w : UInt<42>, flip x : UInt<30>}[2] - output b : { w : UInt<42>, flip x : UInt<30>}[2] - mem m : - depth => 10 - data-type => UInt<32>[4] - read-latency => 0 - write-latency => 1 - reader => r - writer => w - readwriter => rw - wire x : { w : UInt<42>, x : UInt<20>} - reg c : { w : UInt<42>, x : UInt<20>},clk with : - reset => (reset,x) - inst other of Other - - clk is invalid - reset is invalid - a is invalid - b is invalid - m is invalid - x is invalid - c is invalid - other is invalid - module Other : - input a : { w : UInt<42>, flip x : UInt<30>} - output b : { w : UInt<42>, flip x : UInt<30>} - b <= a - - -;CHECK: Expand Connects -;CHECK: skip -;CHECK: skip -;CHECK: a[0].x is invalid -;CHECK: a[1].x is invalid -;CHECK: b[0].w is invalid -;CHECK: b[1].w is invalid -;CHECK: m.r.addr is invalid -;CHECK: m.r.en is invalid -;CHECK: m.r.clk is invalid -;CHECK: m.w.data[0] is invalid -;CHECK: m.w.data[1] is invalid -;CHECK: m.w.data[2] is invalid -;CHECK: m.w.data[3] is invalid -;CHECK: m.w.mask[0] is invalid -;CHECK: m.w.mask[1] is invalid -;CHECK: m.w.mask[2] is invalid -;CHECK: m.w.mask[3] is invalid -;CHECK: m.w.addr is invalid -;CHECK: m.w.en is invalid -;CHECK: m.w.clk is invalid -;CHECK: m.rw.wmode is invalid -;CHECK: m.rw.data[0] is invalid -;CHECK: m.rw.data[1] is invalid -;CHECK: m.rw.data[2] is invalid -;CHECK: m.rw.data[3] is invalid -;CHECK: m.rw.mask[0] is invalid -;CHECK: m.rw.mask[1] is invalid -;CHECK: m.rw.mask[2] is invalid -;CHECK: m.rw.mask[3] is invalid -;CHECK: m.rw.addr is invalid -;CHECK: m.rw.en is invalid -;CHECK: m.rw.clk is invalid -;CHECK: x.w is invalid -;CHECK: x.x is invalid -;CHECK: c.w is invalid -;CHECK: c.x is invalid -;CHECK: other.a.w is invalid -;CHECK: other.b.x is invalid -;CHECK: Done! diff --git a/test/features/Link.fir b/test/features/Link.fir deleted file mode 100644 index 57fb8605..00000000 --- a/test/features/Link.fir +++ /dev/null @@ -1,14 +0,0 @@ -; RUN: firrtl -i %s -m %S/Queue.fir -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: Done! -circuit Top : - module Top : - input clk : Clock - input reset : UInt<1> - output out : UInt<10> - - inst q of Queue - q.clk <= clk - q.reset <= reset - q.in <= UInt(1) - out <= q.out - diff --git a/test/features/Long.fir b/test/features/Long.fir deleted file mode 100644 index 7ac5ad6c..00000000 --- a/test/features/Long.fir +++ /dev/null @@ -1,6 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: Done -circuit Top : - module Top : - wire a : UInt - a <= UInt("h4261441663") diff --git a/test/features/MemSize1.fir b/test/features/MemSize1.fir deleted file mode 100644 index a29d3fc5..00000000 --- a/test/features/MemSize1.fir +++ /dev/null @@ -1,11 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: Done! -circuit Top : - module Top : - input clk : Clock - output out : UInt<32> - input i : UInt<1> - cmem m : UInt<32>[1] - read mport r = m[i],clk - out <= r - diff --git a/test/features/MuxBundle.fir b/test/features/MuxBundle.fir deleted file mode 100644 index 764078d5..00000000 --- a/test/features/MuxBundle.fir +++ /dev/null @@ -1,16 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: Expand Connects -circuit Top : - module Top : - input a: {w:UInt<42>,x:UInt<20>} - input b: {w:UInt<42>,x:UInt<20>} - input c: {w:UInt<42>,x:UInt<20>} - input p : UInt<1> - output d: {w:UInt<42>,x:UInt<20>} - d <= mux(p,mux(p,a,b),c) -;CHECK: d.w <= mux(p, mux(p, a.w, b.w), c.w) -;CHECK: d.x <= mux(p, mux(p, a.x, b.x), c.x) - -;CHECK: Finished Expand Connects -;CHECK: Done! - diff --git a/test/features/MuxNodeExamples.fir b/test/features/MuxNodeExamples.fir deleted file mode 100644 index 07fa16b4..00000000 --- a/test/features/MuxNodeExamples.fir +++ /dev/null @@ -1,28 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: Expand Connects -circuit Top : - module Top : - input a : {f:UInt<3>[3], flip g:UInt<3>[3]}[2] - input b : {f:UInt<3>[3], flip g:UInt<3>[3]}[2] - input p : UInt<1> - input i : UInt<1> - b[0].g[0] <= UInt(0) - b[0].g[1] <= UInt(0) - b[0].g[2] <= UInt(0) - b[1].g[0] <= UInt(0) - b[1].g[1] <= UInt(0) - b[1].g[2] <= UInt(0) - a[0].g[0] <= UInt(0) - a[0].g[1] <= UInt(0) - a[0].g[2] <= UInt(0) - a[1].g[0] <= UInt(0) - a[1].g[1] <= UInt(0) - a[1].g[2] <= UInt(0) - node x = mux(p,a[i].f,b[i].f) - - - -;CHECK: Finished Expand Connects -;CHECK: Done! - - diff --git a/test/features/MuxType.fir b/test/features/MuxType.fir deleted file mode 100644 index b0e7e7ef..00000000 --- a/test/features/MuxType.fir +++ /dev/null @@ -1,12 +0,0 @@ - -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: Expand Connects -circuit Top : - module Top : - input a: UInt<1> - input b: UInt<32> - input p : UInt<1> - output d: UInt - node y = mux(p, a, b) - d <= y -;CHECK:Done! diff --git a/test/features/NestedAccess.fir b/test/features/NestedAccess.fir deleted file mode 100644 index bd3c436d..00000000 --- a/test/features/NestedAccess.fir +++ /dev/null @@ -1,31 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p cw 2>&1 | tee %s.out | FileCheck %s -;CHECK: Expand Connects -circuit Top : - module Top : - input i : UInt<1> - input j : UInt<1> - wire a : { x : UInt<42> flip y : UInt<42>[2]}[2][3] - wire b : { x : UInt<42> flip y : UInt<42>[2]} - a[0][0].x <= UInt(0) - a[0][0].y[0] <= UInt(0) - a[0][0].y[1] <= UInt(0) - a[0][1].x <= UInt(0) - a[0][1].y[0] <= UInt(0) - a[0][1].y[1] <= UInt(0) - a[1][0].x <= UInt(0) - a[1][0].y[0] <= UInt(0) - a[1][0].y[1] <= UInt(0) - a[1][1].x <= UInt(0) - a[1][1].y[0] <= UInt(0) - a[1][1].y[1] <= UInt(0) - a[2][0].x <= UInt(0) - a[2][0].y[0] <= UInt(0) - a[2][0].y[1] <= UInt(0) - a[2][1].x <= UInt(0) - a[2][1].y[0] <= UInt(0) - a[2][1].y[1] <= UInt(0) - b.x <= UInt(0) - a[i][j] <= b -;CHECK: Finished Expand Connects -;CHECK: Done! - diff --git a/test/features/NestedSubAccessTester.fir b/test/features/NestedSubAccessTester.fir deleted file mode 100644 index 36465012..00000000 --- a/test/features/NestedSubAccessTester.fir +++ /dev/null @@ -1,27 +0,0 @@ -circuit NestedSubAccessTester : - module NestedSubAccess : - input foo : UInt<1>[4] - input index : UInt<2> - output out : UInt<4> - - wire vec : UInt<4>[2] - vec[0] <= UInt(3) - vec[1] <= UInt(4) - - out <= vec[foo[index]] - - module NestedSubAccessTester : - input clk : Clock - input reset : UInt<1> - - inst dut of NestedSubAccess - - dut.foo is invalid - dut.index <= UInt(2) - dut.foo[2] <= UInt(1) - - when neq(dut.out, UInt(4)) : - printf(clk, not(reset), "Assertion failed\nTest Failed!\n") - stop(clk, not(reset), 1) - else : - stop(clk, not(reset), 0) diff --git a/test/features/NodeBundle.fir b/test/features/NodeBundle.fir deleted file mode 100644 index c4c33107..00000000 --- a/test/features/NodeBundle.fir +++ /dev/null @@ -1,12 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: Lower Types -circuit Top : - module Top : - input a: {w:UInt<42>,x:UInt<20>} - node d = a -;CHECK: node d_w = a_w -;CHECK: node d_x = a_x - -;CHECK: Finished Lower Types -;CHECK: Done! - diff --git a/test/features/OptionalRegisterReset.fir b/test/features/OptionalRegisterReset.fir deleted file mode 100644 index 54a90b67..00000000 --- a/test/features/OptionalRegisterReset.fir +++ /dev/null @@ -1,17 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -circuit Top : - module Top : - input clk : Clock - input reset : UInt<1> - input a : UInt<32> - input p : UInt<1> - output b : UInt<32> - reg r1:UInt<32> clk with : - reset => (reset, a) - when p : - b <= r1 - else : - b <= r1 - - -;CHECK: Done! diff --git a/test/features/Poison.fir b/test/features/Poison.fir deleted file mode 100644 index 9aafe63f..00000000 --- a/test/features/Poison.fir +++ /dev/null @@ -1,39 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; CHECK: Done! -circuit Poison : - module Poison : - input clk : Clock - input reset : UInt<1> - input index : UInt<7> - input wmask : {x:UInt<1>, y:UInt<1>} - input p : UInt<1> - output out : {x : UInt<10>, y : UInt<10>} - poison q : {x : UInt<10>, y : UInt<10>} - mem m : - data-type => {x : UInt<10>, y : UInt<10>} - depth => 128 - read-latency => 1 - write-latency => 2 - reader => r - writer => w - readwriter => rw - m.r.addr <= index - m.r.en <= UInt(1) - m.r.clk <= clk - m.w.addr <= index - m.w.en <= UInt(1) - m.w.mask <= wmask - m.w.clk <= clk - m.w.data <= q - - m.rw.clk <= clk - m.rw.addr <= index - m.rw.en <= UInt(1) - m.rw.wmode <= UInt(1) - m.rw.mask <= wmask - m.rw.data <= q - when p : - out <= m.r.data - else : - out <= q - diff --git a/test/features/Printf.fir b/test/features/Printf.fir deleted file mode 100644 index 912023af..00000000 --- a/test/features/Printf.fir +++ /dev/null @@ -1,21 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s - -;CHECK: Expand Whens -circuit Top : - module Top : - input x : {y : UInt<1>} - input p : UInt<1> - input clk : Clock - input en : UInt<1> - printf(clk,en,"Hello World!\n") - printf(clk,en,"Hello World! %x\n", x.y) - when p : - printf(clk,en,"In consequence\n") - else : - printf(clk,en,"In alternate\n") - -;CHECK: printf(clk, en, "Hello World!\n") -;CHECK: printf(clk, en, "Hello World! %x\n", x.y) -;CHECK: printf(clk, and(p, en), "In consequence\n") -;CHECK: printf(clk, and(eq(p, UInt<1>("h0")), en), "In alternate\n") -;CHECK: Done! diff --git a/test/features/Queue.fir b/test/features/Queue.fir deleted file mode 100644 index 3ce58e31..00000000 --- a/test/features/Queue.fir +++ /dev/null @@ -1,13 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; CHECK: Done! -circuit Queue : - module Queue : - input in : UInt<10> - output out : UInt<10> - input clk : Clock - input reset : UInt<1> - - reg r : UInt<10>,clk with : - reset => (reset,in) - r <= in - out <= r diff --git a/test/features/SeqMem.fir b/test/features/SeqMem.fir deleted file mode 100644 index d97435af..00000000 --- a/test/features/SeqMem.fir +++ /dev/null @@ -1,46 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: Done! -circuit Top : - module Top : - input clk : Clock - wire i : UInt<5> - i <= UInt(1) - wire i0 : UInt<5> - wire j : UInt<128> - - i0 <= UInt(10) - - mem m-com : - data-type => UInt<128> - depth => 32 - reader => r - writer => w - read-latency => 0 - write-latency => 1 - m-com.r.addr <= i - m-com.r.en <= UInt(1) - m-com.r.clk <= clk - m-com.w.addr <= i - m-com.w.mask <= UInt(1) - m-com.w.en <= UInt(1) - m-com.w.clk <= clk - j <= m-com.r.data - m-com.w.data <= j - - - mem m-seq : - data-type => UInt<128> - depth => 32 - reader => r - writer => w - read-latency => 1 - write-latency => 1 - m-seq.r.addr <= i - m-seq.r.en <= UInt(1) - m-seq.r.clk <= clk - m-seq.w.addr <= i - m-seq.w.mask <= UInt(1) - m-seq.w.en <= UInt(1) - m-seq.w.clk <= clk - j <= m-seq.r.data - m-seq.w.data <= j diff --git a/test/features/Stop.fir b/test/features/Stop.fir deleted file mode 100644 index 888da3d7..00000000 --- a/test/features/Stop.fir +++ /dev/null @@ -1,20 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s - -;CHECK: Expand Whens - -circuit Top : - module Top : - input p : UInt<1> - input q : UInt<1> - input clk : Clock - when p : - stop(clk,UInt(1),0) - when q : - stop(clk,UInt(1),1) - stop(clk,UInt(1),3) - -;CHECK: stop(clk, p, 0) -;CHECK: stop(clk, q, 1) -;CHECK: stop(clk, UInt<1>("h1"), 3) -;CHECK: Done! - diff --git a/test/features/TwoClocks.fir b/test/features/TwoClocks.fir deleted file mode 100644 index 3753ee8d..00000000 --- a/test/features/TwoClocks.fir +++ /dev/null @@ -1,24 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -circuit Top : - module Top : - input clk1 : Clock - input clk2 : Clock - input reset1 : UInt<1> - input reset2 : UInt<1> - reg src : UInt<10>, clk1 with : - reset => ( reset1, UInt(0)) - reg sink : UInt<10>, clk2 with : - reset => ( reset2, UInt(0)) - - src <= add(src,UInt(1)) - - reg sync_A : UInt<10>, clk2 with : - reset => ( reset2, UInt(0)) - sync_A <= src - reg sync_B : UInt<10>, clk2 with : - reset => ( reset2, UInt(0)) - sync_B <= sync_A - - sink <= sync_B - -;CHECK: Done! diff --git a/test/features/ValidIf.fir b/test/features/ValidIf.fir deleted file mode 100644 index 70c69313..00000000 --- a/test/features/ValidIf.fir +++ /dev/null @@ -1,21 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -circuit Top : - module Top : - input clk : Clock - input reset : UInt<1> - input a : { w : UInt<42>, x : UInt<30>}[2] - input b : { w : UInt<42>, x : UInt<30>}[2] - input p: UInt<1> - input q: UInt<1> - output c : { w : UInt<42>, x : UInt<30>}[2] - output d : { w : UInt<42>, x : UInt<30>}[2] - - c is invalid - when p : - when q : - c <= a - else : - c <= b - d <= validif(p,b) - -;CHECK: Done! diff --git a/test/features/VerilogReg.fir b/test/features/VerilogReg.fir deleted file mode 100644 index 96022933..00000000 --- a/test/features/VerilogReg.fir +++ /dev/null @@ -1,18 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; CHECK: Done! -circuit Poison : - module Poison : - input clk : Clock - input reset : UInt<1> - input p1 : UInt<1> - input p2 : UInt<1> - input p3 : UInt<1> - reg r : UInt<32>,clk with : - reset => (reset,r) - when p1 : - r <= UInt(1) - when p2 : - r <= UInt(2) - when p3 : - r <= UInt(3) - diff --git a/test/features/VerilogRename.fir b/test/features/VerilogRename.fir deleted file mode 100644 index f8fceaa9..00000000 --- a/test/features/VerilogRename.fir +++ /dev/null @@ -1,18 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -circuit Top : - module Top : - input with : Clock - output unsigned : Clock - wire trireg : Clock - unsigned <= with - trireg <= with - -;CHECK: Verilog Rename - -;CHECK: input with$ : Clock -;CHECK: output unsigned$ : Clock -;CHECK: wire trireg$ : Clock -;CHECK: trireg$ <= with$ -;CHECK: unsigned$ <= with$ - -;CHECK: Done! diff --git a/test/lit.cfg b/test/lit.cfg deleted file mode 100644 index 71928a43..00000000 --- a/test/lit.cfg +++ /dev/null @@ -1,4 +0,0 @@ -import lit.formats - -config.test_format = lit.formats.ShTest() -config.suffixes = ['.fir'] diff --git a/test/parser/bundle.fir b/test/parser/bundle.fir deleted file mode 100644 index 16a72a1b..00000000 --- a/test/parser/bundle.fir +++ /dev/null @@ -1,44 +0,0 @@ -; RUN: firrtl -i %s -o %s.out -X firrtl && cat %s.out | FileCheck %s - -circuit top : - module top : - wire z : { x : UInt, flip y: SInt} - z.x <= UInt(1) - z.y <= SInt(1) - node x = z.x - node y = z.y - wire a : UInt<3>[10] - a[0] <= UInt(1) - a[1] <= UInt(1) - a[2] <= UInt(1) - a[3] <= UInt(1) - a[4] <= UInt(1) - a[5] <= UInt(1) - a[6] <= UInt(1) - a[7] <= UInt(1) - a[8] <= UInt(1) - a[9] <= UInt(1) - node b = a[2] - node c = a[UInt(3)] - -; CHECK: circuit top : -; CHECK: module top : -; CHECK: wire z : { x : UInt, flip y : SInt} -; CHECK: z.x <= UInt<1>("h1") -; CHECK: z.y <= SInt<2>("h1") -; CHECK: node x = z.x -; CHECK: node y = z.y -; CHECK: wire a : UInt<3>[10] -; CHECK: a[0] <= UInt<1>("h1") -; CHECK: a[1] <= UInt<1>("h1") -; CHECK: a[2] <= UInt<1>("h1") -; CHECK: a[3] <= UInt<1>("h1") -; CHECK: a[4] <= UInt<1>("h1") -; CHECK: a[5] <= UInt<1>("h1") -; CHECK: a[6] <= UInt<1>("h1") -; CHECK: a[7] <= UInt<1>("h1") -; CHECK: a[8] <= UInt<1>("h1") -; CHECK: a[9] <= UInt<1>("h1") -; CHECK: node b = a[2] -; CHECK: node c = a[UInt<2>("h3")] - diff --git a/test/parser/dshl.fir b/test/parser/dshl.fir deleted file mode 100644 index 99a6ec7d..00000000 --- a/test/parser/dshl.fir +++ /dev/null @@ -1,14 +0,0 @@ -; RUN: firrtl -i %s -o %s.out -X firrtl && cat %s.out | FileCheck %s -circuit GCD : - module GCD : - input a : UInt<63> - input b : UInt<63> - input sign : UInt<1> - output d : UInt - ;wire T_205 : UInt - node T_203 = UInt<6>("h3f") - node normCount = not(T_203) - node absIn = mux(sign, a, b) - node T_205 = dshl(absIn, normCount) - d <= T_205 - diff --git a/test/parser/gcd.fir b/test/parser/gcd.fir deleted file mode 100644 index 45a048f2..00000000 --- a/test/parser/gcd.fir +++ /dev/null @@ -1,54 +0,0 @@ -; RUN: firrtl -i %s -o %s.out -X firrtl && cat %s.out | FileCheck %s -circuit GCD : - module GCD : - input e : UInt<1> - input clk : Clock - input reset : UInt<1> - output z : UInt - output v : UInt<1> - input a : UInt<16> - input b : UInt<16> - - reg x : UInt<16>,clk - reg y : UInt<16>,clk - node T_17 = gt(x, y) - when T_17 : - node T_18 = tail(sub(x, y), 1) - x <= T_18 - else : - node T_19 = tail(sub(y, x), 1) - y <= T_19 - when e : - x <= a - y <= b - z <= x - node T_20 = eq(y, UInt<1>(0)) - v <= T_20 - -; CHECK: circuit GCD : -; CHECK: module GCD : -; CHECK: input e : UInt<1> -; CHECK: input clk : Clock -; CHECK: input reset : UInt<1> -; CHECK: output z : UInt<16> -; CHECK: output v : UInt<1> -; CHECK: input a : UInt<16> -; CHECK: input b : UInt<16> -; CHECK: reg x : UInt<16>, clk with : -; CHECK: reset => (UInt<1>("h0"), x) -; CHECK: reg y : UInt<16>, clk with : -; CHECK: reset => (UInt<1>("h0"), y) -; CHECK: node T_17 = gt(x, y) -; CHECK: when T_17 : -; CHECK: node T_18 = tail(sub(x, y), 1) -; CHECK: x <= T_18 -; CHECK: else : -; CHECK: node T_19 = tail(sub(y, x), 1) -; CHECK: y <= T_19 -; CHECK: when e : -; CHECK: x <= a -; CHECK: y <= b -; CHECK: z <= x -; CHECK: node T_20 = eq(y, UInt<1>("h0")) -; CHECK: v <= T_20 - diff --git a/test/parser/ints.fir b/test/parser/ints.fir deleted file mode 100644 index 0c79276b..00000000 --- a/test/parser/ints.fir +++ /dev/null @@ -1,20 +0,0 @@ -; RUN: firrtl -i %s -o %s.out -X firrtl 2>&1 | tee %s.out | FileCheck %s -: XFAIL: * - -circuit top : - module top : - output a : UInt - output b : SInt - output c : SInt - a <= UInt(8) - b <= SInt(8) - c <= SInt(-8) - -; CHECK: circuit top : -; CHECK: module top : -; CHECK: output a : UInt -; CHECK: output b : SInt -; CHECK: output c : SInt -; CHECK: a <= UInt<4>("h8") -; CHECK: b <= SInt<5>("h08") -; CHECK: c <= SInt<4>("h8") diff --git a/test/parser/invalids.fir b/test/parser/invalids.fir deleted file mode 100644 index 65051832..00000000 --- a/test/parser/invalids.fir +++ /dev/null @@ -1,13 +0,0 @@ -; RUN: firrtl -i %s -o %s.out -X firrtl && cat %s.out | FileCheck %s -; CHECK: Done! -circuit GCD : - module GCD : - input x : UInt<128> - input p : UInt<1> - input q : UInt<1> - input clk : Clock - wire w : UInt[3] - w is invalid - w[0] <= UInt(0) - w[1] <= UInt(0) - w[2] <= UInt(0) diff --git a/test/parser/mux.fir b/test/parser/mux.fir deleted file mode 100644 index 4705aa75..00000000 --- a/test/parser/mux.fir +++ /dev/null @@ -1,14 +0,0 @@ -; RUN: firrtl -i %s -o %s.out -X firrtl && cat %s.out | FileCheck %s -circuit GCD : - module GCD : - input e : UInt<1> - input f : UInt<1> - input g : UInt<1> - output o : UInt<1> - node y = f - node z = f - node x = mux(UInt<1>(0),y,z) - o <= x - - - diff --git a/test/parser/node.fir b/test/parser/node.fir deleted file mode 100644 index 193aed88..00000000 --- a/test/parser/node.fir +++ /dev/null @@ -1,16 +0,0 @@ -; RUN: firrtl -i %s -o %s.out -X firrtl && cat %s.out | FileCheck %s -; CHECK: Done! -circuit GCD : - module GCD : - input x : UInt<128> - input p : UInt<1> - input q : UInt<1> - input clk : Clock - reg addr : UInt, clk with : - reset => (UInt<1>("h0"), addr) - when p : - node T_1234 = bits(x, 63, 24) - addr <= T_1234 - when q : - node T_1380 = tail(x, 1) - addr <= T_1380 diff --git a/test/passes/const-prop/bits.fir b/test/passes/const-prop/bits.fir deleted file mode 100644 index 74aa19de..00000000 --- a/test/passes/const-prop/bits.fir +++ /dev/null @@ -1,11 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p cT 2>&1 | tee %s.out | FileCheck %s - -;CHECK: Constant Propagation -;CHECK: node x = UInt<3>("h7") -;CHECK: Finished Constant Propagation - -circuit top : - module top : - output out : UInt - node x = bits(UInt(127),2,0) - out <= x diff --git a/test/passes/const-prop/rsh.fir b/test/passes/const-prop/rsh.fir deleted file mode 100644 index 5ed8b1be..00000000 --- a/test/passes/const-prop/rsh.fir +++ /dev/null @@ -1,14 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s - -;CHECK: Constant Propagation -;CHECK: x <= UInt<5>("h1f") -;CHECK: y <= SInt<6>("h20") -;CHECK: Finished Constant Propagation - -circuit top : - module top : - output x : UInt - output y : SInt - x <= shr(UInt(127),2) - y <= shr(SInt(-128),2) - diff --git a/test/passes/expand-accessors/accessor-mem.fir b/test/passes/expand-accessors/accessor-mem.fir deleted file mode 100644 index ce1d8da3..00000000 --- a/test/passes/expand-accessors/accessor-mem.fir +++ /dev/null @@ -1,36 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s - -circuit top : - module top : - input clk : Clock - wire i : UInt<4> - wire j : UInt<32> - wire z : UInt<32> - i <= UInt(1) - mem m : - data-type => UInt<32>[2] - depth => 2 - reader => a - writer => x - read-latency => 0 - write-latency => 1 - m.a.addr <= i - m.a.clk <= clk - m.a.en <= UInt(1) - m.x.addr <= i - m.x.clk <= clk - m.x.en <= UInt(1) - m.x.mask[0] <= UInt(1) - m.x.mask[1] <= UInt(1) - wire b : UInt<32>[2] - b <= m.a.data - node c = b[i] - z <= j - j <= c - wire y : UInt<32>[2] - y[0] <= UInt(1) - y[1] <= UInt(1) - m.x.data <= y - y[i] <= z - -; CHECK: Done! diff --git a/test/passes/expand-accessors/accessor-vec.fir b/test/passes/expand-accessors/accessor-vec.fir deleted file mode 100644 index 8b4b7eb8..00000000 --- a/test/passes/expand-accessors/accessor-vec.fir +++ /dev/null @@ -1,53 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s - -circuit top : - module top : - wire m : UInt<32>[2][2][2] - wire a : UInt<32>[2][2] - wire b : UInt<32>[2] - wire c : UInt<32> - wire i : UInt - wire j : UInt - m[0][0][0] <= UInt(1) - m[1][0][0] <= UInt(1) - m[0][1][0] <= UInt(1) - m[1][1][0] <= UInt(1) - m[0][0][1] <= UInt(1) - m[1][0][1] <= UInt(1) - m[0][1][1] <= UInt(1) - m[1][1][1] <= UInt(1) - i <= UInt(1) - a <= m[i] - b <= a[i] - c <= b[i] - j <= c - - wire x : UInt<32>[2][2] - wire y : UInt<32>[2] - wire z : UInt<32> - x[0][0] <= UInt(1) - x[1][0] <= UInt(1) - x[0][1] <= UInt(1) - x[1][1] <= UInt(1) - y[0] <= UInt(1) - y[1] <= UInt(1) - m[i] <= x - x[i] <= y - y[i] <= z - z <= j - - wire p : {n : UInt<32>[2]} - p.n[0] <= UInt(1) - p.n[1] <= UInt(1) - wire q : UInt<32> - p.n[i] <= q - q <= j - - wire r : {m : UInt<32>}[2] - r[0].m <= UInt(1) - r[1].m <= UInt(1) - wire s : { m : UInt<32>} - s <= r[i] - j <= s.m - -; CHECK: Done! diff --git a/test/passes/expand-accessors/simple.fir b/test/passes/expand-accessors/simple.fir deleted file mode 100644 index b595fc4c..00000000 --- a/test/passes/expand-accessors/simple.fir +++ /dev/null @@ -1,16 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s - -;CHECK: Done! -circuit top : - module top : - output o : UInt - wire m : UInt<32>[2] - wire i : UInt - m[0] <= UInt("h1") - m[1] <= UInt("h1") - i <= UInt("h1") - wire a : UInt<32> - a <= m[i] - o <= a - - diff --git a/test/passes/expand-accessors/simple2.fir b/test/passes/expand-accessors/simple2.fir deleted file mode 100644 index a7d8258d..00000000 --- a/test/passes/expand-accessors/simple2.fir +++ /dev/null @@ -1,18 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s - -;CHECK: Done! -circuit top : - module top : - output o1 : UInt - output o2 : UInt - wire m : UInt<32>[2] - wire i : UInt - m[0] <= UInt("h1") - m[1] <= UInt("h1") - i <= UInt("h1") - wire a : UInt<32> - a <= m[i] - o1 <= a - o2 <= a - - diff --git a/test/passes/expand-whens/bundle-init.fir b/test/passes/expand-whens/bundle-init.fir deleted file mode 100644 index 333619d9..00000000 --- a/test/passes/expand-whens/bundle-init.fir +++ /dev/null @@ -1,27 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p cd 2>&1 | tee %s.out | FileCheck %s -; CHECK: Expand Whens -circuit top : - module top : - input clk : Clock - input reset : UInt<1> - wire w : { x : UInt, y : UInt} - reg r : { x : UInt, y : UInt},clk with : - reset => (reset,w) - wire a : UInt - wire b : UInt - a <= UInt(1) - b <= UInt(2) - - w.x <= b - w.y <= a - r.x <= a - r.y <= b - -; CHECK: w.x <= b -; CHECK: w.y <= a -; CHECK: r.x <= a -; CHECK: r.y <= b -; CHECK: a <= UInt<1>("h1") -; CHECK: b <= UInt<2>("h2") - -; CHECK: Finished Expand Whens diff --git a/test/passes/expand-whens/nested-whens.fir b/test/passes/expand-whens/nested-whens.fir deleted file mode 100644 index 68409931..00000000 --- a/test/passes/expand-whens/nested-whens.fir +++ /dev/null @@ -1,33 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; CHECK: Expand Whens -circuit top : - module top : - input clk : Clock - input reset : UInt<1> - wire p : UInt - wire q : UInt - wire a : UInt - wire b : UInt - wire x : UInt - wire y : UInt - wire z : UInt - wire w : UInt - reg r : UInt, clk with : - reset => (reset, w) - p <= UInt(1) - q <= UInt(1) - a <= UInt(1) - b <= UInt(1) - x <= UInt(1) - y <= UInt(1) - z <= UInt(1) - w <= UInt(1) - - when p : - r <= a - when q : - r <= b - r <= z -; CHECK: r <= z -; CHECK: Finished Expand Whens -; CHECK: Done! diff --git a/test/passes/expand-whens/partial-init.fir b/test/passes/expand-whens/partial-init.fir deleted file mode 100644 index 2fb54717..00000000 --- a/test/passes/expand-whens/partial-init.fir +++ /dev/null @@ -1,34 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s - -; CHECK: Expand Whens -circuit top : - module top : - input clk : Clock - input reset : UInt<1> - poison x : UInt<1> - wire init : UInt<1>[10] - init[0] <= x - init[1] <= x - init[2] <= x - init[3] <= UInt(3) - init[4] <= x - init[5] <= x - init[6] <= x - init[7] <= x - init[8] <= x - init[9] <= x - reg r : UInt<1>[10],clk with : - reset => (reset,init) - r[0] <= UInt(1) - r[1] <= UInt(1) - r[2] <= UInt(1) - r[3] <= UInt(1) - r[4] <= UInt(1) - r[5] <= UInt(1) - r[6] <= UInt(1) - r[7] <= UInt(1) - r[8] <= UInt(1) - r[9] <= UInt(1) - -; CHECK: Finished Expand Whens -; CHECK: Done! diff --git a/test/passes/expand-whens/reg-and-when.fir b/test/passes/expand-whens/reg-and-when.fir deleted file mode 100644 index 97b96735..00000000 --- a/test/passes/expand-whens/reg-and-when.fir +++ /dev/null @@ -1,160 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p cd 2>&1 | tee %s.out ; cat %s.v | FileCheck %s -; CHECK: out__slow__bits <= fromhost__q$deq$valid ? fromhost__q$deq$bits : tohost__q$deq$bits; -circuit Top : - module Top : - input clock : Clock - input reset : UInt<1> - input out_fast : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>} - output out_slow : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>} - output in_fast : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>} - input in_slow : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>} - output clk_slow : UInt<1> - input set_divisor : {valid : UInt<1>, bits : UInt<32>} - output divisor : UInt<32> - - out_fast.ready <= UInt<1>("h00") - out_slow.bits <= UInt<1>("h00") - out_slow.valid <= UInt<1>("h00") - in_fast.bits <= UInt<1>("h00") - in_fast.valid <= UInt<1>("h00") - in_slow.ready <= UInt<1>("h00") - clk_slow <= UInt<1>("h00") - divisor <= UInt<1>("h00") - - inst fromhost_q of Queue_50 - fromhost_q.reset <= UInt<1>("h00") - fromhost_q.enq.bits <= UInt<1>("h00") - fromhost_q.enq.valid <= UInt<1>("h00") - fromhost_q.deq.ready <= UInt<1>("h00") - fromhost_q.clock <= clock - fromhost_q.reset <= reset - - inst tohost_q of Queue_51 - tohost_q.reset <= UInt<1>("h00") - tohost_q.enq.bits <= UInt<1>("h00") - tohost_q.enq.valid <= UInt<1>("h00") - tohost_q.deq.ready <= UInt<1>("h00") - tohost_q.clock <= clock - tohost_q.reset <= reset - - reg out_slow_bits : UInt<17>, clock, reset - out_slow_bits <= tohost_q.deq.bits - when fromhost_q.deq.valid : - out_slow_bits <= fromhost_q.deq.bits - - module Queue_50 : - input clock : Clock - input reset : UInt<1> - input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>} - output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>} - output count : UInt<1> - - enq.ready <= UInt<1>("h00") - deq.bits <= UInt<1>("h00") - deq.valid <= UInt<1>("h00") - count <= UInt<1>("h00") - - cmem ram : UInt<17>[1], clock - reg maybe_full : UInt<1>, clock, reset - onreset maybe_full <= UInt<1>("h00") - node ptr_match = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_115167 = eq(maybe_full, UInt<1>("h00")) - node empty = and(ptr_match, T_115167) - node full = and(ptr_match, maybe_full) - node maybe_flow = and(UInt<1>("h00"), empty) - node do_flow = and(maybe_flow, deq.ready) - node T_115173 = and(enq.ready, enq.valid) - node T_115175 = eq(do_flow, UInt<1>("h00")) - node do_enq = and(T_115173, T_115175) - node T_115177 = and(deq.ready, deq.valid) - node T_115179 = eq(do_flow, UInt<1>("h00")) - node do_deq = and(T_115177, T_115179) - when do_enq : - infer accessor T_115181 = ram[UInt<1>("h00")] - T_115181 <= enq.bits - skip - when do_deq : - skip - node T_115184 = neq(do_enq, do_deq) - when T_115184 : - maybe_full <= do_enq - skip - node T_115186 = eq(empty, UInt<1>("h00")) - node T_115188 = and(UInt<1>("h00"), enq.valid) - node T_115189 = or(T_115186, T_115188) - deq.valid <= T_115189 - node T_115191 = eq(full, UInt<1>("h00")) - node T_115193 = and(UInt<1>("h00"), deq.ready) - node T_115194 = or(T_115191, T_115193) - enq.ready <= T_115194 - infer accessor T_115195 = ram[UInt<1>("h00")] - wire T_115197 : UInt<17> - T_115197 <= T_115195 - when maybe_flow : - T_115197 <= enq.bits - skip - deq.bits <= T_115197 - node ptr_diff = subw(UInt<1>("h00"), UInt<1>("h00")) - node T_115199 = and(maybe_full, ptr_match) - node T_115200 = T_115199 - node T_115201 = cat(T_115200, ptr_diff) - count <= T_115201 - - module Queue_51 : - input clock : Clock - input reset : UInt<1> - input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>} - output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>} - output count : UInt<1> - - enq.ready <= UInt<1>("h00") - deq.bits <= UInt<1>("h00") - deq.valid <= UInt<1>("h00") - count <= UInt<1>("h00") - - cmem ram : UInt<17>[1], clock - reg maybe_full : UInt<1>, clock, reset - onreset maybe_full <= UInt<1>("h00") - node ptr_match = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_115235 = eq(maybe_full, UInt<1>("h00")) - node empty = and(ptr_match, T_115235) - node full = and(ptr_match, maybe_full) - node maybe_flow = and(UInt<1>("h00"), empty) - node do_flow = and(maybe_flow, deq.ready) - node T_115241 = and(enq.ready, enq.valid) - node T_115243 = eq(do_flow, UInt<1>("h00")) - node do_enq = and(T_115241, T_115243) - node T_115245 = and(deq.ready, deq.valid) - node T_115247 = eq(do_flow, UInt<1>("h00")) - node do_deq = and(T_115245, T_115247) - when do_enq : - infer accessor T_115249 = ram[UInt<1>("h00")] - T_115249 <= enq.bits - skip - when do_deq : - skip - node T_115252 = neq(do_enq, do_deq) - when T_115252 : - maybe_full <= do_enq - skip - node T_115254 = eq(empty, UInt<1>("h00")) - node T_115256 = and(UInt<1>("h00"), enq.valid) - node T_115257 = or(T_115254, T_115256) - deq.valid <= T_115257 - node T_115259 = eq(full, UInt<1>("h00")) - node T_115261 = and(UInt<1>("h00"), deq.ready) - node T_115262 = or(T_115259, T_115261) - enq.ready <= T_115262 - infer accessor T_115263 = ram[UInt<1>("h00")] - wire T_115265 : UInt<17> - T_115265 <= T_115263 - when maybe_flow : - T_115265 <= enq.bits - skip - deq.bits <= T_115265 - node ptr_diff = subw(UInt<1>("h00"), UInt<1>("h00")) - node T_115267 = and(maybe_full, ptr_match) - node T_115268 = T_115267 - node T_115269 = cat(T_115268, ptr_diff) - count <= T_115269 - diff --git a/test/passes/expand-whens/reg-dwc.fir b/test/passes/expand-whens/reg-dwc.fir deleted file mode 100644 index 6713b1f2..00000000 --- a/test/passes/expand-whens/reg-dwc.fir +++ /dev/null @@ -1,25 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -circuit top : - module top : - input clk : Clock - input reset : UInt<1> - wire p : UInt - p <= UInt(1) - reg r : UInt,clk with : - reset => (reset,r) - when p : - r <= UInt(2) - -; CHECK: Expand Whens - -; CHECK: circuit top : -; CHECK: module top : -; CHECK: wire p : UInt -; CHECK: reg r : UInt -; CHECK: p <= UInt<1>("h1") -; CHECK: r <= mux(p, UInt<2>("h2"), r) - -; CHECK: Finished Expand Whens - -; CHECK: Done! - diff --git a/test/passes/expand-whens/reg-wdc.fir b/test/passes/expand-whens/reg-wdc.fir deleted file mode 100644 index 6e8e7c04..00000000 --- a/test/passes/expand-whens/reg-wdc.fir +++ /dev/null @@ -1,26 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -circuit top : - module top : - input clk : Clock - input reset : UInt<1> - wire p : UInt - p <= UInt(1) - when p : - reg r : UInt,clk with : - reset => (reset,r) - r <= UInt(2) - -; CHECK: Expand Whens - -; CHECK: circuit top : -; CHECK: module top : -; CHECK: wire p : UInt -; CHECK: reg r : UInt<2>, clk with : -; CHECK: reset => (reset, r) -; CHECK: p <= UInt<1>("h1") -; CHECK-NOT: r <= mux(p, UInt<2>("h2"), r) -; CHECK: r <= UInt<2>("h2") - -; CHECK: Finished Expand Whens - -; CHECK: Done! diff --git a/test/passes/infer-types/bundle.fir b/test/passes/infer-types/bundle.fir deleted file mode 100644 index 0a2d2e4f..00000000 --- a/test/passes/infer-types/bundle.fir +++ /dev/null @@ -1,32 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p ct 2>&1 | tee %s.out | FileCheck %s - -circuit top : - module top : - wire z : { x : UInt, flip y: SInt} - z.x <= UInt(1) - z.y <= SInt(1) - node x = z.x - node y = z.y - wire a : UInt<3>[10] - a[0] <= UInt(1) - a[1] <= UInt(1) - a[2] <= UInt(1) - a[3] <= UInt(1) - a[4] <= UInt(1) - a[5] <= UInt(1) - a[6] <= UInt(1) - a[7] <= UInt(1) - a[8] <= UInt(1) - a[9] <= UInt(1) - node b = a[2] - node c = a[UInt(3)] - -;CHECK: Infer Types -;CHECK: node x = z@<t:{ x : UInt, flip y : SInt}>.x@<t:UInt> -;CHECK: node y = z@<t:{ x : UInt, flip y : SInt}>.y@<t:SInt> -;CHECK: wire a : UInt<3>[10]@<t:UInt>@<t:UInt[10]@<t:UInt>> -;CHECK: node b = a@<t:UInt[10]@<t:UInt>>[2]@<t:UInt> -;CHECK: node c = a@<t:UInt[10]@<t:UInt>>[UInt<2>("h3")@<t:UInt>] -;CHECK: Finished Infer Types - - diff --git a/test/passes/infer-types/gcd.fir b/test/passes/infer-types/gcd.fir deleted file mode 100644 index 398a4944..00000000 --- a/test/passes/infer-types/gcd.fir +++ /dev/null @@ -1,57 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p ct 2>&1 | tee %s.out | FileCheck %s - -;CHECK: Infer Types -circuit top : - module subtracter : - input x : UInt - input y : UInt - output z : UInt - z <= tail(sub(x, y),1) - ;CHECK: z@<t:UInt> <= tail(sub(x@<t:UInt>, y@<t:UInt>)@<t:SInt>, 1)@<t:UInt> - module gcd : - input a : UInt<16> - input b : UInt<16> - input e : UInt<1> - input clk : Clock - input reset : UInt<1> - output z : UInt<16> - reg x : UInt,clk with : - reset => (reset,UInt(0)) - reg y : UInt,clk with : - reset => (reset,UInt(42)) - ; CHECK: reg x : UInt, clk@<t:Clock> with : - ;CHECK:reset => (reset@<t:UInt>, UInt<1>("h0")@<t:UInt>) - when gt(x, y) : - ;CHECK: when gt(x@<t:UInt>, y@<t:UInt>)@<t:UInt> : - inst s of subtracter - ;CHECK: inst s of subtracter : {flip x : UInt, flip y : UInt, z : UInt} - s.x <= x - s.y <= y - x <= s.z - ;CHECK: s@<t:{flip x : UInt, flip y : UInt, z : UInt}>.x@<t:UInt> <= x@<t:UInt> - ;CHECK: s@<t:{flip x : UInt, flip y : UInt, z : UInt}>.y@<t:UInt> <= y@<t:UInt> - ;CHECK: x@<t:UInt> <= s@<t:{flip x : UInt, flip y : UInt, z : UInt}>.z@<t:UInt> - else : - inst s2 of subtracter - s2.x <= x - s2.y <= y - y <= s2.z - when e : - x <= a - y <= b - z <= x - module top : - input a : UInt<16> - input b : UInt<16> - input clk : Clock - input reset : UInt<1> - output z : UInt - inst i of gcd - i.a <= a - i.b <= b - i.clk <= clk - i.reset <= reset - i.e <= UInt(1) - z <= i.z - -; CHECK: Finished Infer Types diff --git a/test/passes/infer-types/primops.fir b/test/passes/infer-types/primops.fir deleted file mode 100644 index de0f9f1d..00000000 --- a/test/passes/infer-types/primops.fir +++ /dev/null @@ -1,152 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p ct 2>&1 | tee %s.out | FileCheck %s - -;CHECK: Infer Types -circuit top : - module top : - input clk : Clock - wire a : UInt<16> - wire b : UInt<8> - wire c : SInt<16> - wire d : SInt<8> - wire e : UInt<1> - - a <= UInt(1) - b <= UInt(1) - c <= SInt(1) - d <= SInt(1) - e <= UInt(1) - - node vadd = add(a, c) ;CHECK: node vadd = add(a@<t:UInt>, c@<t:SInt>)@<t:SInt> - node wadd = add(a, b) ;CHECK: node wadd = add(a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node xadd = add(a, d) ;CHECK: node xadd = add(a@<t:UInt>, d@<t:SInt>)@<t:SInt> - node yadd = add(c, b) ;CHECK: node yadd = add(c@<t:SInt>, b@<t:UInt>)@<t:SInt> - node zadd = add(c, d) ;CHECK: node zadd = add(c@<t:SInt>, d@<t:SInt>)@<t:SInt> - - node vsub = sub(a, c) ;CHECK: node vsub = sub(a@<t:UInt>, c@<t:SInt>)@<t:SInt> - node wsub = sub(a, b) ;CHECK: node wsub = sub(a@<t:UInt>, b@<t:UInt>)@<t:SInt> - node xsub = sub(a, d) ;CHECK: node xsub = sub(a@<t:UInt>, d@<t:SInt>)@<t:SInt> - node ysub = sub(c, b) ;CHECK: node ysub = sub(c@<t:SInt>, b@<t:UInt>)@<t:SInt> - node zsub = sub(c, d) ;CHECK: node zsub = sub(c@<t:SInt>, d@<t:SInt>)@<t:SInt> - - node vmul = mul(a, c) ;CHECK: node vmul = mul(a@<t:UInt>, c@<t:SInt>)@<t:SInt> - node wmul = mul(a, b) ;CHECK: node wmul = mul(a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node xmul = mul(a, d) ;CHECK: node xmul = mul(a@<t:UInt>, d@<t:SInt>)@<t:SInt> - node ymul = mul(c, b) ;CHECK: node ymul = mul(c@<t:SInt>, b@<t:UInt>)@<t:SInt> - node zmul = mul(c, d) ;CHECK: node zmul = mul(c@<t:SInt>, d@<t:SInt>)@<t:SInt> - - node vdiv = div(a, c) ;CHECK: node vdiv = div(a@<t:UInt>, c@<t:SInt>)@<t:SInt> - node wdiv = div(a, b) ;CHECK: node wdiv = div(a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node xdiv = div(a, d) ;CHECK: node xdiv = div(a@<t:UInt>, d@<t:SInt>)@<t:SInt> - node ydiv = div(c, b) ;CHECK: node ydiv = div(c@<t:SInt>, b@<t:UInt>)@<t:SInt> - node zdiv = div(c, d) ;CHECK: node zdiv = div(c@<t:SInt>, d@<t:SInt>)@<t:SInt> - - node vrem = rem(a, c) ;CHECK: node vrem = rem(a@<t:UInt>, c@<t:SInt>)@<t:UInt> - node wrem = rem(a, b) ;CHECK: node wrem = rem(a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node xrem = rem(a, d) ;CHECK: node xrem = rem(a@<t:UInt>, d@<t:SInt>)@<t:UInt> - node yrem = rem(c, b) ;CHECK: node yrem = rem(c@<t:SInt>, b@<t:UInt>)@<t:SInt> - node zrem = rem(c, d) ;CHECK: node zrem = rem(c@<t:SInt>, d@<t:SInt>)@<t:SInt> - - node vlt = lt(a, c) ;CHECK: node vlt = lt(a@<t:UInt>, c@<t:SInt>)@<t:UInt> - node wlt = lt(a, b) ;CHECK: node wlt = lt(a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node xlt = lt(a, d) ;CHECK: node xlt = lt(a@<t:UInt>, d@<t:SInt>)@<t:UInt> - node ylt = lt(c, b) ;CHECK: node ylt = lt(c@<t:SInt>, b@<t:UInt>)@<t:UInt> - node zlt = lt(c, d) ;CHECK: node zlt = lt(c@<t:SInt>, d@<t:SInt>)@<t:UInt> - - node vleq = leq(a, c) ;CHECK: node vleq = leq(a@<t:UInt>, c@<t:SInt>)@<t:UInt> - node wleq = leq(a, b) ;CHECK: node wleq = leq(a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node xleq = leq(a, d) ;CHECK: node xleq = leq(a@<t:UInt>, d@<t:SInt>)@<t:UInt> - node yleq = leq(c, b) ;CHECK: node yleq = leq(c@<t:SInt>, b@<t:UInt>)@<t:UInt> - node zleq = leq(c, d) ;CHECK: node zleq = leq(c@<t:SInt>, d@<t:SInt>)@<t:UInt> - - node vgt = gt(a, c) ;CHECK: node vgt = gt(a@<t:UInt>, c@<t:SInt>)@<t:UInt> - node wgt = gt(a, b) ;CHECK: node wgt = gt(a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node xgt = gt(a, d) ;CHECK: node xgt = gt(a@<t:UInt>, d@<t:SInt>)@<t:UInt> - node ygt = gt(c, b) ;CHECK: node ygt = gt(c@<t:SInt>, b@<t:UInt>)@<t:UInt> - node zgt = gt(c, d) ;CHECK: node zgt = gt(c@<t:SInt>, d@<t:SInt>)@<t:UInt> - - node vgeq = geq(a, c) ;CHECK: node vgeq = geq(a@<t:UInt>, c@<t:SInt>)@<t:UInt> - node wgeq = geq(a, b) ;CHECK: node wgeq = geq(a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node xgeq = geq(a, d) ;CHECK: node xgeq = geq(a@<t:UInt>, d@<t:SInt>)@<t:UInt> - node ygeq = geq(c, b) ;CHECK: node ygeq = geq(c@<t:SInt>, b@<t:UInt>)@<t:UInt> - node zgeq = geq(c, d) ;CHECK: node zgeq = geq(c@<t:SInt>, d@<t:SInt>)@<t:UInt> - - node veq = eq(a, c) ;CHECK: node veq = eq(a@<t:UInt>, c@<t:SInt>)@<t:UInt> - node weq = eq(a, b) ;CHECK: node weq = eq(a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node xeq = eq(a, d) ;CHECK: node xeq = eq(a@<t:UInt>, d@<t:SInt>)@<t:UInt> - node yeq = eq(c, b) ;CHECK: node yeq = eq(c@<t:SInt>, b@<t:UInt>)@<t:UInt> - node zeq = eq(c, d) ;CHECK: node zeq = eq(c@<t:SInt>, d@<t:SInt>)@<t:UInt> - - node vneq = neq(a, c) ;CHECK: node vneq = neq(a@<t:UInt>, c@<t:SInt>)@<t:UInt> - node wneq = neq(a, b) ;CHECK: node wneq = neq(a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node xneq = neq(a, d) ;CHECK: node xneq = neq(a@<t:UInt>, d@<t:SInt>)@<t:UInt> - node yneq = neq(c, b) ;CHECK: node yneq = neq(c@<t:SInt>, b@<t:UInt>)@<t:UInt> - node zneq = neq(c, d) ;CHECK: node zneq = neq(c@<t:SInt>, d@<t:SInt>)@<t:UInt> - - node vpad = pad(a, 10) ;CHECK: node vpad = pad(a@<t:UInt>, 10)@<t:UInt> - node wpad = pad(a, 10) ;CHECK: node wpad = pad(a@<t:UInt>, 10)@<t:UInt> - node zpad = pad(c, 10) ;CHECK: node zpad = pad(c@<t:SInt>, 10)@<t:SInt> - - node vasUInt = asUInt(d) ;CHECK: node vasUInt = asUInt(d@<t:SInt>)@<t:UInt> - node wasUInt = asUInt(a) ;CHECK: node wasUInt = asUInt(a@<t:UInt>)@<t:UInt> - node zasUInt = asUInt(clk) ;CHECK: node zasUInt = asUInt(clk@<t:Clock>)@<t:UInt> - - node vasSInt = asSInt(a) ;CHECK: node vasSInt = asSInt(a@<t:UInt>)@<t:SInt> - node wasSInt = asSInt(c) ;CHECK: node wasSInt = asSInt(c@<t:SInt>)@<t:SInt> - node zasSInt = asSInt(clk) ;CHECK: node zasSInt = asSInt(clk@<t:Clock>)@<t:SInt> - - node vasClock = asClock(a) ;CHECK: node vasClock = asClock(a@<t:UInt>)@<t:Clock> - node wasClock = asClock(c) ;CHECK: node wasClock = asClock(c@<t:SInt>)@<t:Clock> - node zasClock = asClock(clk) ;CHECK: node zasClock = asClock(clk@<t:Clock>)@<t:Clock> - - node vshl = shl(a, 10) ;CHECK: node vshl = shl(a@<t:UInt>, 10)@<t:UInt> - node wshl = shl(a, 10) ;CHECK: node wshl = shl(a@<t:UInt>, 10)@<t:UInt> - node zshl = shl(c, 10) ;CHECK: node zshl = shl(c@<t:SInt>, 10)@<t:SInt> - - node vdshl = dshl(a, a) ;CHECK: node vdshl = dshl(a@<t:UInt>, a@<t:UInt>)@<t:UInt> - node wdshl = dshl(a, a) ;CHECK: node wdshl = dshl(a@<t:UInt>, a@<t:UInt>)@<t:UInt> - node zdshl = dshl(c, a) ;CHECK: node zdshl = dshl(c@<t:SInt>, a@<t:UInt>)@<t:SInt> - - node vdshr = dshr(a, a) ;CHECK: node vdshr = dshr(a@<t:UInt>, a@<t:UInt>)@<t:UInt> - node wdshr = dshr(a, a) ;CHECK: node wdshr = dshr(a@<t:UInt>, a@<t:UInt>)@<t:UInt> - node zdshr = dshr(c, a) ;CHECK: node zdshr = dshr(c@<t:SInt>, a@<t:UInt>)@<t:SInt> - - node vshr = shr(a, 10) ;CHECK: node vshr = shr(a@<t:UInt>, 10)@<t:UInt> - node wshr = shr(a, 10) ;CHECK: node wshr = shr(a@<t:UInt>, 10)@<t:UInt> - node zshr = shr(c, 10) ;CHECK: node zshr = shr(c@<t:SInt>, 10)@<t:SInt> - - node vcvt = cvt(a) ;CHECK: node vcvt = cvt(a@<t:UInt>)@<t:SInt> - node wcvt = cvt(a) ;CHECK: node wcvt = cvt(a@<t:UInt>)@<t:SInt> - node zcvt = cvt(c) ;CHECK: node zcvt = cvt(c@<t:SInt>)@<t:SInt> - - node vneg = neg(a) ;CHECK: node vneg = neg(a@<t:UInt>)@<t:SInt> - node wneg = neg(a) ;CHECK: node wneg = neg(a@<t:UInt>)@<t:SInt> - node zneg = neg(c) ;CHECK: node zneg = neg(c@<t:SInt>)@<t:SInt> - - node wnot = not(a) ;CHECK: node wnot = not(a@<t:UInt>)@<t:UInt> - node unot = not(c) ;CHECK: node unot = not(c@<t:SInt>)@<t:UInt> - - node WAND = and(a, b) ;CHECK: node WAND = and(a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node uand = and(c, d) ;CHECK: node uand = and(c@<t:SInt>, d@<t:SInt>)@<t:UInt> - - node WOR = or(a, b) ;CHECK: node WOR = or(a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node uor = or(c, d) ;CHECK: node uor = or(c@<t:SInt>, d@<t:SInt>)@<t:UInt> - - node wxor = xor(a, b) ;CHECK: node wxor = xor(a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node uxor = xor(c, d) ;CHECK: node uxor = xor(c@<t:SInt>, d@<t:SInt>)@<t:UInt> - - node wbits = bits(a, 2, 0) ;CHECK: node wbits = bits(a@<t:UInt>, 2, 0)@<t:UInt> - node ubits = bits(c, 2, 0) ;CHECK: node ubits = bits(c@<t:SInt>, 2, 0)@<t:UInt> - - node xcat = cat(a, b) ;CHECK: node xcat = cat(a@<t:UInt>, b@<t:UInt>)@<t:UInt> - - node uandr = andr(a, b, a) ;CHECK: node uandr = andr(a@<t:UInt>, b@<t:UInt>, a@<t:UInt>)@<t:UInt> - node uorr = orr(a, b, a) ;CHECK: node uorr = orr(a@<t:UInt>, b@<t:UInt>, a@<t:UInt>)@<t:UInt> - node uxorr = xorr(a, b, a) ;CHECK: node uxorr = xorr(a@<t:UInt>, b@<t:UInt>, a@<t:UInt>)@<t:UInt> - - node whead = head(a, 2) ;CHECK: node whead = head(a@<t:UInt>, 2)@<t:UInt> - node uhead = head(c, 2) ;CHECK: node uhead = head(c@<t:SInt>, 2)@<t:UInt> - - node wtail = tail(a, 2) ;CHECK: node wtail = tail(a@<t:UInt>, 2)@<t:UInt> - node utail = tail(c, 2) ;CHECK: node utail = tail(c@<t:SInt>, 2)@<t:UInt> - -;CHECK: Finished Infer Types diff --git a/test/passes/infer-widths/dsh.fir b/test/passes/infer-widths/dsh.fir deleted file mode 100644 index f36b8ad4..00000000 --- a/test/passes/infer-widths/dsh.fir +++ /dev/null @@ -1,28 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p cd 2>&1 | tee %s.out | FileCheck %s - -;CHECK: Infer Widths - -circuit top : - module top : - wire x : UInt<16> - wire z : SInt<16> - wire y : UInt<3> - wire a : UInt - wire b : SInt - wire c : UInt - wire d : SInt - x <= UInt(1) - y <= UInt(1) - z <= SInt(1) - - a <= dshl(x,y) - b <= dshl(z,y) - c <= dshr(x,y) - d <= dshr(z,y) - - -; CHECK: wire a : UInt<23> -; CHECK: wire b : SInt<23> -; CHECK: wire c : UInt<16> -; CHECK: wire d : SInt<16> -; CHECK: Finished Infer Widths diff --git a/test/passes/infer-widths/gcd.fir b/test/passes/infer-widths/gcd.fir deleted file mode 100644 index 1333fbda..00000000 --- a/test/passes/infer-widths/gcd.fir +++ /dev/null @@ -1,49 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p ctd 2>&1 | tee %s.out | FileCheck %s - -;CHECK: Infer Widths -circuit top : - module subtracter : - input x : UInt - input y : UInt - output q : UInt - q <= tail(sub(x, y),1) - module gcd : - input a : UInt<16> - input b : UInt<16> - input e : UInt<1> - input clk : Clock - input reset : UInt<1> - output z : UInt<16> - reg x : UInt,clk with : - reset => (reset,UInt(0)) - reg y : UInt,clk with : - reset => (reset,UInt(42)) - when gt(x, y) : - inst s of subtracter - s.x <= x - s.y <= y - x <= s.q - else : - inst s2 of subtracter - s2.x <= x - s2.y <= y - y <= s2.q - when e : - x <= a - y <= b - z <= x - module top : - input a : UInt<16> - input b : UInt<16> - input clk : Clock - input reset : UInt<1> - output z : UInt - inst i of gcd - i.a <= a - i.b <= b - i.clk <= clk - i.reset <= reset - i.e <= UInt(1) - z <= i.z - -; CHECK: Finished Infer Widths diff --git a/test/passes/infer-widths/shr.fir b/test/passes/infer-widths/shr.fir deleted file mode 100644 index 6a918ba9..00000000 --- a/test/passes/infer-widths/shr.fir +++ /dev/null @@ -1,129 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s - -;CHECK: Infer Widths -; CHECK: Finished Infer Widths - -circuit MemSerdes : - module MemSerdes : - input clock : Clock - input reset : UInt<1> - input wide : {req_cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<26>, tag : UInt<7>, rw : UInt<1>}}, req_data : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, tag : UInt<7>}}} - output narrow : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, flip resp : {valid : UInt<1>, bits : UInt<16>}} - - wide.resp.bits.tag <= UInt<1>("h00") - wide.resp.bits.data <= UInt<1>("h00") - wide.resp.valid <= UInt<1>("h00") - wide.req_data.ready <= UInt<1>("h00") - wide.req_cmd.ready <= UInt<1>("h00") - narrow.req.bits <= UInt<1>("h00") - narrow.req.valid <= UInt<1>("h00") - - node T_218961 = cat(wide.req_cmd.bits.tag, wide.req_cmd.bits.rw) - node T_218962 = cat(wide.req_cmd.bits.addr, T_218961) - reg out_buf : UInt, clock with : - reset => ( reset, out_buf) - reg in_buf : UInt, clock with : - reset => ( reset, in_buf) - reg state : UInt<3>, clock with : - reset => ( reset,UInt<3>("h00")) - reg send_cnt : UInt<3>, clock with : - reset => ( reset, UInt<3>("h00")) - reg data_send_cnt : UInt<2>, clock with : - reset => ( reset, UInt<2>("h00")) - node T_218984 = eq(send_cnt, UInt<2>("h02")) - node adone = and(narrow.req.ready, T_218984) - node T_218987 = eq(send_cnt, UInt<3>("h07")) - node ddone = and(narrow.req.ready, T_218987) - - node T_218989 = and(narrow.req.valid, narrow.req.ready) - when T_218989 : - node T_218991 = tail(add(send_cnt, UInt<1>("h01")),1) - send_cnt <= T_218991 - node T_218992 = shr(out_buf, 16) - out_buf <= T_218992 - - node T_218993 = and(wide.req_cmd.valid, wide.req_cmd.ready) - when T_218993 : - node T_218994 = cat(wide.req_cmd.bits.tag, wide.req_cmd.bits.rw) - node T_218995 = cat(wide.req_cmd.bits.addr, T_218994) - out_buf <= T_218995 - - node T_218996 = and(wide.req_data.valid, wide.req_data.ready) - when T_218996 : out_buf <= wide.req_data.bits.data - node T_218997 = eq(state, UInt<3>("h00")) - wide.req_cmd.ready <= T_218997 - node T_218998 = eq(state, UInt<3>("h03")) - wide.req_data.ready <= T_218998 - node T_218999 = eq(state, UInt<3>("h01")) - node T_219000 = eq(state, UInt<3>("h02")) - node T_219001 = or(T_218999, T_219000) - node T_219002 = eq(state, UInt<3>("h04")) - node T_219003 = or(T_219001, T_219002) - narrow.req.valid <= T_219003 - narrow.req.bits <= out_buf - - - node T_219004 = eq(state, UInt<3>("h00")) - node T_219005 = and(T_219004, wide.req_cmd.valid) - when T_219005 : - node T_219006 = mux(wide.req_cmd.bits.rw, UInt<3>("h02"), UInt<3>("h01")) - state <= T_219006 - - - node T_219007 = eq(state, UInt<3>("h01")) - node T_219008 = and(T_219007, adone) - when T_219008 : - state <= UInt<3>("h00") - send_cnt <= UInt<1>("h00") - - - node T_219010 = eq(state, UInt<3>("h02")) - node T_219011 = and(T_219010, adone) - when T_219011 : - state <= UInt<3>("h03") - send_cnt <= UInt<1>("h00") - - - node T_219013 = eq(state, UInt<3>("h03")) - node T_219014 = and(T_219013, wide.req_data.valid) - when T_219014 : state <= UInt<3>("h04") - - - node T_219015 = eq(state, UInt<3>("h04")) - node T_219016 = and(T_219015, ddone) - when T_219016 : - node T_219018 = tail(add(data_send_cnt, UInt<1>("h01")),1) - data_send_cnt <= T_219018 - node T_219020 = eq(data_send_cnt, UInt<2>("h03")) - node T_219021 = mux(T_219020, UInt<3>("h00"), UInt<3>("h03")) - state <= T_219021 - send_cnt <= UInt<1>("h00") - reg recv_cnt : UInt<4>, clock with : - reset => ( reset, UInt<4>("h00")) - reg data_recv_cnt : UInt<2>, clock with : - reset => ( reset, UInt<2>("h00")) - reg resp_val : UInt<1>, clock with : - reset => ( reset, UInt<1>("h00")) - resp_val <= UInt<1>("h00") - when narrow.resp.valid : - node T_219031 = tail(add(recv_cnt, UInt<1>("h01")),1) - recv_cnt <= T_219031 - - node T_219033 = eq(recv_cnt, UInt<4>("h08")) - when T_219033 : - recv_cnt <= UInt<1>("h00") - node T_219036 = tail(add(data_recv_cnt, UInt<1>("h01")),1) - data_recv_cnt <= T_219036 - resp_val <= UInt<1>("h01") - node T_219038 = bits(in_buf, 143, 16) - node T_219039 = cat(narrow.resp.bits, T_219038) - in_buf <= T_219039 - wide.resp.valid <= resp_val - wire T_219043 : {data : UInt<128>, tag : UInt<7>} - T_219043.tag <= UInt<1>("h00") - T_219043.data <= UInt<1>("h00") - node T_219048 = bits(in_buf, 6, 0) - T_219043.tag <= T_219048 - node T_219049 = bits(in_buf, 134, 7) - T_219043.data <= T_219049 - wide.resp.bits <- T_219043 diff --git a/test/passes/infer-widths/simple.fir b/test/passes/infer-widths/simple.fir deleted file mode 100644 index 63b31a32..00000000 --- a/test/passes/infer-widths/simple.fir +++ /dev/null @@ -1,28 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p cTwd 2>&1 | tee %s.out | FileCheck %s - -;CHECK: Infer Widths -circuit top : - module top : - input clk : Clock - input reset : UInt<1> - wire e : UInt<30> - e <= UInt(1) - reg y : UInt,clk with : - reset => (reset,y) - y <= e - - wire a : UInt<20> - a <= UInt(1) - wire b : UInt<10> - b <= UInt(1) - wire c : UInt - c <= UInt(1) - wire z : UInt - - z <= mux(c,a,b) - - - -; CHECK: Finished Infer Widths -; CHECK: Done! - diff --git a/test/passes/inline/gcd.fir b/test/passes/inline/gcd.fir deleted file mode 100644 index 781b949c..00000000 --- a/test/passes/inline/gcd.fir +++ /dev/null @@ -1,50 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; XFAIL: * - -;CHECK: Inline Instances -circuit top : - module subtracter : - input x : UInt - input y : UInt - output q : UInt - q <= subw(x, y) - module gcd : - input a : UInt<16> - input b : UInt<16> - input e : UInt<1> - input clk : Clock - input reset : UInt<1> - output z : UInt<16> - reg x : UInt,clk,reset - reg y : UInt,clk,reset - onreset x <= UInt(0) - onreset y <= UInt(42) - when gt(x, y) : - inst s of subtracter - s.x <= x - s.y <= y - x <= s.q - else : - inst s2 of subtracter - s2.x <= x - s2.y <= y - y <= s2.q - when e : - x <= a - y <= b - z <= x - module top : - input a : UInt<16> - input b : UInt<16> - input clk : Clock - input reset : UInt<1> - output z : UInt - inst i of gcd - i.a <= a - i.b <= b - i.clk <= clk - i.reset <= reset - i.e <= UInt(1) - z <= i.z - -; CHECK: Finished Inline Instances diff --git a/test/passes/jacktest/ALUTop.fir b/test/passes/jacktest/ALUTop.fir deleted file mode 100644 index a0aadb11..00000000 --- a/test/passes/jacktest/ALUTop.fir +++ /dev/null @@ -1,117 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: Done! -circuit ALUTop : - module ALU : - input B : UInt<32> - output out : UInt<32> - output sum : UInt<32> - input A : UInt<32> - input alu_op : UInt<4> - - node shamt = bits(B, 4, 0) - node T_157 = tail(add(A, B),1) - node T_158 = tail(sub(A, B),1) - node T_159 = cvt(A) - node T_160 = dshr(T_159, shamt) - node T_161 = asUInt(T_160) - node T_162 = dshr(A, shamt) - node T_163 = dshl(A, shamt) - node T_164 = bits(T_163, 31, 0) - node T_165 = cvt(A) - node T_166 = cvt(B) - node T_167 = lt(T_165, T_166) - node T_168 = asUInt(T_167) - node T_169 = lt(A, B) - node T_170 = asUInt(T_169) - node T_171 = and(A, B) - node T_172 = or(A, B) - node T_173 = xor(A, B) - node T_174 = eq(UInt<4>(10), alu_op) - node T_175 = mux(T_174, A, B) - node T_176 = eq(UInt<4>(4), alu_op) - node T_177 = mux(T_176, T_173, T_175) - node T_178 = eq(UInt<4>(3), alu_op) - node T_179 = mux(T_178, T_172, T_177) - node T_180 = eq(UInt<4>(2), alu_op) - node T_181 = mux(T_180, T_171, T_179) - node T_182 = eq(UInt<4>(7), alu_op) - node T_183 = mux(T_182, T_170, T_181) - node T_184 = eq(UInt<4>(5), alu_op) - node T_185 = mux(T_184, T_168, T_183) - node T_186 = eq(UInt<4>(6), alu_op) - node T_187 = mux(T_186, T_164, T_185) - node T_188 = eq(UInt<4>(8), alu_op) - node T_189 = mux(T_188, T_162, T_187) - node T_190 = eq(UInt<4>(9), alu_op) - node T_191 = mux(T_190, T_161, T_189) - node T_192 = eq(UInt<4>(1), alu_op) - node T_193 = mux(T_192, T_158, T_191) - node T_194 = eq(UInt<4>(0), alu_op) - node oot = mux(T_194, T_157, T_193) - node T_195 = bits(oot, 31, 0) - out <= T_195 - node T_196 = bits(alu_op, 0, 0) - node T_197 = tail(sub(UInt<1>(0), B),1) - node T_198 = mux(T_196, T_197, B) - node T_199 = tail(add(A, T_198),1) - sum <= T_199 - module ALUdec : - input opcode : UInt<7> - input funct : UInt<3> - input add_rshift_type : UInt<1> - output alu_op : UInt<4> - - node T_200 = mux(add_rshift_type, UInt<4>(1), UInt<4>(0)) - node T_201 = mux(add_rshift_type, UInt<4>(9), UInt<4>(8)) - node T_202 = eq(UInt<3>(5), funct) - node T_203 = mux(T_202, T_201, UInt<4>(15)) - node T_204 = eq(UInt<3>(7), funct) - node T_205 = mux(T_204, UInt<4>(2), T_203) - node T_206 = eq(UInt<3>(6), funct) - node T_207 = mux(T_206, UInt<4>(3), T_205) - node T_208 = eq(UInt<3>(4), funct) - node T_209 = mux(T_208, UInt<4>(4), T_207) - node T_210 = eq(UInt<3>(3), funct) - node T_211 = mux(T_210, UInt<4>(7), T_209) - node T_212 = eq(UInt<3>(2), funct) - node T_213 = mux(T_212, UInt<4>(5), T_211) - node T_214 = eq(UInt<3>(1), funct) - node T_215 = mux(T_214, UInt<4>(6), T_213) - node T_216 = eq(UInt<3>(0), funct) - node alu_op1 = mux(T_216, T_200, T_215) - node T_217 = eq(UInt<7>(19), opcode) - node T_218 = mux(T_217, alu_op1, UInt<4>(15)) - node T_219 = eq(UInt<7>(51), opcode) - node T_220 = mux(T_219, alu_op1, T_218) - node T_221 = eq(UInt<7>(3), opcode) - node T_222 = mux(T_221, UInt<4>(0), T_220) - node T_223 = eq(UInt<7>(35), opcode) - node T_224 = mux(T_223, UInt<4>(0), T_222) - node T_225 = eq(UInt<7>(99), opcode) - node T_226 = mux(T_225, UInt<4>(0), T_224) - node T_227 = eq(UInt<7>(103), opcode) - node T_228 = mux(T_227, UInt<4>(0), T_226) - node T_229 = eq(UInt<7>(111), opcode) - node T_230 = mux(T_229, UInt<4>(0), T_228) - node T_231 = eq(UInt<7>(23), opcode) - node T_232 = mux(T_231, UInt<4>(0), T_230) - node T_233 = eq(UInt<7>(55), opcode) - node alu_op2 = mux(T_233, UInt<4>(11), T_232) - alu_op <= alu_op2 - module ALUTop : - input B : UInt<32> - output out : UInt<32> - input A : UInt<32> - input opcode : UInt<7> - input funct : UInt<3> - input add_rshift_type : UInt<1> - - inst alu of ALU - inst alu_dec of ALUdec - alu_dec.opcode <= opcode - alu_dec.funct <= funct - alu_dec.add_rshift_type <= add_rshift_type - alu.A <= A - alu.B <= B - out <= alu.out - alu.alu_op <= alu_dec.alu_op diff --git a/test/passes/jacktest/ComplexAssign.fir b/test/passes/jacktest/ComplexAssign.fir deleted file mode 100644 index 9ce51652..00000000 --- a/test/passes/jacktest/ComplexAssign.fir +++ /dev/null @@ -1,15 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: Done! -circuit ComplexAssign : - module ComplexAssign : - input in : {re : UInt<10>, im : UInt<10>} - output out : {re : UInt<10>, im : UInt<10>} - input e : UInt<1> - when e : - wire T_18 : {re : UInt<10>, im : UInt<10>} - T_18 <= in - out.re <= T_18.re - out.im <= T_18.im - else : - out.re <= UInt<1>(0) - out.im <= UInt<1>(0) diff --git a/test/passes/jacktest/Counter.fir b/test/passes/jacktest/Counter.fir deleted file mode 100644 index 266c1849..00000000 --- a/test/passes/jacktest/Counter.fir +++ /dev/null @@ -1,18 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: Done! -circuit Counter : - module Counter : - input inc : UInt<1> - input clk : Clock - input reset : UInt<1> - output tot : UInt<8> - input amt : UInt<4> - - reg T_13 : UInt<8>,clk with : - reset => (reset,UInt<8>(0)) - when inc : - node T_14 = tail(add(T_13, amt),1) - node T_15 = gt(T_14, UInt<8>(255)) - node T_16 = mux(T_15, UInt<1>(0), T_14) - T_13 <= T_16 - tot <= T_13 diff --git a/test/passes/jacktest/EnableShiftRegister.fir b/test/passes/jacktest/EnableShiftRegister.fir deleted file mode 100644 index 9927e83f..00000000 --- a/test/passes/jacktest/EnableShiftRegister.fir +++ /dev/null @@ -1,24 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: Done! -circuit EnableShiftRegister : - module EnableShiftRegister : - input in : UInt<4> - input clk : Clock - input reset : UInt<1> - output out : UInt<4> - input shift : UInt<1> - - reg r0 : UInt<4>,clk with : - reset => (reset,UInt<4>(0)) - reg r1 : UInt<4>,clk with : - reset => (reset,UInt<4>(0)) - reg r2 : UInt<4>,clk with : - reset => (reset,UInt<4>(0)) - reg r3 : UInt<4>,clk with : - reset => (reset,UInt<4>(0)) - when shift : - r0 <= in - r1 <= r0 - r2 <= r1 - r3 <= r2 - out <= r3 diff --git a/test/passes/jacktest/LFSR16.fir b/test/passes/jacktest/LFSR16.fir deleted file mode 100644 index b3fb05cc..00000000 --- a/test/passes/jacktest/LFSR16.fir +++ /dev/null @@ -1,23 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: Done! -circuit LFSR16 : - module LFSR16 : - output out : UInt<16> - input inc : UInt<1> - input clk : Clock - input reset : UInt<1> - - reg res : UInt<16>,clk with : - reset => (reset,UInt<16>(1)) - when inc : - node T_16 = bits(res, 0, 0) - node T_17 = bits(res, 2, 2) - node T_18 = xor(T_16, T_17) - node T_19 = bits(res, 3, 3) - node T_20 = xor(T_18, T_19) - node T_21 = bits(res, 5, 5) - node T_22 = xor(T_20, T_21) - node T_23 = bits(res, 15, 1) - node T_24 = cat(T_22, T_23) - res <= T_24 - out <= res diff --git a/test/passes/jacktest/MemorySearch.fir b/test/passes/jacktest/MemorySearch.fir deleted file mode 100644 index 39c19dda..00000000 --- a/test/passes/jacktest/MemorySearch.fir +++ /dev/null @@ -1,35 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: Done! -circuit MemorySearch : - module MemorySearch : - input target : UInt<4> - output address : UInt<3> - input en : UInt<1> - input clk : Clock - input reset : UInt<1> - output done : UInt<1> - - reg index : UInt<3>,clk with : - reset => (reset,UInt<3>(0)) - wire elts : UInt<4>[7] - elts[0] <= UInt<4>(0) - elts[1] <= UInt<4>(4) - elts[2] <= UInt<4>(15) - elts[3] <= UInt<4>(14) - elts[4] <= UInt<4>(2) - elts[5] <= UInt<4>(5) - elts[6] <= UInt<4>(13) - node elt = elts[index] - node T_35 = not(en) - node T_36 = eq(elt, target) - node T_37 = eq(index, UInt<3>(7)) - node T_38 = or(T_36, T_37) - node end = and(T_35, T_38) - when en : index <= UInt<1>(0) - else : - node T_39 = not(end) - when T_39 : - node T_40 = tail(add(index, UInt<1>(1)),1) - index <= T_40 - done <= end - address <= index diff --git a/test/passes/jacktest/ModuleVec.fir b/test/passes/jacktest/ModuleVec.fir deleted file mode 100644 index 6f9b699b..00000000 --- a/test/passes/jacktest/ModuleVec.fir +++ /dev/null @@ -1,28 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: Done! -circuit ModuleVec : - module PlusOne : - input in : UInt<32> - output out : UInt<32> - - node T_33 = tail(add(in, UInt<1>(1)),1) - out <= T_33 - module PlusOne_25 : - input in : UInt<32> - output out : UInt<32> - - node T_34 = tail(add(in, UInt<1>(1)),1) - out <= T_34 - module ModuleVec : - input ins : UInt<32>[2] - output outs : UInt<32>[2] - - inst T_35 of PlusOne - inst T_36 of PlusOne_25 - wire pluses : {flip in : UInt<32>, out : UInt<32>}[2] - pluses[0] <= T_35 - pluses[1] <= T_36 - pluses[0].in <= ins[0] - outs[0] <= pluses[0].out - pluses[1].in <= ins[1] - outs[1] <= pluses[1].out diff --git a/test/passes/jacktest/Mul.fir b/test/passes/jacktest/Mul.fir deleted file mode 100644 index 370c84a7..00000000 --- a/test/passes/jacktest/Mul.fir +++ /dev/null @@ -1,29 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: Done! -circuit Mul : - module Mul : - input x : UInt<2> - input y : UInt<2> - output z : UInt<4> - - wire tbl : UInt<4>[16] - tbl[0] <= UInt<4>(0) - tbl[1] <= UInt<4>(0) - tbl[2] <= UInt<4>(0) - tbl[3] <= UInt<4>(0) - tbl[4] <= UInt<4>(0) - tbl[5] <= UInt<4>(1) - tbl[6] <= UInt<4>(2) - tbl[7] <= UInt<4>(3) - tbl[8] <= UInt<4>(0) - tbl[9] <= UInt<4>(2) - tbl[10] <= UInt<4>(4) - tbl[11] <= UInt<4>(6) - tbl[12] <= UInt<4>(0) - tbl[13] <= UInt<4>(3) - tbl[14] <= UInt<4>(6) - tbl[15] <= UInt<4>(9) - node T_42 = shl(x, 2) - node T_43 = or(T_42, y) - node T_44 = tbl[T_43] - z <= T_44 diff --git a/test/passes/jacktest/RegisterVecShift.fir b/test/passes/jacktest/RegisterVecShift.fir deleted file mode 100644 index f138d00a..00000000 --- a/test/passes/jacktest/RegisterVecShift.fir +++ /dev/null @@ -1,31 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: Done! -circuit RegisterVecShift : - module RegisterVecShift : - input load : UInt<1> - input clk : Clock - input reset : UInt<1> - output out : UInt<4> - input shift : UInt<1> - input ins : UInt<4>[4] - - reg delays : UInt<4>[4],clk with : - reset => (reset,delays) - when reset : - wire T_33 : UInt<4>[4] - T_33[0] <= UInt<4>(0) - T_33[1] <= UInt<4>(0) - T_33[2] <= UInt<4>(0) - T_33[3] <= UInt<4>(0) - delays <= T_33 - when load : - delays[0] <= ins[0] - delays[1] <= ins[1] - delays[2] <= ins[2] - delays[3] <= ins[3] - else : when shift : - delays[0] <= ins[0] - delays[1] <= delays[0] - delays[2] <= delays[1] - delays[3] <= delays[2] - out <= delays[3] diff --git a/test/passes/jacktest/Rom.fir b/test/passes/jacktest/Rom.fir deleted file mode 100644 index db76b9c7..00000000 --- a/test/passes/jacktest/Rom.fir +++ /dev/null @@ -1,26 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: Done! -circuit Rom : - module Rom : - output out : UInt<5> - input addr : UInt<4> - - wire r : UInt<5>[16] - r[0] <= UInt<5>(0) - r[1] <= UInt<5>(2) - r[2] <= UInt<5>(4) - r[3] <= UInt<5>(6) - r[4] <= UInt<5>(8) - r[5] <= UInt<5>(10) - r[6] <= UInt<5>(12) - r[7] <= UInt<5>(14) - r[8] <= UInt<5>(16) - r[9] <= UInt<5>(18) - r[10] <= UInt<5>(20) - r[11] <= UInt<5>(22) - r[12] <= UInt<5>(24) - r[13] <= UInt<5>(26) - r[14] <= UInt<5>(28) - r[15] <= UInt<5>(30) - node T_39 = r[addr] - out <= T_39 diff --git a/test/passes/jacktest/RouterUnitTest.fir b/test/passes/jacktest/RouterUnitTest.fir deleted file mode 100644 index dec4083e..00000000 --- a/test/passes/jacktest/RouterUnitTest.fir +++ /dev/null @@ -1,1076 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; CHECK: Done! - -circuit RouterUnitTester : - module Router : - input clk : Clock - input reset : UInt<1> - output io : {read_routing_table_request : {ready : UInt<1>, flip valid : UInt<1>, flip bits : {addr : UInt<32>}}, read_routing_table_response : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<8>}, load_routing_table_request : {ready : UInt<1>, flip valid : UInt<1>, flip bits : {addr : UInt<32>, data : UInt<32>}}, in : {ready : UInt<1>, flip valid : UInt<1>, flip bits : {header : UInt<8>, body : UInt<64>}}, outs : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : UInt<8>, body : UInt<64>}}[4]} - - io.outs[0].bits.body <= UInt<1>("h00") - io.outs[0].bits.header <= UInt<1>("h00") - io.outs[0].valid <= UInt<1>("h00") - io.outs[1].bits.body <= UInt<1>("h00") - io.outs[1].bits.header <= UInt<1>("h00") - io.outs[1].valid <= UInt<1>("h00") - io.outs[2].bits.body <= UInt<1>("h00") - io.outs[2].bits.header <= UInt<1>("h00") - io.outs[2].valid <= UInt<1>("h00") - io.outs[3].bits.body <= UInt<1>("h00") - io.outs[3].bits.header <= UInt<1>("h00") - io.outs[3].valid <= UInt<1>("h00") - io.in.ready <= UInt<1>("h00") - io.load_routing_table_request.ready <= UInt<1>("h00") - io.read_routing_table_response.bits <= UInt<1>("h00") - io.read_routing_table_response.valid <= UInt<1>("h00") - io.read_routing_table_request.ready <= UInt<1>("h00") - cmem tbl : UInt<3>[15] - when reset : - infer mport T_115 = tbl[UInt<1>("h00")], clk - T_115 <= UInt<32>("h00") - infer mport T_118 = tbl[UInt<1>("h01")], clk - T_118 <= UInt<32>("h00") - infer mport T_121 = tbl[UInt<2>("h02")], clk - T_121 <= UInt<32>("h00") - infer mport T_124 = tbl[UInt<2>("h03")], clk - T_124 <= UInt<32>("h00") - infer mport T_127 = tbl[UInt<3>("h04")], clk - T_127 <= UInt<32>("h00") - infer mport T_130 = tbl[UInt<3>("h05")], clk - T_130 <= UInt<32>("h00") - infer mport T_133 = tbl[UInt<3>("h06")], clk - T_133 <= UInt<32>("h00") - infer mport T_136 = tbl[UInt<3>("h07")], clk - T_136 <= UInt<32>("h00") - infer mport T_139 = tbl[UInt<4>("h08")], clk - T_139 <= UInt<32>("h00") - infer mport T_142 = tbl[UInt<4>("h09")], clk - T_142 <= UInt<32>("h00") - infer mport T_145 = tbl[UInt<4>("h0a")], clk - T_145 <= UInt<32>("h00") - infer mport T_148 = tbl[UInt<4>("h0b")], clk - T_148 <= UInt<32>("h00") - infer mport T_151 = tbl[UInt<4>("h0c")], clk - T_151 <= UInt<32>("h00") - infer mport T_154 = tbl[UInt<4>("h0d")], clk - T_154 <= UInt<32>("h00") - infer mport T_157 = tbl[UInt<4>("h0e")], clk - T_157 <= UInt<32>("h00") - skip - io.read_routing_table_request.ready <= UInt<1>("h01") - io.load_routing_table_request.ready <= UInt<1>("h01") - io.read_routing_table_response.valid <= UInt<1>("h00") - io.read_routing_table_response.bits <= UInt<1>("h00") - io.in.ready <= UInt<1>("h01") - io.outs[0].valid <= UInt<1>("h00") - io.outs[0].bits.body <= UInt<1>("h00") - io.outs[0].bits.header <= UInt<1>("h00") - io.outs[1].valid <= UInt<1>("h00") - io.outs[1].bits.body <= UInt<1>("h00") - io.outs[1].bits.header <= UInt<1>("h00") - io.outs[2].valid <= UInt<1>("h00") - io.outs[2].bits.body <= UInt<1>("h00") - io.outs[2].bits.header <= UInt<1>("h00") - io.outs[3].valid <= UInt<1>("h00") - io.outs[3].bits.body <= UInt<1>("h00") - io.outs[3].bits.header <= UInt<1>("h00") - node T_176 = and(io.read_routing_table_request.valid, io.read_routing_table_response.ready) - when T_176 : - io.read_routing_table_request.ready <= UInt<1>("h01") - infer mport T_178 = tbl[io.read_routing_table_request.bits.addr], clk - io.read_routing_table_response.valid <= UInt<1>("h01") - io.read_routing_table_response.bits <= T_178 - skip - node T_181 = eq(T_176, UInt<1>("h00")) - node T_182 = and(T_181, io.load_routing_table_request.valid) - when T_182 : - io.load_routing_table_request.ready <= UInt<1>("h01") - infer mport T_184 = tbl[io.load_routing_table_request.bits.addr], clk - T_184 <= io.load_routing_table_request.bits.data - node T_186 = eq(reset, UInt<1>("h00")) - when T_186 : - printf(clk, UInt<1>(1), "setting tbl(%d) to %d", io.load_routing_table_request.bits.addr, io.load_routing_table_request.bits.data) - skip - skip - node T_188 = eq(T_176, UInt<1>("h00")) - node T_190 = eq(io.load_routing_table_request.valid, UInt<1>("h00")) - node T_191 = and(T_188, T_190) - node T_192 = and(T_191, io.in.valid) - when T_192 : - node T_193 = bits(io.in.bits.header, 4, 0) - infer mport T_194 = tbl[T_193], clk - when io.outs[T_194].ready : - io.in.ready <= UInt<1>("h01") - io.outs[T_194].valid <= UInt<1>("h01") - io.outs[T_194].bits <- io.in.bits - infer mport T_215 = tbl[io.in.bits.header], clk - node T_217 = eq(reset, UInt<1>("h00")) - when T_217 : - printf(clk, UInt<1>(1), "got packet to route header %d, data %d, being routed to out(%d) ", io.in.bits.header, io.in.bits.body, T_215) - skip - skip - skip - - module RouterUnitTester : - input clk : Clock - input reset : UInt<1> - output io : {} - - inst device_under_test of Router - device_under_test.io.outs[0].ready <= UInt<1>("h00") - device_under_test.io.outs[1].ready <= UInt<1>("h00") - device_under_test.io.outs[2].ready <= UInt<1>("h00") - device_under_test.io.outs[3].ready <= UInt<1>("h00") - device_under_test.io.in.bits.body <= UInt<1>("h00") - device_under_test.io.in.bits.header <= UInt<1>("h00") - device_under_test.io.in.valid <= UInt<1>("h00") - device_under_test.io.load_routing_table_request.bits.data <= UInt<1>("h00") - device_under_test.io.load_routing_table_request.bits.addr <= UInt<1>("h00") - device_under_test.io.load_routing_table_request.valid <= UInt<1>("h00") - device_under_test.io.read_routing_table_response.ready <= UInt<1>("h00") - device_under_test.io.read_routing_table_request.bits.addr <= UInt<1>("h00") - device_under_test.io.read_routing_table_request.valid <= UInt<1>("h00") - device_under_test.clk <= clk - device_under_test.reset <= reset - reg T_19 : UInt<8>, clk with : - reset => (reset, UInt<8>("h00")) - reg T_21 : UInt<1>, clk with : - reset => (reset, UInt<1>("h00")) - reg T_23 : UInt<8>, clk with : - reset => (reset, UInt<8>("h00")) - reg T_25 : UInt<1>, clk with : - reset => (reset, UInt<1>("h00")) - node T_26 = and(T_21, T_25) - when T_26 : - node T_28 = eq(reset, UInt<1>("h00")) - when T_28 : - printf(clk, UInt<1>(1), "All input and output events completed -") - skip - node T_30 = eq(reset, UInt<1>("h00")) - when T_30 : - stop(clk, UInt<1>(1), 0) - skip - skip - reg T_32 : UInt<10>, clk with : - reset => (reset, UInt<10>("h00")) - node T_34 = tail(add(T_32, UInt<1>("h01")),1) - T_32 <= T_34 - node T_36 = gt(T_32, UInt<10>("h03e8")) - when T_36 : - node T_39 = eq(reset, UInt<1>("h00")) - when T_39 : - printf(clk, UInt<1>(1), "Exceeded maximum allowed %d ticks in OrderedDecoupledHWIOTester, If you think code is correct use: -DecoupleTester.max_tick_count = <some-higher-value> -in the OrderedDecoupledHWIOTester subclass -", UInt<10>("h03e8")) - skip - node T_41 = eq(reset, UInt<1>("h00")) - when T_41 : - stop(clk, UInt<1>(1), 0) - skip - skip - wire T_97 : UInt<1>[54] - T_97[0] <= UInt<1>("h00") - T_97[1] <= UInt<1>("h00") - T_97[2] <= UInt<1>("h00") - T_97[3] <= UInt<1>("h00") - T_97[4] <= UInt<1>("h00") - T_97[5] <= UInt<1>("h00") - T_97[6] <= UInt<1>("h00") - T_97[7] <= UInt<1>("h00") - T_97[8] <= UInt<1>("h00") - T_97[9] <= UInt<1>("h00") - T_97[10] <= UInt<1>("h00") - T_97[11] <= UInt<1>("h00") - T_97[12] <= UInt<1>("h00") - T_97[13] <= UInt<1>("h01") - T_97[14] <= UInt<1>("h01") - T_97[15] <= UInt<1>("h01") - T_97[16] <= UInt<1>("h01") - T_97[17] <= UInt<1>("h00") - T_97[18] <= UInt<1>("h00") - T_97[19] <= UInt<1>("h00") - T_97[20] <= UInt<1>("h00") - T_97[21] <= UInt<1>("h00") - T_97[22] <= UInt<1>("h00") - T_97[23] <= UInt<1>("h00") - T_97[24] <= UInt<1>("h00") - T_97[25] <= UInt<1>("h00") - T_97[26] <= UInt<1>("h00") - T_97[27] <= UInt<1>("h00") - T_97[28] <= UInt<1>("h00") - T_97[29] <= UInt<1>("h00") - T_97[30] <= UInt<1>("h00") - T_97[31] <= UInt<1>("h00") - T_97[32] <= UInt<1>("h01") - T_97[33] <= UInt<1>("h01") - T_97[34] <= UInt<1>("h01") - T_97[35] <= UInt<1>("h01") - T_97[36] <= UInt<1>("h01") - T_97[37] <= UInt<1>("h01") - T_97[38] <= UInt<1>("h01") - T_97[39] <= UInt<1>("h01") - T_97[40] <= UInt<1>("h01") - T_97[41] <= UInt<1>("h01") - T_97[42] <= UInt<1>("h01") - T_97[43] <= UInt<1>("h01") - T_97[44] <= UInt<1>("h01") - T_97[45] <= UInt<1>("h01") - T_97[46] <= UInt<1>("h01") - T_97[47] <= UInt<1>("h01") - T_97[48] <= UInt<1>("h01") - T_97[49] <= UInt<1>("h01") - T_97[50] <= UInt<1>("h01") - T_97[51] <= UInt<1>("h01") - T_97[52] <= UInt<1>("h01") - T_97[53] <= UInt<1>("h00") - reg T_154 : UInt<5>, clk with : - reset => (reset, UInt<5>("h00")) - wire T_182 : UInt<4>[26] - T_182[0] <= UInt<1>("h00") - T_182[1] <= UInt<1>("h01") - T_182[2] <= UInt<2>("h02") - T_182[3] <= UInt<2>("h03") - T_182[4] <= UInt<1>("h00") - T_182[5] <= UInt<1>("h01") - T_182[6] <= UInt<2>("h02") - T_182[7] <= UInt<2>("h03") - T_182[8] <= UInt<3>("h04") - T_182[9] <= UInt<3>("h05") - T_182[10] <= UInt<3>("h06") - T_182[11] <= UInt<3>("h07") - T_182[12] <= UInt<4>("h08") - T_182[13] <= UInt<4>("h09") - T_182[14] <= UInt<4>("h0a") - T_182[15] <= UInt<4>("h0b") - T_182[16] <= UInt<4>("h0c") - T_182[17] <= UInt<4>("h0d") - T_182[18] <= UInt<4>("h0e") - T_182[19] <= UInt<1>("h00") - T_182[20] <= UInt<1>("h01") - T_182[21] <= UInt<2>("h02") - T_182[22] <= UInt<2>("h03") - T_182[23] <= UInt<3>("h04") - T_182[24] <= UInt<3>("h05") - T_182[25] <= UInt<1>("h00") - wire T_237 : UInt<31>[26] - T_237[0] <= UInt<1>("h00") - T_237[1] <= UInt<2>("h03") - T_237[2] <= UInt<3>("h06") - T_237[3] <= UInt<4>("h09") - T_237[4] <= UInt<31>("h07dcd07ac") - T_237[5] <= UInt<31>("h070890d84") - T_237[6] <= UInt<26>("h02f45883") - T_237[7] <= UInt<31>("h0787ada79") - T_237[8] <= UInt<29>("h016866878") - T_237[9] <= UInt<30>("h02331b107") - T_237[10] <= UInt<30>("h0280e4938") - T_237[11] <= UInt<29>("h0107fb3ac") - T_237[12] <= UInt<30>("h02f19d47b") - T_237[13] <= UInt<29>("h012c3d7cc") - T_237[14] <= UInt<31>("h05a432a9c") - T_237[15] <= UInt<26>("h02f9778f") - T_237[16] <= UInt<22>("h02d705a") - T_237[17] <= UInt<31>("h045fb9184") - T_237[18] <= UInt<25>("h012e47af") - T_237[19] <= UInt<31>("h07b744e21") - T_237[20] <= UInt<31>("h0480ebc3d") - T_237[21] <= UInt<28>("h0d5ff365") - T_237[22] <= UInt<30>("h0205e7973") - T_237[23] <= UInt<31>("h05004cbd2") - T_237[24] <= UInt<30>("h024988736") - T_237[25] <= UInt<1>("h00") - device_under_test.io.in.bits.header <= T_182[T_154] - device_under_test.io.in.bits.body <= T_237[T_154] - device_under_test.io.in.valid <= T_97[T_19] - node T_268 = and(device_under_test.io.in.valid, device_under_test.io.in.ready) - when T_268 : - node T_270 = eq(T_154, UInt<5>("h018")) - node T_272 = and(UInt<1>("h01"), T_270) - node T_275 = tail(add(T_154, UInt<1>("h01")),1) - node T_276 = mux(T_272, UInt<1>("h00"), T_275) - T_154 <= T_276 - node T_278 = eq(T_21, UInt<1>("h00")) - when T_278 : - node T_280 = eq(T_19, UInt<6>("h034")) - when T_280 : - T_21 <= UInt<1>("h01") - skip - node T_283 = tail(add(T_19, UInt<1>("h01")),1) - T_19 <= T_283 - skip - skip - wire T_339 : UInt<1>[54] - T_339[0] <= UInt<1>("h00") - T_339[1] <= UInt<1>("h01") - T_339[2] <= UInt<1>("h00") - T_339[3] <= UInt<1>("h01") - T_339[4] <= UInt<1>("h00") - T_339[5] <= UInt<1>("h01") - T_339[6] <= UInt<1>("h00") - T_339[7] <= UInt<1>("h01") - T_339[8] <= UInt<1>("h00") - T_339[9] <= UInt<1>("h00") - T_339[10] <= UInt<1>("h00") - T_339[11] <= UInt<1>("h00") - T_339[12] <= UInt<1>("h00") - T_339[13] <= UInt<1>("h00") - T_339[14] <= UInt<1>("h00") - T_339[15] <= UInt<1>("h00") - T_339[16] <= UInt<1>("h00") - T_339[17] <= UInt<1>("h01") - T_339[18] <= UInt<1>("h01") - T_339[19] <= UInt<1>("h01") - T_339[20] <= UInt<1>("h01") - T_339[21] <= UInt<1>("h01") - T_339[22] <= UInt<1>("h01") - T_339[23] <= UInt<1>("h01") - T_339[24] <= UInt<1>("h01") - T_339[25] <= UInt<1>("h01") - T_339[26] <= UInt<1>("h01") - T_339[27] <= UInt<1>("h01") - T_339[28] <= UInt<1>("h01") - T_339[29] <= UInt<1>("h01") - T_339[30] <= UInt<1>("h01") - T_339[31] <= UInt<1>("h01") - T_339[32] <= UInt<1>("h00") - T_339[33] <= UInt<1>("h00") - T_339[34] <= UInt<1>("h00") - T_339[35] <= UInt<1>("h00") - T_339[36] <= UInt<1>("h00") - T_339[37] <= UInt<1>("h00") - T_339[38] <= UInt<1>("h00") - T_339[39] <= UInt<1>("h00") - T_339[40] <= UInt<1>("h00") - T_339[41] <= UInt<1>("h00") - T_339[42] <= UInt<1>("h00") - T_339[43] <= UInt<1>("h00") - T_339[44] <= UInt<1>("h00") - T_339[45] <= UInt<1>("h00") - T_339[46] <= UInt<1>("h00") - T_339[47] <= UInt<1>("h00") - T_339[48] <= UInt<1>("h00") - T_339[49] <= UInt<1>("h00") - T_339[50] <= UInt<1>("h00") - T_339[51] <= UInt<1>("h00") - T_339[52] <= UInt<1>("h00") - T_339[53] <= UInt<1>("h00") - reg T_396 : UInt<5>, clk with : - reset => (reset, UInt<5>("h00")) - wire T_418 : UInt<2>[20] - T_418[0] <= UInt<1>("h01") - T_418[1] <= UInt<2>("h02") - T_418[2] <= UInt<2>("h03") - T_418[3] <= UInt<1>("h00") - T_418[4] <= UInt<2>("h02") - T_418[5] <= UInt<2>("h03") - T_418[6] <= UInt<1>("h00") - T_418[7] <= UInt<2>("h02") - T_418[8] <= UInt<2>("h02") - T_418[9] <= UInt<1>("h01") - T_418[10] <= UInt<2>("h02") - T_418[11] <= UInt<1>("h00") - T_418[12] <= UInt<2>("h02") - T_418[13] <= UInt<2>("h03") - T_418[14] <= UInt<1>("h01") - T_418[15] <= UInt<1>("h01") - T_418[16] <= UInt<1>("h01") - T_418[17] <= UInt<2>("h02") - T_418[18] <= UInt<2>("h03") - T_418[19] <= UInt<1>("h00") - wire T_461 : UInt<4>[20] - T_461[0] <= UInt<1>("h00") - T_461[1] <= UInt<1>("h01") - T_461[2] <= UInt<2>("h02") - T_461[3] <= UInt<2>("h03") - T_461[4] <= UInt<1>("h00") - T_461[5] <= UInt<1>("h01") - T_461[6] <= UInt<2>("h02") - T_461[7] <= UInt<2>("h03") - T_461[8] <= UInt<3>("h04") - T_461[9] <= UInt<3>("h05") - T_461[10] <= UInt<3>("h06") - T_461[11] <= UInt<3>("h07") - T_461[12] <= UInt<4>("h08") - T_461[13] <= UInt<4>("h09") - T_461[14] <= UInt<4>("h0a") - T_461[15] <= UInt<4>("h0b") - T_461[16] <= UInt<4>("h0c") - T_461[17] <= UInt<4>("h0d") - T_461[18] <= UInt<4>("h0e") - T_461[19] <= UInt<1>("h00") - device_under_test.io.load_routing_table_request.bits.data <= T_418[T_396] - device_under_test.io.load_routing_table_request.bits.addr <= T_461[T_396] - device_under_test.io.load_routing_table_request.valid <= T_339[T_19] - node T_486 = and(device_under_test.io.load_routing_table_request.valid, device_under_test.io.load_routing_table_request.ready) - when T_486 : - node T_488 = eq(T_396, UInt<5>("h012")) - node T_490 = and(UInt<1>("h01"), T_488) - node T_493 = tail(add(T_396, UInt<1>("h01")),1) - node T_494 = mux(T_490, UInt<1>("h00"), T_493) - T_396 <= T_494 - node T_496 = eq(T_21, UInt<1>("h00")) - when T_496 : - node T_498 = eq(T_19, UInt<6>("h034")) - when T_498 : - T_21 <= UInt<1>("h01") - skip - node T_501 = tail(add(T_19, UInt<1>("h01")),1) - T_19 <= T_501 - skip - skip - wire T_557 : UInt<1>[54] - T_557[0] <= UInt<1>("h01") - T_557[1] <= UInt<1>("h00") - T_557[2] <= UInt<1>("h01") - T_557[3] <= UInt<1>("h00") - T_557[4] <= UInt<1>("h01") - T_557[5] <= UInt<1>("h00") - T_557[6] <= UInt<1>("h01") - T_557[7] <= UInt<1>("h00") - T_557[8] <= UInt<1>("h01") - T_557[9] <= UInt<1>("h01") - T_557[10] <= UInt<1>("h01") - T_557[11] <= UInt<1>("h01") - T_557[12] <= UInt<1>("h01") - T_557[13] <= UInt<1>("h00") - T_557[14] <= UInt<1>("h00") - T_557[15] <= UInt<1>("h00") - T_557[16] <= UInt<1>("h00") - T_557[17] <= UInt<1>("h00") - T_557[18] <= UInt<1>("h00") - T_557[19] <= UInt<1>("h00") - T_557[20] <= UInt<1>("h00") - T_557[21] <= UInt<1>("h00") - T_557[22] <= UInt<1>("h00") - T_557[23] <= UInt<1>("h00") - T_557[24] <= UInt<1>("h00") - T_557[25] <= UInt<1>("h00") - T_557[26] <= UInt<1>("h00") - T_557[27] <= UInt<1>("h00") - T_557[28] <= UInt<1>("h00") - T_557[29] <= UInt<1>("h00") - T_557[30] <= UInt<1>("h00") - T_557[31] <= UInt<1>("h00") - T_557[32] <= UInt<1>("h00") - T_557[33] <= UInt<1>("h00") - T_557[34] <= UInt<1>("h00") - T_557[35] <= UInt<1>("h00") - T_557[36] <= UInt<1>("h00") - T_557[37] <= UInt<1>("h00") - T_557[38] <= UInt<1>("h00") - T_557[39] <= UInt<1>("h00") - T_557[40] <= UInt<1>("h00") - T_557[41] <= UInt<1>("h00") - T_557[42] <= UInt<1>("h00") - T_557[43] <= UInt<1>("h00") - T_557[44] <= UInt<1>("h00") - T_557[45] <= UInt<1>("h00") - T_557[46] <= UInt<1>("h00") - T_557[47] <= UInt<1>("h00") - T_557[48] <= UInt<1>("h00") - T_557[49] <= UInt<1>("h00") - T_557[50] <= UInt<1>("h00") - T_557[51] <= UInt<1>("h00") - T_557[52] <= UInt<1>("h00") - T_557[53] <= UInt<1>("h00") - reg T_614 : UInt<4>, clk with : - reset => (reset, UInt<4>("h00")) - wire T_626 : UInt<2>[10] - T_626[0] <= UInt<1>("h00") - T_626[1] <= UInt<1>("h00") - T_626[2] <= UInt<1>("h01") - T_626[3] <= UInt<2>("h02") - T_626[4] <= UInt<2>("h03") - T_626[5] <= UInt<2>("h03") - T_626[6] <= UInt<2>("h02") - T_626[7] <= UInt<1>("h01") - T_626[8] <= UInt<1>("h00") - T_626[9] <= UInt<1>("h00") - device_under_test.io.read_routing_table_request.bits.addr <= T_626[T_614] - device_under_test.io.read_routing_table_request.valid <= T_557[T_19] - node T_640 = and(device_under_test.io.read_routing_table_request.valid, device_under_test.io.read_routing_table_request.ready) - when T_640 : - node T_642 = eq(T_614, UInt<4>("h08")) - node T_644 = and(UInt<1>("h01"), T_642) - node T_647 = tail(add(T_614, UInt<1>("h01")),1) - node T_648 = mux(T_644, UInt<1>("h00"), T_647) - T_614 <= T_648 - node T_650 = eq(T_21, UInt<1>("h00")) - when T_650 : - node T_652 = eq(T_19, UInt<6>("h034")) - when T_652 : - T_21 <= UInt<1>("h01") - skip - node T_655 = tail(add(T_19, UInt<1>("h01")),1) - T_19 <= T_655 - skip - skip - wire T_711 : UInt<1>[54] - T_711[0] <= UInt<1>("h00") - T_711[1] <= UInt<1>("h00") - T_711[2] <= UInt<1>("h00") - T_711[3] <= UInt<1>("h00") - T_711[4] <= UInt<1>("h00") - T_711[5] <= UInt<1>("h00") - T_711[6] <= UInt<1>("h00") - T_711[7] <= UInt<1>("h00") - T_711[8] <= UInt<1>("h00") - T_711[9] <= UInt<1>("h00") - T_711[10] <= UInt<1>("h00") - T_711[11] <= UInt<1>("h00") - T_711[12] <= UInt<1>("h01") - T_711[13] <= UInt<1>("h00") - T_711[14] <= UInt<1>("h00") - T_711[15] <= UInt<1>("h01") - T_711[16] <= UInt<1>("h00") - T_711[17] <= UInt<1>("h00") - T_711[18] <= UInt<1>("h00") - T_711[19] <= UInt<1>("h00") - T_711[20] <= UInt<1>("h01") - T_711[21] <= UInt<1>("h00") - T_711[22] <= UInt<1>("h00") - T_711[23] <= UInt<1>("h00") - T_711[24] <= UInt<1>("h00") - T_711[25] <= UInt<1>("h00") - T_711[26] <= UInt<1>("h00") - T_711[27] <= UInt<1>("h00") - T_711[28] <= UInt<1>("h00") - T_711[29] <= UInt<1>("h00") - T_711[30] <= UInt<1>("h01") - T_711[31] <= UInt<1>("h00") - T_711[32] <= UInt<1>("h00") - T_711[33] <= UInt<1>("h00") - T_711[34] <= UInt<1>("h00") - T_711[35] <= UInt<1>("h00") - T_711[36] <= UInt<1>("h00") - T_711[37] <= UInt<1>("h00") - T_711[38] <= UInt<1>("h00") - T_711[39] <= UInt<1>("h00") - T_711[40] <= UInt<1>("h00") - T_711[41] <= UInt<1>("h00") - T_711[42] <= UInt<1>("h00") - T_711[43] <= UInt<1>("h00") - T_711[44] <= UInt<1>("h00") - T_711[45] <= UInt<1>("h00") - T_711[46] <= UInt<1>("h00") - T_711[47] <= UInt<1>("h00") - T_711[48] <= UInt<1>("h00") - T_711[49] <= UInt<1>("h00") - T_711[50] <= UInt<1>("h00") - T_711[51] <= UInt<1>("h00") - T_711[52] <= UInt<1>("h00") - T_711[53] <= UInt<1>("h00") - reg T_768 : UInt<6>, clk with : - reset => (reset, UInt<6>("h00")) - wire T_775 : UInt<29>[5] - T_775[0] <= UInt<4>("h09") - T_775[1] <= UInt<26>("h02f45883") - T_775[2] <= UInt<29>("h0107fb3ac") - T_775[3] <= UInt<28>("h0d5ff365") - T_775[4] <= UInt<1>("h00") - device_under_test.io.outs[0].ready <= T_711[T_23] - node T_783 = and(device_under_test.io.outs[0].ready, device_under_test.io.outs[0].valid) - when T_783 : - node T_786 = eq(reset, UInt<1>("h00")) - when T_786 : - printf(clk, UInt<1>(1), "output test event %d testing outs(0).bits.body = %d, should be %d -", T_23, device_under_test.io.outs[0].bits.body, T_775[T_768]) - skip - node T_788 = neq(device_under_test.io.outs[0].bits.body, T_775[T_768]) - when T_788 : - node T_791 = eq(reset, UInt<1>("h00")) - when T_791 : - printf(clk, UInt<1>(1), "Error: event %d outs(0).bits.body was %d should be %d -", T_23, device_under_test.io.outs[0].bits.body, T_775[T_768]) - skip - node T_794 = eq(reset, UInt<1>("h00")) - when T_794 : - node T_796 = eq(UInt<1>("h00"), UInt<1>("h00")) - when T_796 : - node T_798 = eq(reset, UInt<1>("h00")) - when T_798 : - printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno)") - skip - stop(clk, UInt<1>(1), 1) - skip - skip - node T_800 = eq(reset, UInt<1>("h00")) - when T_800 : - stop(clk, UInt<1>(1), 0) - skip - skip - node T_802 = eq(T_768, UInt<6>("h021")) - node T_804 = and(UInt<1>("h01"), T_802) - node T_807 = tail(add(T_768, UInt<1>("h01")),1) - node T_808 = mux(T_804, UInt<1>("h00"), T_807) - T_768 <= T_808 - node T_810 = eq(T_25, UInt<1>("h00")) - when T_810 : - node T_812 = eq(T_23, UInt<6>("h021")) - when T_812 : - T_25 <= UInt<1>("h01") - skip - node T_815 = tail(add(T_23, UInt<1>("h01")),1) - T_23 <= T_815 - skip - skip - wire T_871 : UInt<1>[54] - T_871[0] <= UInt<1>("h00") - T_871[1] <= UInt<1>("h00") - T_871[2] <= UInt<1>("h00") - T_871[3] <= UInt<1>("h00") - T_871[4] <= UInt<1>("h00") - T_871[5] <= UInt<1>("h00") - T_871[6] <= UInt<1>("h00") - T_871[7] <= UInt<1>("h00") - T_871[8] <= UInt<1>("h00") - T_871[9] <= UInt<1>("h00") - T_871[10] <= UInt<1>("h00") - T_871[11] <= UInt<1>("h01") - T_871[12] <= UInt<1>("h00") - T_871[13] <= UInt<1>("h00") - T_871[14] <= UInt<1>("h01") - T_871[15] <= UInt<1>("h00") - T_871[16] <= UInt<1>("h00") - T_871[17] <= UInt<1>("h00") - T_871[18] <= UInt<1>("h00") - T_871[19] <= UInt<1>("h00") - T_871[20] <= UInt<1>("h00") - T_871[21] <= UInt<1>("h00") - T_871[22] <= UInt<1>("h01") - T_871[23] <= UInt<1>("h00") - T_871[24] <= UInt<1>("h00") - T_871[25] <= UInt<1>("h00") - T_871[26] <= UInt<1>("h00") - T_871[27] <= UInt<1>("h01") - T_871[28] <= UInt<1>("h00") - T_871[29] <= UInt<1>("h01") - T_871[30] <= UInt<1>("h00") - T_871[31] <= UInt<1>("h00") - T_871[32] <= UInt<1>("h00") - T_871[33] <= UInt<1>("h00") - T_871[34] <= UInt<1>("h00") - T_871[35] <= UInt<1>("h00") - T_871[36] <= UInt<1>("h00") - T_871[37] <= UInt<1>("h00") - T_871[38] <= UInt<1>("h00") - T_871[39] <= UInt<1>("h00") - T_871[40] <= UInt<1>("h00") - T_871[41] <= UInt<1>("h00") - T_871[42] <= UInt<1>("h00") - T_871[43] <= UInt<1>("h00") - T_871[44] <= UInt<1>("h00") - T_871[45] <= UInt<1>("h00") - T_871[46] <= UInt<1>("h00") - T_871[47] <= UInt<1>("h00") - T_871[48] <= UInt<1>("h00") - T_871[49] <= UInt<1>("h00") - T_871[50] <= UInt<1>("h00") - T_871[51] <= UInt<1>("h00") - T_871[52] <= UInt<1>("h00") - T_871[53] <= UInt<1>("h00") - reg T_928 : UInt<6>, clk with : - reset => (reset, UInt<6>("h00")) - wire T_936 : UInt<31>[6] - T_936[0] <= UInt<3>("h06") - T_936[1] <= UInt<31>("h070890d84") - T_936[2] <= UInt<29>("h012c3d7cc") - T_936[3] <= UInt<25>("h012e47af") - T_936[4] <= UInt<31>("h0480ebc3d") - T_936[5] <= UInt<1>("h00") - device_under_test.io.outs[3].ready <= T_871[T_23] - node T_945 = and(device_under_test.io.outs[3].ready, device_under_test.io.outs[3].valid) - when T_945 : - node T_948 = eq(reset, UInt<1>("h00")) - when T_948 : - printf(clk, UInt<1>(1), "output test event %d testing outs(3).bits.body = %d, should be %d -", T_23, device_under_test.io.outs[3].bits.body, T_936[T_928]) - skip - node T_950 = neq(device_under_test.io.outs[3].bits.body, T_936[T_928]) - when T_950 : - node T_953 = eq(reset, UInt<1>("h00")) - when T_953 : - printf(clk, UInt<1>(1), "Error: event %d outs(3).bits.body was %d should be %d -", T_23, device_under_test.io.outs[3].bits.body, T_936[T_928]) - skip - node T_956 = eq(reset, UInt<1>("h00")) - when T_956 : - node T_958 = eq(UInt<1>("h00"), UInt<1>("h00")) - when T_958 : - node T_960 = eq(reset, UInt<1>("h00")) - when T_960 : - printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno)") - skip - stop(clk, UInt<1>(1), 1) - skip - skip - node T_962 = eq(reset, UInt<1>("h00")) - when T_962 : - stop(clk, UInt<1>(1), 0) - skip - skip - node T_964 = eq(T_928, UInt<6>("h021")) - node T_966 = and(UInt<1>("h01"), T_964) - node T_969 = tail(add(T_928, UInt<1>("h01")),1) - node T_970 = mux(T_966, UInt<1>("h00"), T_969) - T_928 <= T_970 - node T_972 = eq(T_25, UInt<1>("h00")) - when T_972 : - node T_974 = eq(T_23, UInt<6>("h021")) - when T_974 : - T_25 <= UInt<1>("h01") - skip - node T_977 = tail(add(T_23, UInt<1>("h01")),1) - T_23 <= T_977 - skip - skip - wire T_1033 : UInt<1>[54] - T_1033[0] <= UInt<1>("h00") - T_1033[1] <= UInt<1>("h00") - T_1033[2] <= UInt<1>("h00") - T_1033[3] <= UInt<1>("h00") - T_1033[4] <= UInt<1>("h00") - T_1033[5] <= UInt<1>("h00") - T_1033[6] <= UInt<1>("h00") - T_1033[7] <= UInt<1>("h00") - T_1033[8] <= UInt<1>("h00") - T_1033[9] <= UInt<1>("h01") - T_1033[10] <= UInt<1>("h00") - T_1033[11] <= UInt<1>("h00") - T_1033[12] <= UInt<1>("h00") - T_1033[13] <= UInt<1>("h00") - T_1033[14] <= UInt<1>("h00") - T_1033[15] <= UInt<1>("h00") - T_1033[16] <= UInt<1>("h00") - T_1033[17] <= UInt<1>("h00") - T_1033[18] <= UInt<1>("h01") - T_1033[19] <= UInt<1>("h00") - T_1033[20] <= UInt<1>("h00") - T_1033[21] <= UInt<1>("h00") - T_1033[22] <= UInt<1>("h00") - T_1033[23] <= UInt<1>("h01") - T_1033[24] <= UInt<1>("h01") - T_1033[25] <= UInt<1>("h01") - T_1033[26] <= UInt<1>("h00") - T_1033[27] <= UInt<1>("h00") - T_1033[28] <= UInt<1>("h00") - T_1033[29] <= UInt<1>("h00") - T_1033[30] <= UInt<1>("h00") - T_1033[31] <= UInt<1>("h00") - T_1033[32] <= UInt<1>("h00") - T_1033[33] <= UInt<1>("h01") - T_1033[34] <= UInt<1>("h00") - T_1033[35] <= UInt<1>("h00") - T_1033[36] <= UInt<1>("h00") - T_1033[37] <= UInt<1>("h00") - T_1033[38] <= UInt<1>("h00") - T_1033[39] <= UInt<1>("h00") - T_1033[40] <= UInt<1>("h00") - T_1033[41] <= UInt<1>("h00") - T_1033[42] <= UInt<1>("h00") - T_1033[43] <= UInt<1>("h00") - T_1033[44] <= UInt<1>("h00") - T_1033[45] <= UInt<1>("h00") - T_1033[46] <= UInt<1>("h00") - T_1033[47] <= UInt<1>("h00") - T_1033[48] <= UInt<1>("h00") - T_1033[49] <= UInt<1>("h00") - T_1033[50] <= UInt<1>("h00") - T_1033[51] <= UInt<1>("h00") - T_1033[52] <= UInt<1>("h00") - T_1033[53] <= UInt<1>("h00") - reg T_1090 : UInt<6>, clk with : - reset => (reset, UInt<6>("h00")) - wire T_1099 : UInt<31>[7] - T_1099[0] <= UInt<1>("h00") - T_1099[1] <= UInt<30>("h02331b107") - T_1099[2] <= UInt<31>("h05a432a9c") - T_1099[3] <= UInt<26>("h02f9778f") - T_1099[4] <= UInt<22>("h02d705a") - T_1099[5] <= UInt<30>("h024988736") - T_1099[6] <= UInt<1>("h00") - device_under_test.io.outs[1].ready <= T_1033[T_23] - node T_1109 = and(device_under_test.io.outs[1].ready, device_under_test.io.outs[1].valid) - when T_1109 : - node T_1112 = eq(reset, UInt<1>("h00")) - when T_1112 : - printf(clk, UInt<1>(1), "output test event %d testing outs(1).bits.body = %d, should be %d -", T_23, device_under_test.io.outs[1].bits.body, T_1099[T_1090]) - skip - node T_1114 = neq(device_under_test.io.outs[1].bits.body, T_1099[T_1090]) - when T_1114 : - node T_1117 = eq(reset, UInt<1>("h00")) - when T_1117 : - printf(clk, UInt<1>(1), "Error: event %d outs(1).bits.body was %d should be %d -", T_23, device_under_test.io.outs[1].bits.body, T_1099[T_1090]) - skip - node T_1120 = eq(reset, UInt<1>("h00")) - when T_1120 : - node T_1122 = eq(UInt<1>("h00"), UInt<1>("h00")) - when T_1122 : - node T_1124 = eq(reset, UInt<1>("h00")) - when T_1124 : - printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno)") - skip - stop(clk, UInt<1>(1), 1) - skip - skip - node T_1126 = eq(reset, UInt<1>("h00")) - when T_1126 : - stop(clk, UInt<1>(1), 0) - skip - skip - node T_1128 = eq(T_1090, UInt<6>("h021")) - node T_1130 = and(UInt<1>("h01"), T_1128) - node T_1133 = tail(add(T_1090, UInt<1>("h01")),1) - node T_1134 = mux(T_1130, UInt<1>("h00"), T_1133) - T_1090 <= T_1134 - node T_1136 = eq(T_25, UInt<1>("h00")) - when T_1136 : - node T_1138 = eq(T_23, UInt<6>("h021")) - when T_1138 : - T_25 <= UInt<1>("h01") - skip - node T_1141 = tail(add(T_23, UInt<1>("h01")),1) - T_23 <= T_1141 - skip - skip - wire T_1197 : UInt<1>[54] - T_1197[0] <= UInt<1>("h00") - T_1197[1] <= UInt<1>("h00") - T_1197[2] <= UInt<1>("h00") - T_1197[3] <= UInt<1>("h00") - T_1197[4] <= UInt<1>("h00") - T_1197[5] <= UInt<1>("h00") - T_1197[6] <= UInt<1>("h00") - T_1197[7] <= UInt<1>("h00") - T_1197[8] <= UInt<1>("h00") - T_1197[9] <= UInt<1>("h00") - T_1197[10] <= UInt<1>("h01") - T_1197[11] <= UInt<1>("h00") - T_1197[12] <= UInt<1>("h00") - T_1197[13] <= UInt<1>("h01") - T_1197[14] <= UInt<1>("h00") - T_1197[15] <= UInt<1>("h00") - T_1197[16] <= UInt<1>("h01") - T_1197[17] <= UInt<1>("h01") - T_1197[18] <= UInt<1>("h00") - T_1197[19] <= UInt<1>("h01") - T_1197[20] <= UInt<1>("h00") - T_1197[21] <= UInt<1>("h01") - T_1197[22] <= UInt<1>("h00") - T_1197[23] <= UInt<1>("h00") - T_1197[24] <= UInt<1>("h00") - T_1197[25] <= UInt<1>("h00") - T_1197[26] <= UInt<1>("h01") - T_1197[27] <= UInt<1>("h00") - T_1197[28] <= UInt<1>("h01") - T_1197[29] <= UInt<1>("h00") - T_1197[30] <= UInt<1>("h00") - T_1197[31] <= UInt<1>("h01") - T_1197[32] <= UInt<1>("h01") - T_1197[33] <= UInt<1>("h00") - T_1197[34] <= UInt<1>("h00") - T_1197[35] <= UInt<1>("h00") - T_1197[36] <= UInt<1>("h00") - T_1197[37] <= UInt<1>("h00") - T_1197[38] <= UInt<1>("h00") - T_1197[39] <= UInt<1>("h00") - T_1197[40] <= UInt<1>("h00") - T_1197[41] <= UInt<1>("h00") - T_1197[42] <= UInt<1>("h00") - T_1197[43] <= UInt<1>("h00") - T_1197[44] <= UInt<1>("h00") - T_1197[45] <= UInt<1>("h00") - T_1197[46] <= UInt<1>("h00") - T_1197[47] <= UInt<1>("h00") - T_1197[48] <= UInt<1>("h00") - T_1197[49] <= UInt<1>("h00") - T_1197[50] <= UInt<1>("h00") - T_1197[51] <= UInt<1>("h00") - T_1197[52] <= UInt<1>("h00") - T_1197[53] <= UInt<1>("h00") - reg T_1254 : UInt<6>, clk with : - reset => (reset, UInt<6>("h00")) - wire T_1267 : UInt<31>[11] - T_1267[0] <= UInt<2>("h03") - T_1267[1] <= UInt<31>("h07dcd07ac") - T_1267[2] <= UInt<31>("h0787ada79") - T_1267[3] <= UInt<29>("h016866878") - T_1267[4] <= UInt<30>("h0280e4938") - T_1267[5] <= UInt<30>("h02f19d47b") - T_1267[6] <= UInt<31>("h045fb9184") - T_1267[7] <= UInt<31>("h07b744e21") - T_1267[8] <= UInt<30>("h0205e7973") - T_1267[9] <= UInt<31>("h05004cbd2") - T_1267[10] <= UInt<1>("h00") - device_under_test.io.outs[2].ready <= T_1197[T_23] - node T_1281 = and(device_under_test.io.outs[2].ready, device_under_test.io.outs[2].valid) - when T_1281 : - node T_1284 = eq(reset, UInt<1>("h00")) - when T_1284 : - printf(clk, UInt<1>(1), "output test event %d testing outs(2).bits.body = %d, should be %d -", T_23, device_under_test.io.outs[2].bits.body, T_1267[T_1254]) - skip - node T_1286 = neq(device_under_test.io.outs[2].bits.body, T_1267[T_1254]) - when T_1286 : - node T_1289 = eq(reset, UInt<1>("h00")) - when T_1289 : - printf(clk, UInt<1>(1), "Error: event %d outs(2).bits.body was %d should be %d -", T_23, device_under_test.io.outs[2].bits.body, T_1267[T_1254]) - skip - node T_1292 = eq(reset, UInt<1>("h00")) - when T_1292 : - node T_1294 = eq(UInt<1>("h00"), UInt<1>("h00")) - when T_1294 : - node T_1296 = eq(reset, UInt<1>("h00")) - when T_1296 : - printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno)") - skip - stop(clk, UInt<1>(1), 1) - skip - skip - node T_1298 = eq(reset, UInt<1>("h00")) - when T_1298 : - stop(clk, UInt<1>(1), 0) - skip - skip - node T_1300 = eq(T_1254, UInt<6>("h021")) - node T_1302 = and(UInt<1>("h01"), T_1300) - node T_1305 = tail(add(T_1254, UInt<1>("h01")),1) - node T_1306 = mux(T_1302, UInt<1>("h00"), T_1305) - T_1254 <= T_1306 - node T_1308 = eq(T_25, UInt<1>("h00")) - when T_1308 : - node T_1310 = eq(T_23, UInt<6>("h021")) - when T_1310 : - T_25 <= UInt<1>("h01") - skip - node T_1313 = tail(add(T_23, UInt<1>("h01")),1) - T_23 <= T_1313 - skip - skip - wire T_1369 : UInt<1>[54] - T_1369[0] <= UInt<1>("h01") - T_1369[1] <= UInt<1>("h01") - T_1369[2] <= UInt<1>("h01") - T_1369[3] <= UInt<1>("h01") - T_1369[4] <= UInt<1>("h01") - T_1369[5] <= UInt<1>("h01") - T_1369[6] <= UInt<1>("h01") - T_1369[7] <= UInt<1>("h01") - T_1369[8] <= UInt<1>("h01") - T_1369[9] <= UInt<1>("h00") - T_1369[10] <= UInt<1>("h00") - T_1369[11] <= UInt<1>("h00") - T_1369[12] <= UInt<1>("h00") - T_1369[13] <= UInt<1>("h00") - T_1369[14] <= UInt<1>("h00") - T_1369[15] <= UInt<1>("h00") - T_1369[16] <= UInt<1>("h00") - T_1369[17] <= UInt<1>("h00") - T_1369[18] <= UInt<1>("h00") - T_1369[19] <= UInt<1>("h00") - T_1369[20] <= UInt<1>("h00") - T_1369[21] <= UInt<1>("h00") - T_1369[22] <= UInt<1>("h00") - T_1369[23] <= UInt<1>("h00") - T_1369[24] <= UInt<1>("h00") - T_1369[25] <= UInt<1>("h00") - T_1369[26] <= UInt<1>("h00") - T_1369[27] <= UInt<1>("h00") - T_1369[28] <= UInt<1>("h00") - T_1369[29] <= UInt<1>("h00") - T_1369[30] <= UInt<1>("h00") - T_1369[31] <= UInt<1>("h00") - T_1369[32] <= UInt<1>("h00") - T_1369[33] <= UInt<1>("h00") - T_1369[34] <= UInt<1>("h00") - T_1369[35] <= UInt<1>("h00") - T_1369[36] <= UInt<1>("h00") - T_1369[37] <= UInt<1>("h00") - T_1369[38] <= UInt<1>("h00") - T_1369[39] <= UInt<1>("h00") - T_1369[40] <= UInt<1>("h00") - T_1369[41] <= UInt<1>("h00") - T_1369[42] <= UInt<1>("h00") - T_1369[43] <= UInt<1>("h00") - T_1369[44] <= UInt<1>("h00") - T_1369[45] <= UInt<1>("h00") - T_1369[46] <= UInt<1>("h00") - T_1369[47] <= UInt<1>("h00") - T_1369[48] <= UInt<1>("h00") - T_1369[49] <= UInt<1>("h00") - T_1369[50] <= UInt<1>("h00") - T_1369[51] <= UInt<1>("h00") - T_1369[52] <= UInt<1>("h00") - T_1369[53] <= UInt<1>("h00") - reg T_1426 : UInt<6>, clk with : - reset => (reset, UInt<6>("h00")) - wire T_1438 : UInt<2>[10] - T_1438[0] <= UInt<1>("h00") - T_1438[1] <= UInt<1>("h01") - T_1438[2] <= UInt<2>("h02") - T_1438[3] <= UInt<2>("h03") - T_1438[4] <= UInt<1>("h00") - T_1438[5] <= UInt<1>("h00") - T_1438[6] <= UInt<2>("h03") - T_1438[7] <= UInt<2>("h02") - T_1438[8] <= UInt<1>("h01") - T_1438[9] <= UInt<1>("h00") - device_under_test.io.read_routing_table_response.ready <= T_1369[T_23] - node T_1451 = and(device_under_test.io.read_routing_table_response.ready, device_under_test.io.read_routing_table_response.valid) - when T_1451 : - node T_1454 = eq(reset, UInt<1>("h00")) - when T_1454 : - printf(clk, UInt<1>(1), "output test event %d testing read_routing_table_response.bits = %d, should be %d -", T_23, device_under_test.io.read_routing_table_response.bits, T_1438[T_1426]) - skip - node T_1456 = neq(device_under_test.io.read_routing_table_response.bits, T_1438[T_1426]) - when T_1456 : - node T_1459 = eq(reset, UInt<1>("h00")) - when T_1459 : - printf(clk, UInt<1>(1), "Error: event %d read_routing_table_response.bits was %d should be %d -", T_23, device_under_test.io.read_routing_table_response.bits, T_1438[T_1426]) - skip - node T_1462 = eq(reset, UInt<1>("h00")) - when T_1462 : - node T_1464 = eq(UInt<1>("h00"), UInt<1>("h00")) - when T_1464 : - node T_1466 = eq(reset, UInt<1>("h00")) - when T_1466 : - printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno)") - skip - stop(clk, UInt<1>(1), 1) - skip - skip - node T_1468 = eq(reset, UInt<1>("h00")) - when T_1468 : - stop(clk, UInt<1>(1), 0) - skip - skip - node T_1470 = eq(T_1426, UInt<6>("h021")) - node T_1472 = and(UInt<1>("h01"), T_1470) - node T_1475 = tail(add(T_1426, UInt<1>("h01")),1) - node T_1476 = mux(T_1472, UInt<1>("h00"), T_1475) - T_1426 <= T_1476 - node T_1478 = eq(T_25, UInt<1>("h00")) - when T_1478 : - node T_1480 = eq(T_23, UInt<6>("h021")) - when T_1480 : - T_25 <= UInt<1>("h01") - skip - node T_1483 = tail(add(T_23, UInt<1>("h01")),1) - T_23 <= T_1483 - skip - skip - node T_1485 = eq(reset, UInt<1>("h00")) - when T_1485 : - printf(clk, UInt<1>(1), "in_event_counter %d, out_event_counter %d -", T_19, T_23) - skip - - - diff --git a/test/passes/jacktest/Stack.fir b/test/passes/jacktest/Stack.fir deleted file mode 100644 index 3eb9c67c..00000000 --- a/test/passes/jacktest/Stack.fir +++ /dev/null @@ -1,37 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p cT 2>&1 | tee %s.out | FileCheck %s -;CHECK: Done! -circuit Stack : - module Stack : - input push : UInt<1> - input pop : UInt<1> - input en : UInt<1> - input clk : Clock - input reset : UInt<1> - output dataOut : UInt<32> - input dataIn : UInt<32> - - cmem stack_mem : UInt<32>[16] - reg sp : UInt<5>,clk with : - reset => (reset,UInt<5>(0)) - reg out : UInt<32>,clk with : - reset => (reset,UInt<32>(0)) - when en : - node T_30 = lt(sp, UInt<5>(16)) - node T_31 = and(push, T_30) - when T_31 : - write mport T_32 = stack_mem[sp],clk - T_32 <= dataIn - node T_33 = tail(add(sp, UInt<1>(1)),1) - sp <= T_33 - else : - node T_34 = gt(sp, UInt<1>(0)) - node T_35 = and(pop, T_34) - when T_35 : - node T_36 = tail(sub(sp, UInt<1>(1)),1) - sp <= T_36 - node T_37 = gt(sp, UInt<1>(0)) - when T_37 : - node T_38 = tail(sub(sp, UInt<1>(1)),1) - read mport T_39 = stack_mem[T_38],clk - out <= T_39 - dataOut <= out diff --git a/test/passes/jacktest/Tbl.fir b/test/passes/jacktest/Tbl.fir deleted file mode 100644 index 5feb71bb..00000000 --- a/test/passes/jacktest/Tbl.fir +++ /dev/null @@ -1,21 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: Done! - -circuit Tbl : - module Tbl : - input clk : Clock - input reset : UInt<1> - output io : {flip wi : UInt<3>, flip ri : UInt<3>, flip we : UInt<1>, flip d : UInt<3>, o : UInt<3>} - - io.o <= UInt<1>("h00") - cmem m : UInt<3>[8] - infer mport T_12 = m[io.ri], clk - io.o <= T_12 - when io.we : - infer mport T_13 = m[io.wi], clk - T_13 <= io.d - node T_14 = eq(io.ri, io.wi) - when T_14 : - io.o <= io.d - skip - skip diff --git a/test/passes/jacktest/VendingMachine.fir b/test/passes/jacktest/VendingMachine.fir deleted file mode 100644 index d7822a17..00000000 --- a/test/passes/jacktest/VendingMachine.fir +++ /dev/null @@ -1,32 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: Done! -circuit VendingMachine : - module VendingMachine : - output valid : UInt<1> - input nickel : UInt<1> - input dime : UInt<1> - input clk : Clock - input reset : UInt<1> - - reg state : UInt<3>,clk with : - reset => (reset,UInt<3>(0)) - node T_22 = eq(state, UInt<3>(0)) - when T_22 : - when nickel : state <= UInt<3>(1) - when dime : state <= UInt<3>(2) - node T_23 = eq(state, UInt<3>(1)) - when T_23 : - when nickel : state <= UInt<3>(2) - when dime : state <= UInt<3>(3) - node T_24 = eq(state, UInt<3>(2)) - when T_24 : - when nickel : state <= UInt<3>(3) - when dime : state <= UInt<3>(4) - node T_25 = eq(state, UInt<3>(3)) - when T_25 : - when nickel : state <= UInt<3>(4) - when dime : state <= UInt<3>(4) - node T_26 = eq(state, UInt<3>(4)) - when T_26 : state <= UInt<3>(0) - node T_27 = eq(state, UInt<3>(4)) - valid <= T_27 diff --git a/test/passes/jacktest/gcd.fir b/test/passes/jacktest/gcd.fir deleted file mode 100644 index 31ca30b2..00000000 --- a/test/passes/jacktest/gcd.fir +++ /dev/null @@ -1,29 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: Done! -circuit GCD : - module GCD : - input e : UInt<1> - input clk : Clock - input reset : UInt<1> - output z : UInt<16> - output v : UInt<1> - input a : UInt<16> - input b : UInt<16> - - reg x : UInt<16>,clk with : - reset => (reset,x) - reg y : UInt<16>,clk with : - reset => (reset,y) - node T_17 = gt(x, y) - when T_17 : - node T_18 = tail(sub(x, y),1) - x <= T_18 - else : - node T_19 = tail(sub(y, x),1) - y <= T_19 - when e : - x <= a - y <= b - z <= x - node T_20 = eq(y, UInt<1>(0)) - v <= T_20 diff --git a/test/passes/jacktest/risc.fir b/test/passes/jacktest/risc.fir deleted file mode 100644 index f722cf97..00000000 --- a/test/passes/jacktest/risc.fir +++ /dev/null @@ -1,54 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p cT 2>&1 | tee %s.out | FileCheck %s -; CHECK: Done! -circuit Risc : - module Risc : - output out : UInt<32> - output valid : UInt<1> - input boot : UInt<1> - input isWr : UInt<1> - input wrAddr : UInt<8> - input wrData : UInt<32> - input clk : Clock - input reset : UInt<1> - - cmem file : UInt<32>[256] - cmem code : UInt<32>[256] - reg pc : UInt<8>,clk with : - reset => (reset,UInt<8>(0)) - read mport inst = code[pc],clk - node op = bits(inst, 31, 24) - node rci = bits(inst, 23, 16) - node rai = bits(inst, 15, 8) - node rbi = bits(inst, 7, 0) - node T_51 = eq(rai, UInt<1>(0)) - read mport T_52 = file[rai],clk - node ra = mux(T_51, UInt<1>(0), T_52) - node T_53 = eq(rbi, UInt<1>(0)) - read mport T_54 = file[rbi],clk - node rb = mux(T_53, UInt<1>(0), T_54) - wire rc : UInt<32> - valid <= UInt<1>(0) - out <= UInt<1>(0) - rc <= UInt<1>(0) - when isWr : - write mport T_55 = code[wrAddr],clk - T_55 <= wrData - else : when boot : pc <= UInt<1>(0) - else : - node T_56 = eq(UInt<1>(0), op) - when T_56 : - node T_57 = tail(add(ra, rb),1) - rc <= T_57 - node T_58 = eq(UInt<1>(1), op) - when T_58 : - node T_59 = shl(rai, 8) - node T_60 = or(T_59, rbi) - rc <= T_60 - out <= rc - node T_61 = eq(rci, UInt<8>(255)) - when T_61 : valid <= UInt<1>(1) - else : - write mport T_62 = file[rci],clk - T_62 <= rc - node T_63 = tail(add(pc, UInt<1>(1)),1) - pc <= T_63 diff --git a/test/passes/lower-to-ground/bundle-vecs.fir b/test/passes/lower-to-ground/bundle-vecs.fir deleted file mode 100644 index d6af7a82..00000000 --- a/test/passes/lower-to-ground/bundle-vecs.fir +++ /dev/null @@ -1,38 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s - -; CHECK: Lower Types -circuit top : - module top : - input i : UInt<1> - wire j : { x : UInt<32>, flip y : UInt<32> } - - wire a : { x : UInt<32>, flip y : UInt<32> }[2] - ; CHECK: wire a{{[_$]+}}0{{[_$]+}}x : UInt<32> - ; CHECK: wire a{{[_$]+}}0{{[_$]+}}y : UInt<32> - ; CHECK: wire a{{[_$]+}}1{{[_$]+}}x : UInt<32> - ; CHECK: wire a{{[_$]+}}1{{[_$]+}}y : UInt<32> - a[0].x <= UInt(0) - a[0].y <= UInt(0) - a[1].x <= UInt(0) - a[1].y <= UInt(0) - - j <= a[i] - a[i] <= j - -; CHECK: wire GEN_0 : UInt<32> -; CHECK: wire GEN_1 : UInt<32> -; CHECK: wire GEN_2 : UInt<32> -; CHECK: wire GEN_3 : UInt<32> -; CHECK: j_x <= GEN_0 -; CHECK: j_y <= GEN_3 -; CHECK: a_0_x <= mux(eq(UInt<1>("h0"), i), GEN_2, UInt<1>("h0")) -; CHECK: a_0_y <= mux(eq(UInt<1>("h0"), i), GEN_1, UInt<1>("h0")) -; CHECK: a_1_x <= mux(eq(UInt<1>("h1"), i), GEN_2, UInt<1>("h0")) -; CHECK: a_1_y <= mux(eq(UInt<1>("h1"), i), GEN_1, UInt<1>("h0")) -; CHECK: GEN_0 <= mux(eq(UInt<1>("h1"), i), a_1_x, a_0_x) -; CHECK: GEN_1 <= j_y -; CHECK: GEN_2 <= j_x -; CHECK: GEN_3 <= mux(eq(UInt<1>("h1"), i), a_1_y, a_0_y) - -; CHECK: Finished Lower Types - diff --git a/test/passes/lower-to-ground/bundle.fir b/test/passes/lower-to-ground/bundle.fir deleted file mode 100644 index a8f8ad78..00000000 --- a/test/passes/lower-to-ground/bundle.fir +++ /dev/null @@ -1,60 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p cd 2>&1 | tee %s.out | FileCheck %s - -circuit top : - module m : - input a : { x : UInt<5>, flip y: SInt<5>} - output b : { x : UInt<5>, flip y: SInt<5>} - a.y <= SInt(0) - b.x <= UInt(0) - module top : - input c : { x : UInt<5>[5], flip y : { x : UInt<5>[3], flip y : SInt<5> } } - wire a : { x : UInt<5>, flip y : SInt<5>} - wire b : { x : UInt<5>, flip y : SInt<5>} - a <= b - inst i of m - i.a <= a - b <= i.b - wire d : UInt<5>[5] - d[0] <= UInt(0) - d[1] <= UInt(0) - d[2] <= UInt(0) - d[3] <= UInt(0) - d[4] <= UInt(0) - c.y.x[0] <= UInt(0) - c.y.x[1] <= UInt(0) - c.y.x[2] <= UInt(0) - -;CHECK: Lower Types -;CHECK: circuit top : -;CHECK: module m : -;CHECK: input a{{[_$]+}}x : UInt<5> -;CHECK: output a{{[_$]+}}y : SInt<5> -;CHECK: output b{{[_$]+}}x : UInt<5> -;CHECK: input b{{[_$]+}}y : SInt<5> -;CHECK: module top : -;CHECK: input c{{[_$]+}}x{{[_$]+}}0 : UInt<5> -;CHECK: input c{{[_$]+}}x{{[_$]+}}1 : UInt<5> -;CHECK: input c{{[_$]+}}x{{[_$]+}}2 : UInt<5> -;CHECK: input c{{[_$]+}}x{{[_$]+}}3 : UInt<5> -;CHECK: input c{{[_$]+}}x{{[_$]+}}4 : UInt<5> -;CHECK: output c{{[_$]+}}y{{[_$]+}}x{{[_$]+}}0 : UInt<5> -;CHECK: output c{{[_$]+}}y{{[_$]+}}x{{[_$]+}}1 : UInt<5> -;CHECK: output c{{[_$]+}}y{{[_$]+}}x{{[_$]+}}2 : UInt<5> -;CHECK: input c{{[_$]+}}y{{[_$]+}}y : SInt<5> -;CHECK: wire a{{[_$]+}}x : UInt<5> -;CHECK: wire a{{[_$]+}}y : SInt<5> -;CHECK: wire b{{[_$]+}}x : UInt<5> -;CHECK: wire b{{[_$]+}}y : SInt<5> -;CHECK: inst i of m -;CHECK: wire d{{[_$]+}}0 : UInt<5> -;CHECK: wire d{{[_$]+}}1 : UInt<5> -;CHECK: wire d{{[_$]+}}2 : UInt<5> -;CHECK: wire d{{[_$]+}}3 : UInt<5> -;CHECK: wire d{{[_$]+}}4 : UInt<5> -;CHECK: a{{[_$]+}}x <= b{{[_$]+}}x -;CHECK: a{{[_$]+}}y <= i.a{{[_$]+}}y -;CHECK: b{{[_$]+}}x <= i.b{{[_$]+}}x -;CHECK: b{{[_$]+}}y <= a{{[_$]+}}y -;CHECK: i.a{{[_$]+}}x <= a{{[_$]+}}x -;CHECK: i.b{{[_$]+}}y <= b{{[_$]+}}y -;CHECK: Finished Lower Types diff --git a/test/passes/lower-to-ground/instance.fir b/test/passes/lower-to-ground/instance.fir deleted file mode 100644 index e0175f34..00000000 --- a/test/passes/lower-to-ground/instance.fir +++ /dev/null @@ -1,41 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p cdg 2>&1 | tee %s.out | FileCheck %s - -circuit top : - module source : - output data : UInt<16> - input ready : UInt<1> - data <= UInt(16) - module sink : - input data : UInt<16> - output ready : UInt<1> - ready <= UInt(1) - module top: - wire connect : { data : UInt<16>, flip ready: UInt<1> } - connect.ready <= UInt(1) - connect.data <= UInt(1) - wire connect2 : { flip data : UInt<16>, ready: UInt<1> } - connect2.ready <= UInt(1) - connect2.data <= UInt(1) - inst src of source - inst snk of sink - connect <= src - connect2 <= snk - - -; CHECK: Resolve Genders - -; CHECK: connect@<g:f> <= src@<g:m> -; CHECK: connect2@<g:f> <= snk@<g:m> - -; CHECK: Finished Resolve Genders - - -; CHECK: Lower Types - -; CHECK: connect{{[_$]+}}data@<g:f> <= src@<g:m>.data@<g:m> -; CHECK: connect2{{[_$]+}}ready@<g:f> <= snk@<g:m>.ready@<g:m> -; CHECK: src@<g:m>.ready@<g:f> <= connect{{[_$]+}}ready@<g:m> -; CHECK: snk@<g:m>.data@<g:f> <= connect2{{[_$]+}}data@<g:m> - -; CHECK: Finished Lower Types -; CHECK: Done! diff --git a/test/passes/lower-to-ground/nested-vec.fir b/test/passes/lower-to-ground/nested-vec.fir deleted file mode 100644 index 7f9306ce..00000000 --- a/test/passes/lower-to-ground/nested-vec.fir +++ /dev/null @@ -1,68 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s - -; CHECK: Lower Types -circuit top : - module top : - input clk : Clock - input i : UInt<1> - wire j : { x : UInt<32>, flip y : UInt<32> } - wire k : { x : UInt<32>, y : UInt<32> } - - wire a : { x : UInt<32>, flip y : UInt<32> }[2] - ; CHECK: wire a{{[_$]+}}0{{[_$]+}}x : UInt<32> - ; CHECK: wire a{{[_$]+}}0{{[_$]+}}y : UInt<32> - ; CHECK: wire a{{[_$]+}}1{{[_$]+}}x : UInt<32> - ; CHECK: wire a{{[_$]+}}1{{[_$]+}}y : UInt<32> - a[0].x <= UInt(0) - a[0].y <= UInt(0) - a[1].x <= UInt(0) - a[1].y <= UInt(0) - j.x <= UInt(0) - j.y <= UInt(0) - k.x <= UInt(0) - k.y <= UInt(0) - - wire b : { x : UInt<32>, flip y : UInt<32> } - b <= a[i] - j <= b - - mem m : - data-type => { x : UInt<32>, y : UInt<32> } - depth => 2 - read-latency => 0 - write-latency => 1 - writer => c - - m.c.addr <= i - m.c.clk <= clk - m.c.en <= UInt(1) - m.c.mask.x <= UInt(1) - m.c.mask.y <= UInt(1) - m.c.data <= k - -;CHECK: mem m_x : -;CHECK: data-type => UInt<32> -;CHECK: depth => 2 -;CHECK: write-latency => 1 -;CHECK: read-latency => 0 -;CHECK: writer => c -;CHECK: mem m_y : -;CHECK: data-type => UInt<32> -;CHECK: depth => 2 -;CHECK: write-latency => 1 -;CHECK: read-latency => 0 -;CHECK: writer => c -;CHECK: m_x.c.data <= k_x -;CHECK: m_y.c.data <= k_y -;CHECK: m_x.c.mask <= UInt<1>("h1") -;CHECK: m_y.c.mask <= UInt<1>("h1") -;CHECK: m_x.c.addr <= i -;CHECK: m_y.c.addr <= i -;CHECK: m_x.c.en <= UInt<1>("h1") -;CHECK: m_y.c.en <= UInt<1>("h1") -;CHECK: m_x.c.clk <= clk -;CHECK: m_y.c.clk <= clk - -; CHECK: Finished Lower Types -; CHECK: Done! - diff --git a/test/passes/lower-to-ground/register.fir b/test/passes/lower-to-ground/register.fir deleted file mode 100644 index 648964bd..00000000 --- a/test/passes/lower-to-ground/register.fir +++ /dev/null @@ -1,24 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s - -; CHECK: Lower Types - circuit top : - module top : - input a : UInt<16> - input b : UInt<16> - input clk : Clock - input reset : UInt<1> - - wire q : { x : UInt, y : SInt } - q.x <= UInt(0) - q.y <= SInt(0) - reg r1 : { x : UInt, y : SInt } clk with : - reset => (reset,q) - - ; CHECK: wire q{{[_$]+}}x : UInt - ; CHECK: wire q{{[_$]+}}y : SInt - ; CHECK: reg r1{{[_$]+}}x : UInt<1>, clk with : - ;CHECK: reset => (reset, q_x) - ; CHECK: reg r1{{[_$]+}}y : SInt<1>, clk with : - ;CHECK: reset => (reset, q_y) - -; CHECK: Finished Lower Types diff --git a/test/passes/lower-to-ground/test.fir b/test/passes/lower-to-ground/test.fir deleted file mode 100644 index ac3ef21e..00000000 --- a/test/passes/lower-to-ground/test.fir +++ /dev/null @@ -1,16 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; CHECK: Done! - -circuit Top : - module Queue : - output out : {valid : UInt<1>, flip ready : UInt<1>} - out.valid <= UInt(1) - module Top : - output this : {out : {valid : UInt<1>, flip ready : UInt<1>}} - inst queue of Queue - this.out <= queue.out - wire w : { x : UInt<5>, flip y : UInt<5>} - w.x <= UInt(1) - wire a : UInt<5> - a <= UInt(1) - w.y <= a diff --git a/test/passes/pull-muxes/Muxes.fir b/test/passes/pull-muxes/Muxes.fir deleted file mode 100644 index 295e3ca0..00000000 --- a/test/passes/pull-muxes/Muxes.fir +++ /dev/null @@ -1,17 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -circuit Top : - module Top : - input a : {f:UInt<3>[3]}[2] - input b : {f:UInt<3>[3]}[2] - input p : UInt<1> - input i : UInt<1> - node x = mux(p,mux(p,a[i],a[1]).f,b[i].f)[2] - - - -;CHECK: Pull Muxes -;CHECK: node x = mux(p, mux(p, a[i].f[2], a[1].f[2]), b[i].f[2]) -;CHECK: Finished Pull Muxes -;CHECK: Done! - - diff --git a/test/passes/remove-accesses/bundle-vecs.fir b/test/passes/remove-accesses/bundle-vecs.fir deleted file mode 100644 index 6370ace1..00000000 --- a/test/passes/remove-accesses/bundle-vecs.fir +++ /dev/null @@ -1,44 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s - -; CHECK: Remove Accesses -circuit top : - module top : - wire i : UInt - i <= UInt(1) - wire j : UInt - j <= UInt(1) - - wire a : { x : UInt<32>, flip y : UInt<32> }[2] - a[0].x <= UInt(1) - a[0].y <= UInt(1) - a[1].x <= UInt(1) - a[1].y <= UInt(1) - - wire b : { x : UInt<32>, flip y : UInt<32> } - b <= a[i] - j <= b.x - b.y <= UInt(1) - -; CHECK: wire i : UInt<1> -; CHECK: i <= UInt<1>("h1") -; CHECK: wire j : UInt<32> -; CHECK: j <= UInt<1>("h1") -; CHECK: wire a : { x : UInt<32>, flip y : UInt<32>}[2] -; CHECK: a[0].x <= UInt<1>("h1") -; CHECK: a[0].y <= UInt<1>("h1") -; CHECK: a[1].x <= UInt<1>("h1") -; CHECK: a[1].y <= UInt<1>("h1") -; CHECK: wire b : { x : UInt<32>, flip y : UInt<32>} -; CHECK: wire GEN_0 : UInt<32> -; CHECK: GEN_0 <= a[0].x -; CHECK: when eq(UInt<1>("h1"), i) : GEN_0 <= a[1].x -; CHECK: b.x <= GEN_0 -; CHECK: wire GEN_1 : UInt<32> -; CHECK: when eq(UInt<1>("h0"), i) : a[0].y <= GEN_1 -; CHECK: when eq(UInt<1>("h1"), i) : a[1].y <= GEN_1 -; CHECK: GEN_1 <= b.y -; CHECK: j <= b.x -; CHECK: b.y <= UInt<1>("h1") -; CHECK: Finished Remove Access -; CHECK: Done! - diff --git a/test/passes/remove-accesses/init-vecs.fir b/test/passes/remove-accesses/init-vecs.fir deleted file mode 100644 index d8eeec88..00000000 --- a/test/passes/remove-accesses/init-vecs.fir +++ /dev/null @@ -1,15 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s - -circuit top : - module top : - wire outs : UInt<32>[2][1] - outs[0][0] <= UInt(1) - outs[0][1] <= UInt(1) - - wire out : UInt<32>[2] - out <= outs[UInt(0)] - out[0] <= UInt(1) - -; CHECK: Done! - - diff --git a/test/passes/remove-accesses/simple.fir b/test/passes/remove-accesses/simple.fir deleted file mode 100644 index 1a64d321..00000000 --- a/test/passes/remove-accesses/simple.fir +++ /dev/null @@ -1,14 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s - -circuit top : - module top : - output o : UInt - wire m : UInt<32>[2] - wire i : UInt - m[0] <= UInt("h1") - m[1] <= UInt("h1") - i <= UInt("h1") - node a = m[i] - o <= a - -;CHECK: Done! diff --git a/test/passes/remove-accesses/simple10.fir b/test/passes/remove-accesses/simple10.fir deleted file mode 100644 index b213f372..00000000 --- a/test/passes/remove-accesses/simple10.fir +++ /dev/null @@ -1,16 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p cg 2>&1 | tee %s.out | FileCheck %s - -;CHECK: Done! - -circuit DecoupledAdderTests : - module DecoupledAdderTests : - input clock : Clock - input reset : UInt<1> - input T_31 : UInt<1> - input T_68 : UInt<1> - output out : UInt - output io : {} - wire T_43 : {flip ready : UInt<1>}[1] - T_43[0].ready <= UInt(0) - node T_78 = and(T_68, T_43[T_31].ready) - out <= T_78 diff --git a/test/passes/remove-accesses/simple11.fir b/test/passes/remove-accesses/simple11.fir deleted file mode 100644 index b27f1a46..00000000 --- a/test/passes/remove-accesses/simple11.fir +++ /dev/null @@ -1,151 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s - -;CHECK: Done! - -circuit DecoupledAdderTests : - module NewDecoupledAdder : - input clock : Clock - input reset : UInt<1> - output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {a : UInt<16>, b : UInt<16>}}, out : {flip ready : UInt<1>, valid : UInt<1>, bits : {c : UInt<16>}}} - - io.out.bits.c <= UInt<1>("h00") - io.out.valid <= UInt<1>("h00") - io.in.ready <= UInt<1>("h00") - reg ready : UInt<1>, clock with : - reset => ( reset, ready) - reg busy : UInt<1>, clock with : - reset => ( reset, busy) - reg a_reg : UInt<16>, clock with : - reset => ( reset, a_reg) - reg b_reg : UInt<16>, clock with : - reset => ( reset, b_reg) - io.in.ready <= ready - when io.in.valid : - a_reg <= io.in.bits.a - b_reg <= io.in.bits.b - io.in.ready <= UInt<1>("h00") - ready <= UInt<1>("h00") - busy <= UInt<1>("h01") - skip - node T_45 = and(busy, io.out.ready) - when T_45 : - node T_46 = tail(add(a_reg, b_reg),1) - io.out.bits.c <= T_46 - io.out.valid <= UInt<1>("h01") - io.in.ready <= UInt<1>("h01") - busy <= UInt<1>("h00") - skip - - module DecoupledAdderTests : - input clock : Clock - input reset : UInt<1> - output io : {} - - inst device_under_test of NewDecoupledAdder - device_under_test.io.out.ready <= UInt<1>("h00") - device_under_test.io.in.bits.b <= UInt<1>("h00") - device_under_test.io.in.bits.a <= UInt<1>("h00") - device_under_test.io.in.valid <= UInt<1>("h00") - device_under_test.clock <= clock - device_under_test.reset <= reset - reg T_10 : UInt<33>, clock with : - reset => ( reset, UInt<33>("h00")) - node T_12 = tail(add(T_10, UInt<1>("h01")),1) - T_10 <= T_12 - node T_14 = eq(reset, UInt<1>("h00")) - when T_14 : - printf(clock,UInt(1), "ticker %d", T_10) - skip - node T_16 = gt(T_10, UInt<7>("h064")) - when T_16 : - node T_18 = eq(reset, UInt<1>("h00")) - when T_18 : - stop(clock,UInt(1), 0) - skip - skip - node T_20 = eq(reset, UInt<1>("h00")) - when T_20 : - printf(clock,UInt(1), "device out ready %d, valid %d", device_under_test.io.out.ready, device_under_test.io.out.valid) - skip - node T_22 = eq(reset, UInt<1>("h00")) - when T_22 : - printf(clock,UInt(1), "device in ready %d, valid %d", device_under_test.io.in.ready, device_under_test.io.in.valid) - skip - reg T_24 : UInt<1>, clock with : - reset => ( reset, UInt<1>("h00")) - reg T_26 : UInt<1>, clock with : - reset => ( reset, UInt<1>("h00")) - node T_27 = and(T_24, T_26) - when T_27 : - node T_29 = eq(reset, UInt<1>("h00")) - when T_29 : - stop(clock,UInt(1), 0) - skip - skip - reg T_31 : UInt<1>, clock with : - reset => ( reset, UInt<1>("h00")) - reg T_33 : UInt<1>, clock with : - reset => ( reset, UInt<1>("h00")) - wire T_43 : {flip ready : UInt<1>, valid : UInt<1>, bits : {a : UInt<16>, b : UInt<16>}}[1] - T_43[0].bits.b <= UInt(0) - T_43[0].bits.a <= UInt(1) - T_43[0].valid <= UInt(1) - device_under_test.io.in <- T_43[0] - wire T_64 : UInt<16>[1] - T_64[0] <= UInt<16>("h04") - node T_68 = eq(T_24, UInt<1>("h00")) - node T_78 = and(T_68, T_43[T_31].ready) - when T_78 : - node T_80 = eq(reset, UInt<1>("h00")) - when T_80 : - printf(clock,UInt(1), "input_event_counter %d", T_31) - skip - device_under_test.io.in.bits.a <= T_64[T_31] - skip - wire T_84 : UInt<16>[1] - T_84[0] <= UInt<16>("h07") - node T_88 = eq(T_24, UInt<1>("h00")) - node T_98 = and(T_88, T_43[T_31].ready) - when T_98 : - node T_100 = eq(reset, UInt<1>("h00")) - when T_100 : - printf(clock,UInt(1), "input_event_counter %d", T_31) - skip - device_under_test.io.in.bits.b <= T_84[T_31] - skip - node T_103 = eq(T_24, UInt<1>("h00")) - node T_113 = and(T_103, T_43[T_31].ready) - when T_113 : - T_43[T_31].valid <= UInt<1>("h01") - node T_125 = tail(add(T_31, UInt<1>("h01")),1) - T_31 <= T_125 - node T_127 = geq(T_31, UInt<1>("h00")) - T_24 <= T_127 - skip - node T_129 = eq(T_26, UInt<1>("h00")) - when T_129 : - node T_131 = tail(add(T_33, UInt<1>("h01")),1) - T_33 <= T_131 - node T_133 = geq(T_33, UInt<1>("h00")) - T_26 <= T_133 - skip - wire T_136 : UInt<1>[1] - T_136[0] <= UInt<1>("h01") - wire T_141 : UInt<16>[1] - T_141[0] <= UInt<16>("h03") - node T_145 = eq(T_26, UInt<1>("h00")) - node T_147 = and(T_145, T_136[T_33]) - node T_148 = and(T_147, device_under_test.io.out.valid) - when T_148 : - node T_150 = eq(reset, UInt<1>("h00")) - when T_150 : - printf(clock,UInt(1), "output_event_counter %d", T_33) - skip - node T_152 = neq(device_under_test.io.out.bits.c, T_141[T_33]) - when T_152 : - node T_155 = eq(reset, UInt<1>("h00")) - when T_155 : - printf(clock,UInt(1), "Error: event %d out.bits.c was %x should be %x", T_33, device_under_test.io.out.bits.c, T_141[T_33]) - skip - skip - skip diff --git a/test/passes/remove-accesses/simple2.fir b/test/passes/remove-accesses/simple2.fir deleted file mode 100644 index ee6b5923..00000000 --- a/test/passes/remove-accesses/simple2.fir +++ /dev/null @@ -1,16 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s - -circuit top : - module top : - output o1 : UInt - output o2 : UInt - wire m : UInt<32>[2] - wire i : UInt - m[0] <= UInt("h1") - m[1] <= UInt("h1") - i <= UInt("h1") - node a = m[i] - o1 <= a - o2 <= a - -;CHECK: Done! diff --git a/test/passes/remove-accesses/simple3.fir b/test/passes/remove-accesses/simple3.fir deleted file mode 100644 index 9aa0f34f..00000000 --- a/test/passes/remove-accesses/simple3.fir +++ /dev/null @@ -1,24 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s - -;CHECK: Remove Accesses -circuit top : - module top : - input in : UInt<32> - input i : UInt<1> - wire m : UInt<32>[2] - m[0] <= UInt("h1") - m[1] <= UInt("h1") - wire a : UInt<32> - m[i] <= a - a <= in - -;CHECK: wire GEN_0 : UInt<32> -;CHECK: when eq(UInt<1>("h0"), i) : m[0] <= GEN_0 -;CHECK: when eq(UInt<1>("h1"), i) : m[1] <= GEN_0 -;CHECK: GEN_0 <= a - -;CHECK: Finished Remove Accesses - - - -;CHECK: Done! diff --git a/test/passes/remove-accesses/simple4.fir b/test/passes/remove-accesses/simple4.fir deleted file mode 100644 index f4f3a6a5..00000000 --- a/test/passes/remove-accesses/simple4.fir +++ /dev/null @@ -1,22 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s - -;CHECK: Remove Accesses -circuit top : - module top : - input in : {x : UInt<32>, y : UInt<32>} - input i : UInt<1> - wire m : {x : UInt<32>, y : UInt<32>}[2] - m[0].x <= UInt("h1") - m[0].y <= UInt("h1") - m[1].x <= UInt("h1") - m[1].y <= UInt("h1") - m[i].x <= in.x - -;CHECK: when eq(UInt<1>("h0"), i) : m[0].x <= GEN_0 -;CHECK: when eq(UInt<1>("h1"), i) : m[1].x <= GEN_0 -;CHECK: GEN_0 <= in -;CHECK: Finished Remove Accesses -;CHECK: Done! - - - diff --git a/test/passes/remove-accesses/simple5.fir b/test/passes/remove-accesses/simple5.fir deleted file mode 100644 index e21dcf1a..00000000 --- a/test/passes/remove-accesses/simple5.fir +++ /dev/null @@ -1,21 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s - -;CHECK: Remove Accesses -circuit top : - module top : - output o : UInt - o <= UInt(1) - wire m : UInt<32>[2] - wire i : UInt - m[0] <= UInt("h1") - m[1] <= UInt("h1") - i <= UInt("h1") - when i : - o <= m[i] - -;CHECK: when i : -;CHECK: GEN_0 <= m[0] -;CHECK: when eq(UInt<1>("h1"), i) : GEN_0 <= m[1] -;CHECK: o <= GEN_0 -;CHECK: Finished Remove Accesses -;CHECK: Done! diff --git a/test/passes/remove-accesses/simple6.fir b/test/passes/remove-accesses/simple6.fir deleted file mode 100644 index eee62681..00000000 --- a/test/passes/remove-accesses/simple6.fir +++ /dev/null @@ -1,21 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s - -;CHECK: Remove Accesses -circuit top : - module top : - input value : UInt<32> - input in : {x : UInt<32>, y : UInt<32>} - wire m :{x : UInt<32>, y : UInt<32>}[2][2] - wire i : UInt - wire j : UInt - - m[0][0] <= in - m[1][0] <= in - m[0][1] <= in - m[1][1] <= in - i <= UInt("h1") - j <= UInt("h1") - - m[i][j].x <= value - -;CHECK: Done! diff --git a/test/passes/remove-accesses/simple7.fir b/test/passes/remove-accesses/simple7.fir deleted file mode 100644 index 5dfd5ce3..00000000 --- a/test/passes/remove-accesses/simple7.fir +++ /dev/null @@ -1,11 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s - -circuit top : - module top : - output out : UInt<64> - input index : UInt<1> - wire T_292 : UInt<64>[2] - T_292[0] <= UInt(1) - T_292[1] <= UInt(1) - out <= T_292[index] -;CHECK: Done! diff --git a/test/passes/remove-accesses/simple8.fir b/test/passes/remove-accesses/simple8.fir deleted file mode 100644 index 1d275618..00000000 --- a/test/passes/remove-accesses/simple8.fir +++ /dev/null @@ -1,241 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s - -circuit top : - module top : - output resp : UInt<128>[4] - input write : {flip ready : UInt<1>, valid : UInt<1>, bits : {way_en : UInt<4>, addr : UInt<12>, wmask : UInt<2>, data : UInt<128>}} - input read : {flip ready : UInt<1>, valid : UInt<1>, bits : {way_en : UInt<4>, addr : UInt<12>}} - input clock : Clock - input reset : UInt<1> - - resp[0] <= UInt<1>("h00") - resp[1] <= UInt<1>("h00") - resp[2] <= UInt<1>("h00") - resp[3] <= UInt<1>("h00") - write.ready <= UInt<1>("h00") - read.ready <= UInt<1>("h00") - node waddr = shr(write.bits.addr, 4) - node raddr = shr(read.bits.addr, 4) - node T_65 = bits(write.bits.way_en, 1, 0) - node T_66 = bits(read.bits.way_en, 1, 0) - wire T_75 : UInt<128>[2] - T_75[0] <= UInt<1>("h00") - T_75[1] <= UInt<1>("h00") - reg T_81 : UInt<12>, clock with : - reset => ( reset, T_81) - when read.valid : - T_81 <= read.bits.addr - skip - cmem T_84 : UInt<128>[256] - node T_86 = neq(T_65, UInt<1>("h00")) - node T_87 = and(T_86, write.valid) - node T_88 = bits(write.bits.wmask, 0, 0) - node T_89 = and(T_87, T_88) - when T_89 : - node T_90 = bits(write.bits.data, 63, 0) - node T_91 = cat(T_90, T_90) - node T_92 = bits(T_65, 0, 0) - node T_93 = bits(T_65, 1, 1) - wire T_95 : UInt<1>[2] - T_95[0] <= T_92 - T_95[1] <= T_93 - node T_100 = tail(sub(UInt<64>("h00"), T_95[0]),1) - node T_102 = tail(sub(UInt<64>("h00"), T_95[1]),1) - wire T_104 : UInt<64>[2] - T_104[0] <= T_100 - T_104[1] <= T_102 - node T_108 = cat(T_104[1], T_104[0]) - read mport T_109 = T_84[waddr],clock - node T_110 = not(T_108) - node T_111 = and(T_109, T_110) - node T_112 = and(T_91, T_108) - node T_113 = or(T_111, T_112) - wire T_114 : UInt<128> - T_114 <= UInt<1>("h00") - T_114 <= T_113 - write mport T_116 = T_84[waddr],clock - T_116 <= T_114 - skip - node T_118 = neq(T_66, UInt<1>("h00")) - node T_119 = and(T_118, read.valid) - reg T_120 : UInt<8>, clock with : - reset => ( reset, T_120) - when T_119 : - T_120 <= raddr - skip - read mport T_121 = T_84[T_120],clock - T_75[0] <= T_121 - cmem T_124 : UInt<128>[256] - node T_126 = neq(T_65, UInt<1>("h00")) - node T_127 = and(T_126, write.valid) - node T_128 = bits(write.bits.wmask, 1, 1) - node T_129 = and(T_127, T_128) - when T_129 : - node T_130 = bits(write.bits.data, 127, 64) - node T_131 = cat(T_130, T_130) - node T_132 = bits(T_65, 0, 0) - node T_133 = bits(T_65, 1, 1) - wire T_135 : UInt<1>[2] - T_135[0] <= T_132 - T_135[1] <= T_133 - node T_140 = tail(sub(UInt<64>("h00"), T_135[0]),1) - node T_142 = tail(sub(UInt<64>("h00"), T_135[1]),1) - wire T_144 : UInt<64>[2] - T_144[0] <= T_140 - T_144[1] <= T_142 - node T_148 = cat(T_144[1], T_144[0]) - read mport T_149 = T_124[waddr],clock - node T_150 = not(T_148) - node T_151 = and(T_149, T_150) - node T_152 = and(T_131, T_148) - node T_153 = or(T_151, T_152) - wire T_154 : UInt<128> - T_154 <= UInt<1>("h00") - T_154 <= T_153 - write mport T_156 = T_124[waddr],clock - T_156 <= T_154 - skip - node T_158 = neq(T_66, UInt<1>("h00")) - node T_159 = and(T_158, read.valid) - reg T_160 : UInt<8>, clock with : - reset => ( reset, T_160) - when T_159 : - T_160 <= raddr - skip - read mport T_161 = T_124[T_160],clock - T_75[1] <= T_161 - node T_162 = bits(T_75[0], 63, 0) - node T_163 = bits(T_75[1], 63, 0) - wire T_165 : UInt<64>[2] - T_165[0] <= T_162 - T_165[1] <= T_163 - node T_169 = bits(T_81, 3, 3) - wire T_172 : UInt<64>[2] - T_172[0] <= T_165[T_169] - T_172[1] <= T_165[1] - node T_176 = cat(T_172[1], T_172[0]) - resp[0] <= T_176 - node T_177 = bits(T_75[0], 127, 64) - node T_178 = bits(T_75[1], 127, 64) - wire T_180 : UInt<64>[2] - T_180[0] <= T_177 - T_180[1] <= T_178 - node T_184 = bits(T_81, 3, 3) - wire T_187 : UInt<64>[2] - T_187[0] <= T_180[T_184] - T_187[1] <= T_180[1] - node T_191 = cat(T_187[1], T_187[0]) - resp[1] <= T_191 - node T_192 = bits(write.bits.way_en, 3, 2) - node T_193 = bits(read.bits.way_en, 3, 2) - wire T_202 : UInt<128>[2] - T_202[0] <= UInt<1>("h00") - T_202[1] <= UInt<1>("h00") - reg T_208 : UInt<12>, clock with : - reset => ( reset, T_208) - when read.valid : - T_208 <= read.bits.addr - skip - cmem T_211 : UInt<128>[256] - node T_213 = neq(T_192, UInt<1>("h00")) - node T_214 = and(T_213, write.valid) - node T_215 = bits(write.bits.wmask, 0, 0) - node T_216 = and(T_214, T_215) - when T_216 : - node T_217 = bits(write.bits.data, 63, 0) - node T_218 = cat(T_217, T_217) - node T_219 = bits(T_192, 0, 0) - node T_220 = bits(T_192, 1, 1) - wire T_222 : UInt<1>[2] - T_222[0] <= T_219 - T_222[1] <= T_220 - node T_227 = tail(sub(UInt<64>("h00"), T_222[0]),1) - node T_229 = tail(sub(UInt<64>("h00"), T_222[1]),1) - wire T_231 : UInt<64>[2] - T_231[0] <= T_227 - T_231[1] <= T_229 - node T_235 = cat(T_231[1], T_231[0]) - read mport T_236 = T_211[waddr],clock - node T_237 = not(T_235) - node T_238 = and(T_236, T_237) - node T_239 = and(T_218, T_235) - node T_240 = or(T_238, T_239) - wire T_241 : UInt<128> - T_241 <= UInt<1>("h00") - T_241 <= T_240 - write mport T_243 = T_211[waddr],clock - T_243 <= T_241 - skip - node T_245 = neq(T_193, UInt<1>("h00")) - node T_246 = and(T_245, read.valid) - reg T_247 : UInt<8>, clock with : - reset => ( reset, T_247) - when T_246 : - T_247 <= raddr - skip - read mport T_248 = T_211[T_247],clock - T_202[0] <= T_248 - cmem T_251 : UInt<128>[256] - node T_253 = neq(T_192, UInt<1>("h00")) - node T_254 = and(T_253, write.valid) - node T_255 = bits(write.bits.wmask, 1, 1) - node T_256 = and(T_254, T_255) - when T_256 : - node T_257 = bits(write.bits.data, 127, 64) - node T_258 = cat(T_257, T_257) - node T_259 = bits(T_192, 0, 0) - node T_260 = bits(T_192, 1, 1) - wire T_262 : UInt<1>[2] - T_262[0] <= T_259 - T_262[1] <= T_260 - node T_267 = tail(sub(UInt<64>("h00"), T_262[0]),1) - node T_269 = tail(sub(UInt<64>("h00"), T_262[1]),1) - wire T_271 : UInt<64>[2] - T_271[0] <= T_267 - T_271[1] <= T_269 - node T_275 = cat(T_271[1], T_271[0]) - read mport T_276 = T_251[waddr],clock - node T_277 = not(T_275) - node T_278 = and(T_276, T_277) - node T_279 = and(T_258, T_275) - node T_280 = or(T_278, T_279) - wire T_281 : UInt<128> - T_281 <= UInt<1>("h00") - T_281 <= T_280 - write mport T_283 = T_251[waddr],clock - T_283 <= T_281 - skip - node T_285 = neq(T_193, UInt<1>("h00")) - node T_286 = and(T_285, read.valid) - reg T_287 : UInt<8>, clock with : - reset => ( reset, T_287) - when T_286 : - T_287 <= raddr - skip - read mport T_288 = T_251[T_287],clock - T_202[1] <= T_288 - node T_289 = bits(T_202[0], 63, 0) - node T_290 = bits(T_202[1], 63, 0) - wire T_292 : UInt<64>[2] - T_292[0] <= T_289 - T_292[1] <= T_290 - node T_296 = bits(T_208, 3, 3) - wire T_299 : UInt<64>[2] - T_299[0] <= T_292[T_296] - T_299[1] <= T_292[1] - node T_303 = cat(T_299[1], T_299[0]) - resp[2] <= T_303 - node T_304 = bits(T_202[0], 127, 64) - node T_305 = bits(T_202[1], 127, 64) - wire T_307 : UInt<64>[2] - T_307[0] <= T_304 - T_307[1] <= T_305 - node T_311 = bits(T_208, 3, 3) - wire T_314 : UInt<64>[2] - T_314[0] <= T_307[T_311] - T_314[1] <= T_307[1] - node T_318 = cat(T_314[1], T_314[0]) - resp[3] <= T_318 - read.ready <= UInt<1>("h01") - write.ready <= UInt<1>("h01") -;CHECK: Done! diff --git a/test/passes/remove-accesses/simple9.fir b/test/passes/remove-accesses/simple9.fir deleted file mode 100644 index d1aec9f1..00000000 --- a/test/passes/remove-accesses/simple9.fir +++ /dev/null @@ -1,17 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s - -circuit top : - module top : - input T_4910 : UInt<1> - input T_4581 : UInt<1> - input reset : UInt<1> - input clock : Clock - output out : UInt<1> - reg T_4590 : UInt<1>[2], clock with : - reset => ( reset, T_4590) - T_4590[0] <= UInt(0) - T_4590[1] <= UInt(0) - out <= UInt(0) - when T_4910 : - out <= T_4590[T_4581] -;CHECK: Done! diff --git a/test/passes/resolve-genders/bigenders.fir b/test/passes/resolve-genders/bigenders.fir deleted file mode 100644 index a13390f7..00000000 --- a/test/passes/resolve-genders/bigenders.fir +++ /dev/null @@ -1,13 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s - -;CHECK: Resolve Genders -circuit top : - module top : - input i : UInt<10> - output o : UInt<10> - wire w : {x : UInt<10>, flip y : UInt<10>} - w.x <= i - w.y <= i - o <= w.x - o <= w.y -; CHECK: Finished Resolve Genders diff --git a/test/passes/resolve-genders/bulk.fir b/test/passes/resolve-genders/bulk.fir deleted file mode 100644 index 7e746a37..00000000 --- a/test/passes/resolve-genders/bulk.fir +++ /dev/null @@ -1,14 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s - -;CHECK: Resolve Genders -circuit top : - module source : - output bundle : { data : UInt<16>, flip ready : UInt<1> } - module sink : - input bundle : { data : UInt<16>, flip ready : UInt<1> } - module top : - inst src of source - inst snk of sink - snk.bundle <= src.bundle - -; CHECK: Finished Resolve Genders diff --git a/test/passes/resolve-genders/gcd.fir b/test/passes/resolve-genders/gcd.fir deleted file mode 100644 index c2a0df4a..00000000 --- a/test/passes/resolve-genders/gcd.fir +++ /dev/null @@ -1,57 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p cg 2>&1 | tee %s.out | FileCheck %s - -;CHECK: Resolve Genders -circuit top : - module subtracter : - input x : UInt - input y : UInt - output z : UInt - z <= tail(sub(x, y),1) - ;CHECK: z@<g:f> <= tail(sub(x@<g:m>, y@<g:m>)@<g:m>, 1)@<g:m> - module gcd : - input a : UInt<16> - input b : UInt<16> - input e : UInt<1> - input clk : Clock - input reset : UInt<1> - output z : UInt<16> - output v : UInt<1> - reg x : UInt,clk with : - reset => (reset,UInt(0)) - reg y : UInt,clk with : - reset => (reset,UInt(42)) -; CHECK: reg x : UInt - when gt(x, y) : - ;CHECK: when gt(x@<g:m>, y@<g:m>)@<g:m> : - inst s of subtracter - s.x <= x - s.y <= y - x <= s.z - ;CHECK: s@<g:m>.x@<g:f> <= x@<g:m> - ;CHECK: s@<g:m>.y@<g:f> <= y@<g:m> - ;CHECK: x@<g:f> <= s@<g:m>.z@<g:m> - else : - inst s2 of subtracter - s2.x <= x - s2.y <= y - y <= s2.z - when e : - x <= a - y <= b - v <= eq(v, UInt(0)) - z <= x - module top : - input clk : Clock - input reset : UInt<1> - input a : UInt<16> - input b : UInt<16> - output z : UInt - inst i of gcd - i.a <= a - i.b <= b - i.clk <= clk - i.reset <= reset - i.e <= UInt(1) - z <= i.z - -; CHECK: Finished Resolve Genders diff --git a/test/passes/resolve-genders/ports.fir b/test/passes/resolve-genders/ports.fir deleted file mode 100644 index 246fb9ac..00000000 --- a/test/passes/resolve-genders/ports.fir +++ /dev/null @@ -1,21 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p cg 2>&1 | tee %s.out | FileCheck %s - -;CHECK: Resolve Genders -circuit top : - module source : - output data : UInt<16> - input ready : UInt<1> - data <= UInt(16) - module sink : - input data : UInt<16> - output ready : UInt<1> - module top: - wire connect : { data : UInt<16>, flip ready: UInt<1> } - inst src of source - inst snk of sink - connect.data <= src.data ;CHECK: connect@<g:f>.data@<g:f> <= src@<g:m>.data@<g:m> - src.ready <= connect.ready ;CHECK: src@<g:m>.ready@<g:f> <= connect@<g:f>.ready@<g:m> - snk.data <= connect.data ;CHECK: snk@<g:m>.data@<g:f> <= connect@<g:m>.data@<g:m> - connect.ready <= snk.ready ;CHECK: connect@<g:m>.ready@<g:f> <= snk@<g:m>.ready@<g:m> - -; CHECK: Finished Resolve Genders diff --git a/test/passes/resolve-genders/subbundle.fir b/test/passes/resolve-genders/subbundle.fir deleted file mode 100644 index e91fa52e..00000000 --- a/test/passes/resolve-genders/subbundle.fir +++ /dev/null @@ -1,14 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p cT 2>&1 | tee %s.out | FileCheck %s - -;CHECK: Lower Types -circuit top : - module top : - input clk : Clock - input reset : UInt<1> - wire w : { flip x : UInt<10>} - reg r : { flip x : UInt<10>},clk with : - reset => (reset,w) - w <= r ; CHECK r_x := w_x - w.x <= r.x ; CHECK w_x := r_x -; CHECK: Finished Lower Types - diff --git a/test/passes/resolve-kinds/gcd.fir b/test/passes/resolve-kinds/gcd.fir deleted file mode 100644 index cdc8c337..00000000 --- a/test/passes/resolve-kinds/gcd.fir +++ /dev/null @@ -1,55 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p ck 2>&1 | tee %s.out | FileCheck %s - -; CHECK: Resolve Kinds -circuit top : - module subtracter : - input x : UInt - input y : UInt - output z : UInt - z <= tail(sub(x, y),1) - ;CHECK: z@<k:port> <= tail(sub(x@<k:port>, y@<k:port>)@<k:exp>, 1)@<k:exp> - module gcd : - input clk : Clock - input reset : UInt<1> - input a : UInt<16> - input b : UInt<16> - input e : UInt<1> - output z : UInt<16> - output v : UInt<1> - reg x : UInt,clk with : - reset => (reset,UInt(0)) - reg y : UInt,clk with : - reset => (reset,UInt(42)) - when gt(x, y) : - inst s of subtracter - s.x <= x - ;CHECK: s@<k:inst>.x@<k:inst> <= x@<k:reg> - s.y <= y - x <= s.z - else : - inst s2 of subtracter - s2.x <= x - s2.y <= y - y <= s2.z - when e : - x <= a - y <= b - v <= eq(v, UInt(0)) - z <= x - module top : - input a : UInt<16> - input b : UInt<16> - input clk : Clock - input reset : UInt<1> - output z : UInt - inst i of gcd - i.a <= a - i.b <= b - i.clk <= clk - i.reset <= reset - i.e <= UInt(1) - z <= i.z - ;CHECK: z@<k:port> <= i@<k:inst>.z@<k:inst> -; CHECK: Finished Resolve Kinds - - diff --git a/test/passes/split-exp/gcd.fir b/test/passes/split-exp/gcd.fir deleted file mode 100644 index 4b42d007..00000000 --- a/test/passes/split-exp/gcd.fir +++ /dev/null @@ -1,49 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s - -;CHECK: Split Expressions -circuit top : - module subtracter : - input x : UInt - input y : UInt - output q : UInt - q <= tail(sub(x, y),1) - module gcd : - input clk : Clock - input reset : UInt<1> - input a : UInt<16> - input b : UInt<16> - input e : UInt<1> - output z : UInt<16> - reg x : UInt,clk with : - reset => (reset,UInt(0)) - reg y : UInt,clk with : - reset => (reset,UInt(42)) - when gt(x, y) : - inst s of subtracter - s.x <= x - s.y <= y - x <= s.q - else : - inst s2 of subtracter - s2.x <= x - s2.y <= y - y <= s2.q - when e : - x <= a - y <= b - z <= x - module top : - input clk : Clock - input reset : UInt<1> - input a : UInt<16> - input b : UInt<16> - output z : UInt - inst i of gcd - i.clk <= clk - i.reset <= reset - i.a <= a - i.b <= b - i.e <= UInt(1) - z <= i.z - -; CHECK: Finished Split Expressions diff --git a/test/passes/split-exp/primop.fir b/test/passes/split-exp/primop.fir deleted file mode 100644 index cdbd4e77..00000000 --- a/test/passes/split-exp/primop.fir +++ /dev/null @@ -1,21 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s - -;CHECK: Split Expressions -circuit Top : - module Top : - output out : UInt<1> - - wire m : UInt<1>[3] - m[0] <= UInt(0) - m[1] <= UInt(0) - m[2] <= UInt(0) - - wire x : UInt<1> - x <= not(UInt(1)) - wire a : UInt<1> - a <= m[x] - - out <= a - - - diff --git a/test/passes/split-exp/print-args.fir b/test/passes/split-exp/print-args.fir deleted file mode 100644 index df21949d..00000000 --- a/test/passes/split-exp/print-args.fir +++ /dev/null @@ -1,14 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s - -; CHECK: Split Expressions -; CHECK: node GEN_0 = and(a, b) -; CHECK: printf(clk, UInt<1>("h1"), "%d\n", GEN_0) - -circuit Bug : - module Bug : - input clk : Clock - input a : UInt<1> - input b : UInt<1> - - printf(clk, UInt<1>(1), "%d\n", and(a, b)) - diff --git a/test/passes/split-exp/split-and.fir b/test/passes/split-exp/split-and.fir deleted file mode 100644 index 8eb4bdab..00000000 --- a/test/passes/split-exp/split-and.fir +++ /dev/null @@ -1,8 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p cT 2>&1 | tee %s.out | FileCheck %s - -; CHECK: Done! -circuit Top : - module Top : - input a : SInt<2> - output c : UInt<2> - c <= and(a,asSInt(UInt(2))) diff --git a/test/passes/split-exp/split-in-when.fir b/test/passes/split-exp/split-in-when.fir deleted file mode 100644 index 47caa16b..00000000 --- a/test/passes/split-exp/split-in-when.fir +++ /dev/null @@ -1,25 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s - -;CHECK: Split Expressions -circuit Top : - module Top : - input p : UInt<1> - input clk : Clock - input a : UInt<10> - input b : UInt<10> - input c : UInt<10> - - reg out : UInt<10>,clk with : - reset => (p,a) - - when bits(tail(sub(a,c),1),3,3) : out <= mux(eq(bits(UInt(32),4,0),UInt(13)),tail(add(a,tail(add(b,c),1)),1),tail(sub(c,b),1)) - -;CHECK: node GEN_0 = subw(a, c) -;CHECK: node GEN_1 = bits(GEN_0, 3, 3) -;CHECK: node GEN_2 = eq(UInt<5>("h0"), UInt<4>("hd")) -;CHECK: node GEN_3 = addw(b, c) -;CHECK: node GEN_4 = addw(a, GEN_3) -;CHECK: node GEN_5 = subw(c, b) -;CHECK: out <= mux(GEN_1, mux(GEN_2, GEN_4, GEN_5), out) - -;CHECK: Finished Split Expressions diff --git a/test/passes/to-flo/gcd.fir b/test/passes/to-flo/gcd.fir deleted file mode 100644 index 680c2a9a..00000000 --- a/test/passes/to-flo/gcd.fir +++ /dev/null @@ -1,50 +0,0 @@ -; RUN: firrtl -i %s -o %s.flo -X flo -p c 2>&1 | tee %s.out | FileCheck %s -; XFAIL: * - -;CHECK: Flo -circuit top : - module subtracter : - input x : UInt - input y : UInt - output q : UInt - q <= subw(x, y) - module gcd : - input clk : Clock - input reset : UInt<1> - input a : UInt<16> - input b : UInt<16> - input e : UInt<1> - output z : UInt<16> - reg x : UInt,clk,reset - reg y : UInt,clk,reset - onreset x <= UInt(0) - onreset y <= UInt(42) - when gt(x, y) : - inst s of subtracter - s.x <= x - s.y <= y - x <= s.q - else : - inst s2 of subtracter - s2.x <= x - s2.y <= y - y <= s2.q - when e : - x <= a - y <= b - z <= x - module top : - input a : UInt<16> - input b : UInt<16> - input clk : Clock - input reset : UInt<1> - output z : UInt - inst i of gcd - i.clk <= clk - i.reset <= reset - i.a <= a - i.b <= b - i.e <= UInt(1) - z <= i.z -;CHECK: Done! - diff --git a/test/passes/to-verilog/escape-quote.fir b/test/passes/to-verilog/escape-quote.fir deleted file mode 100644 index 224026a9..00000000 --- a/test/passes/to-verilog/escape-quote.fir +++ /dev/null @@ -1,18 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog ; cat %s.v | FileCheck %s - -;CHECK: module top( -;CHECK: input clk -;CHECK: ); -;CHECK: always @(posedge clk) begin -;CHECK: `ifndef SYNTHESIS -;CHECK: if(1'h1) begin -;CHECK: $fwrite(32'h80000002,"This has an escaped quote (\") in it"); -;CHECK: end -;CHECK: `endif -;CHECK: end -;CHECK: endmodule - -circuit top : - module top : - input clk : Clock - printf(clk, UInt<1>(1), "This has an escaped quote (\") in it") diff --git a/test/passes/to-verilog/gcd.fir b/test/passes/to-verilog/gcd.fir deleted file mode 100644 index 5a50ddd1..00000000 --- a/test/passes/to-verilog/gcd.fir +++ /dev/null @@ -1,51 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p cw 2>&1 | tee %s.out | FileCheck %s - -;CHECK: Verilog -circuit top : - module subtracter : - input x : UInt - input y : UInt - output q : UInt - q <= tail(sub(x, y),1) - module gcd : - input clk : Clock - input reset : UInt<1> - input a : UInt<16> - input b : UInt<16> - input e : UInt<1> - output z : UInt<16> - reg x : UInt,clk with : - reset => (reset,UInt(0)) - reg y : UInt,clk with : - reset => (reset,UInt(42)) - when gt(x, y) : - inst s of subtracter - s.x <= x - s.y <= y - x <= s.q - else : - inst s2 of subtracter - s2.x <= x - s2.y <= y - y <= s2.q - when e : - x <= a - y <= b - z <= x - module top : - input a : UInt<16> - input b : UInt<16> - input clk : Clock - input reset : UInt<1> - output z : UInt - inst i of gcd - i.clk <= clk - i.reset <= reset - i.a <= a - i.b <= b - i.e <= UInt(1) - z <= i.z - - - -;CHECK: Done! diff --git a/test/passes/to-verilog/mem.fir b/test/passes/to-verilog/mem.fir deleted file mode 100644 index 5d1c60f0..00000000 --- a/test/passes/to-verilog/mem.fir +++ /dev/null @@ -1,12 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog ; cat %s.v | FileCheck %s - -;CHECK: reg [29:0] m [0:127]; -circuit top : - module top : - input clk : Clock - output read : UInt<30> - cmem m : UInt<30>[128], clk - read accessor x = m[UInt(0)] - read <= x - - diff --git a/test/passes/to-verilog/print-args.fir b/test/passes/to-verilog/print-args.fir deleted file mode 100644 index f0344366..00000000 --- a/test/passes/to-verilog/print-args.fir +++ /dev/null @@ -1,25 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog ; cat %s.v | FileCheck %s - -;CHECK: module Bug( -;CHECK: input clk, -;CHECK: input a, -;CHECK: input b -;CHECK: ); -;CHECK: wire GEN_0; -;CHECK: assign GEN_0 = a & b; -;CHECK: always @(posedge clk) begin -;CHECK: `ifndef SYNTHESIS -;CHECK: if(1'h1) begin -;CHECK: $fwrite(32'h80000002,"%d\n",GEN_0); -;CHECK: end -;CHECK: `endif -;CHECK: end -;CHECK: endmodule - -circuit Bug : - module Bug : - input clk : Clock - input a : UInt<1> - input b : UInt<1> - - printf(clk, UInt<1>(1), "%d\n", and(a, b)) diff --git a/test/passes/to-verilog/rd-mem.fir b/test/passes/to-verilog/rd-mem.fir deleted file mode 100644 index 59829777..00000000 --- a/test/passes/to-verilog/rd-mem.fir +++ /dev/null @@ -1,51 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c &> %s.out ; cat %s.v | FileCheck %s - -circuit top : - module top : - output rdata : UInt<32> - input index : UInt<2> - input ren : UInt<1> - input clk : Clock - - mem m : - data-type => UInt<32> - depth => 4 - read-latency => 1 - write-latency => 1 - reader => c - m.c.addr <= index - m.c.en <= ren - m.c.clk <= clk - rdata <= m.c.data - -;CHECK: module top( -;CHECK: output [31:0] rdata, -;CHECK: input [1:0] index, -;CHECK: input ren, -;CHECK: input clk -;CHECK: ); -;CHECK: reg [31:0] m [0:3]; -;CHECK: wire [31:0] m_c_data; -;CHECK: wire [1:0] m_c_addr; -;CHECK: wire m_c_en; -;CHECK: wire m_c_clk; -;CHECK: reg [1:0] GEN_0; -;CHECK: reg GEN_1; -;CHECK: assign rdata = m_c_data; -;CHECK: assign m_c_addr = index; -;CHECK: assign m_c_en = ren; -;CHECK: assign m_c_clk = clk; -;CHECK: assign m_c_data = m[GEN_0]; -;CHECK: `ifndef SYNTHESIS -;CHECK: integer initvar; -;CHECK: initial begin -;CHECK: #0.002; -;CHECK: for (initvar = 0; initvar < 4; initvar = initvar+1) -;CHECK: m[initvar] = {1{$random}}; -;CHECK: end -;CHECK: `endif -;CHECK: always @(posedge m_c_clk) begin -;CHECK: GEN_0 <= m_c_addr; -;CHECK: GEN_1 <= m_c_en; -;CHECK: end -;CHECK: endmodule diff --git a/test/passes/to-verilog/rdwr-mem.fir b/test/passes/to-verilog/rdwr-mem.fir deleted file mode 100644 index c7897163..00000000 --- a/test/passes/to-verilog/rdwr-mem.fir +++ /dev/null @@ -1,61 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog &> %s.out ; cat %s.v | FileCheck %s - -circuit top : - module top : - output rdata : UInt<32> - input wdata : UInt<32> - input index : UInt<2> - input ren : UInt<1> - input wen : UInt<1> - input clk : Clock - - smem m : UInt<32>[4] - infer mport c = m[index],clk - rdata is invalid - when ren : - rdata <= c - when wen : - c <= wdata - - -;CHECK: module top( -;CHECK: output [31:0] rdata, -;CHECK: input [31:0] wdata, -;CHECK: input [1:0] index, -;CHECK: input ren, -;CHECK: input wen, -;CHECK: input clk -;CHECK: ); -;CHECK: reg [31:0] m [0:3]; -;CHECK: wire m_c_wmode; -;CHECK: wire [31:0] m_c_rdata; -;CHECK: wire [31:0] m_c_data; -;CHECK: wire m_c_mask; -;CHECK: wire [1:0] m_c_addr; -;CHECK: wire m_c_en; -;CHECK: wire m_c_clk; -;CHECK: reg [1:0] GEN_0; -;CHECK: assign rdata = m_c_rdata; -;CHECK: assign m_c_clk = clk; -;CHECK: assign m_c_addr = index; -;CHECK: assign m_c_data = wdata; -;CHECK: assign m_c_addr = index; -;CHECK: assign m_c_mask = wen ? 1'h1 : 1'h0; -;CHECK: assign m_c_en = 1'h1; -;CHECK: assign m_c_wmode = wen ? 1'h1 : 1'h0; -;CHECK: assign m_c_rdata = m[GEN_0]; -;CHECK: `ifndef SYNTHESIS -;CHECK: integer initvar; -;CHECK: initial begin -;CHECK: #0.002; -;CHECK: for (initvar = 0; initvar < 4; initvar = initvar+1) -;CHECK: m[initvar] = {1{$random}}; -;CHECK: end -;CHECK: `endif -;CHECK: always @(posedge m_c_clk) begin -;CHECK: GEN_0 <= m_c_addr; -;CHECK: if(m_c_en & m_c_mask & m_c_wmode) begin -;CHECK: m[m_c_addr] <= m_c_data; -;CHECK: end -;CHECK: end -;CHECK: endmodule diff --git a/test/passes/to-verilog/shr.fir b/test/passes/to-verilog/shr.fir deleted file mode 100644 index 6921e74e..00000000 --- a/test/passes/to-verilog/shr.fir +++ /dev/null @@ -1,35 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s - -;CHECK: Lower Types -;CHECK: node T_928 = bits(s1_req_addr, 11, 0) -;CHECK: node s1_addr = cat(dtlb.resp_ppn, T_928) -;CHECK: Finished Lower Types - -circuit HellaCache : - module TLB_60 : - output resp : {ppn : UInt<20>} - resp.ppn <= UInt<1>("h00") - - module HellaCache : - input clock : Clock - input reset : UInt<1> - - inst dtlb of TLB_60 - poison init : {addr : UInt<40>} - reg s1_req : {addr : UInt<40>}, clock with : - reset => ( reset, init) - reg s2_req : {addr : UInt<40>}, clock with : - reset => ( reset, init) - reg s1_clk_en : UInt<1>, clock with : - reset => ( reset, UInt(0)) - - node T_928 = bits(s1_req.addr, 11, 0) - node s1_addr = cat(dtlb.resp.ppn, T_928) - when s1_clk_en : - s2_req.addr <= s1_addr - - s1_req.addr <= UInt<?>(0) - s1_clk_en <= UInt<?>(0) - - wire foo : UInt<28> - foo <= shr(s1_addr, 3) diff --git a/test/passes/to-verilog/signed-and.fir b/test/passes/to-verilog/signed-and.fir deleted file mode 100644 index ffb7bd23..00000000 --- a/test/passes/to-verilog/signed-and.fir +++ /dev/null @@ -1,17 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog ; cat %s.v | FileCheck %s - -circuit Top : - module Top : - input a : SInt<2> - output c : UInt<2> - c <= and(a,asSInt(UInt(2))) - -; CHECK: module Top( -; CHECK: input [1:0] a, -; CHECK: output [1:0] c -; CHECK: ); -; CHECK: wire [1:0] GEN_0; -; CHECK: assign c = $signed(a) & $signed(GEN_0); -; CHECK: assign GEN_0 = $signed(2'h2); -; CHECK: endmodule - diff --git a/test/passes/to-verilog/wr-mem.fir b/test/passes/to-verilog/wr-mem.fir deleted file mode 100644 index 8c197265..00000000 --- a/test/passes/to-verilog/wr-mem.fir +++ /dev/null @@ -1,45 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog &> %s.out ; cat %s.v | FileCheck %s - -circuit top : - module top : - input wdata : UInt<32> - input index : UInt<2> - input wen : UInt<1> - input clk : Clock - - smem m : UInt<32>[4] - write mport c = m[index],clk - when wen : - c <= wdata - -;CHECK: module top( -;CHECK: input [31:0] wdata, -;CHECK: input [1:0] index, -;CHECK: input wen, -;CHECK: input clk -;CHECK: ); -;CHECK: reg [31:0] m [0:3]; -;CHECK: wire [31:0] m_c_data; -;CHECK: wire [1:0] m_c_addr; -;CHECK: wire m_c_mask; -;CHECK: wire m_c_en; -;CHECK: wire m_c_clk; -;CHECK: assign m_c_data = wdata; -;CHECK: assign m_c_addr = index; -;CHECK: assign m_c_mask = wen ? 1'h1 : 1'h0; -;CHECK: assign m_c_en = 1'h1; -;CHECK: assign m_c_clk = clk; -;CHECK: `ifndef SYNTHESIS -;CHECK: integer initvar; -;CHECK: initial begin -;CHECK: #0.002; -;CHECK: for (initvar = 0; initvar < 4; initvar = initvar+1) -;CHECK: m[initvar] = {1{$random}}; -;CHECK: end -;CHECK: `endif -;CHECK: always @(posedge m_c_clk) begin -;CHECK: if(m_c_en & m_c_mask) begin -;CHECK: m[m_c_addr] <= m_c_data; -;CHECK: end -;CHECK: end -;CHECK: endmodule diff --git a/test/performance/Vector1000.fir b/test/performance/Vector1000.fir deleted file mode 100644 index 767645bb..00000000 --- a/test/performance/Vector1000.fir +++ /dev/null @@ -1,7 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog 2>&1 | tee %s.out | FileCheck %s -; CHECK: Done! -circuit Top : - module Top : - input in1 : UInt<32>[1000] - output out : UInt<32>[1000] - out <= in1 diff --git a/test/performance/Vector2000.fir b/test/performance/Vector2000.fir deleted file mode 100644 index 06a4eb13..00000000 --- a/test/performance/Vector2000.fir +++ /dev/null @@ -1,7 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog 2>&1 | tee %s.out | FileCheck %s -; CHECK: Done! -circuit Top : - module Top : - input in1 : UInt<32>[2000] - output out : UInt<32>[2000] - out <= in1 diff --git a/test/performance/Vector4000.fir b/test/performance/Vector4000.fir deleted file mode 100644 index 73b98e36..00000000 --- a/test/performance/Vector4000.fir +++ /dev/null @@ -1,7 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog 2>&1 | tee %s.out | FileCheck %s -; CHECK: Done! -circuit Top : - module Top : - input in1 : UInt<32>[4000] - output out : UInt<32>[4000] - out <= in1 diff --git a/test/performance/Vector8000.fir b/test/performance/Vector8000.fir deleted file mode 100644 index 24bdfad1..00000000 --- a/test/performance/Vector8000.fir +++ /dev/null @@ -1,7 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog 2>&1 | tee %s.out | FileCheck %s -; CHECK: Done! -circuit Top : - module Top : - input in1 : UInt<32>[8000] - output out : UInt<32>[8000] - out <= in1 diff --git a/utils/bin/FileCheck_linux b/utils/bin/FileCheck_linux Binary files differdeleted file mode 100755 index 1bb70b6d..00000000 --- a/utils/bin/FileCheck_linux +++ /dev/null diff --git a/utils/bin/FileCheck_mac b/utils/bin/FileCheck_mac Binary files differdeleted file mode 100755 index 2ab52bb6..00000000 --- a/utils/bin/FileCheck_mac +++ /dev/null diff --git a/utils/bin/firrtl-scala b/utils/bin/firrtl index f955b9ee..f955b9ee 100755 --- a/utils/bin/firrtl-scala +++ b/utils/bin/firrtl diff --git a/utils/stanza-wrapper b/utils/stanza-wrapper deleted file mode 100755 index 10c8b204..00000000 --- a/utils/stanza-wrapper +++ /dev/null @@ -1,3 +0,0 @@ -#!/bin/bash - -eval '@@TOP@@/src/lib/stanza/stanza' -platform linux "$@" |