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-rw-r--r--test/features/InitAccessor.fir13
1 files changed, 0 insertions, 13 deletions
diff --git a/test/features/InitAccessor.fir b/test/features/InitAccessor.fir
deleted file mode 100644
index 6261ec01..00000000
--- a/test/features/InitAccessor.fir
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@@ -1,13 +0,0 @@
-; RUN: firrtl -i %s -o %s.v -X verilog -p cT 2>&1 | tee %s.out | FileCheck %s
-
-;CHECK: Done!
-circuit Top :
- module Top :
- input in : UInt<1>
- wire b : UInt<1>[3]
- b[0] <= UInt(1)
- b[1] <= UInt(1)
- b[2] <= UInt(1)
- node c = UInt(1)
- when in :
- b[c] <= UInt(1)