diff options
Diffstat (limited to 'test/features')
27 files changed, 0 insertions, 586 deletions
diff --git a/test/features/BigInt.fir b/test/features/BigInt.fir deleted file mode 100644 index 9060d705..00000000 --- a/test/features/BigInt.fir +++ /dev/null @@ -1,10 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p cT 2>&1 | tee %s.out | FileCheck %s -circuit Top : - module Top : - node x = UInt("h2") - node y = UInt("h100000") - node z = UInt("h00") - -;CHECK: node x = UInt<2>("h2") -;CHECK: node z = UInt<1>("h0") -;CHECK: Done! diff --git a/test/features/BulkConnect.fir b/test/features/BulkConnect.fir deleted file mode 100644 index 1b68bbdc..00000000 --- a/test/features/BulkConnect.fir +++ /dev/null @@ -1,39 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: Expand Connects -circuit Top : - module Top : - wire a : { w : UInt} - a.w <= UInt(1) - wire b : { w : UInt<42>, x : UInt<20>} - b.w <= UInt(1) - b.x <= UInt(1) - a <- b - ; CHECK: a.w <= b.w - ; CHECK-NOT: a.x <= b.x - ; CHECK-NOT: a.y <= b.y - ; CHECK-NOT: b.y <= a.y - ; CHECK-NOT: a.z <= b.z - - - wire c : { x : { y : UInt<1>, z : UInt<1>}}[4] - c[0].x.z <= UInt(1) - c[1].x.z <= UInt(1) - c[2].x.y <= UInt(1) - c[2].x.z <= UInt(1) - c[3].x.y <= UInt(1) - c[3].x.z <= UInt(1) - wire d : { x : { y : UInt<1>}}[2] - d[0].x.y <= UInt(1) - d[1].x.y <= UInt(1) - c <- d - ; CHECK: c[0].x.y <= d[0].x.y - ; CHECK: c[1].x.y <= d[1].x.y - ; CHECK-NOT: c[2].x.y <= d[2].x.y - ; CHECK-NOT: c[3].x.y <= d[3].x.y - ; CHECK-NOT: c[0].x.z <= d[0].x.z - ; CHECK-NOT: c[1].x.z <= d[1].x.z - ; CHECK-NOT: c[2].x.z <= d[2].x.z - ; CHECK-NOT: c[3].x.z <= d[3].x.z - -;CHECK: Finished Expand Connects -;CHECK: Done! diff --git a/test/features/DeadCodeElimination.fir b/test/features/DeadCodeElimination.fir deleted file mode 100644 index e67deebf..00000000 --- a/test/features/DeadCodeElimination.fir +++ /dev/null @@ -1,10 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; XFAIL: * - -circuit top : - module top : - input clk : Clock - input reset : UInt<1> - wire x : UInt<1> - -; CHECK: Done! diff --git a/test/features/EmptyStmt.fir b/test/features/EmptyStmt.fir deleted file mode 100644 index 5fb265c0..00000000 --- a/test/features/EmptyStmt.fir +++ /dev/null @@ -1,11 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: Done! -circuit Top : - module Top : - skip - when UInt(1) : - skip - else : - skip - skip - diff --git a/test/features/ExModule.fir b/test/features/ExModule.fir deleted file mode 100644 index b31c77c9..00000000 --- a/test/features/ExModule.fir +++ /dev/null @@ -1,14 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -circuit Top : - module Top : - output z : UInt<4> - inst i of BlackBox - i.x <= UInt(1) - i.y <= UInt(2) - z <= i.z - extmodule BlackBox : - input x : UInt<4> - input y : UInt<4> - output z : UInt<4> - -;CHECK: Done! diff --git a/test/features/InitAccessor.fir b/test/features/InitAccessor.fir deleted file mode 100644 index 6261ec01..00000000 --- a/test/features/InitAccessor.fir +++ /dev/null @@ -1,13 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p cT 2>&1 | tee %s.out | FileCheck %s - -;CHECK: Done! -circuit Top : - module Top : - input in : UInt<1> - wire b : UInt<1>[3] - b[0] <= UInt(1) - b[1] <= UInt(1) - b[2] <= UInt(1) - node c = UInt(1) - when in : - b[c] <= UInt(1) diff --git a/test/features/InitializeVec.fir b/test/features/InitializeVec.fir deleted file mode 100644 index 1cc44daf..00000000 --- a/test/features/InitializeVec.fir +++ /dev/null @@ -1,21 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s - -;CHECK: Done! -circuit Tst : - module Tst : - input in : {valid : UInt<1>, flip ready : UInt<1>, bits : UInt<8>} - output outs : {valid : UInt<1>, flip ready : UInt<1>, bits : UInt<8>}[4] - - in.ready <= UInt<1>(1) - outs[0].valid <= UInt<1>(0) - outs[0].bits <= UInt<1>(0) - outs[1].valid <= UInt<1>(0) - outs[1].bits <= UInt<1>(0) - outs[2].valid <= UInt<1>(0) - outs[2].bits <= UInt<1>(0) - outs[3].valid <= UInt<1>(0) - outs[3].bits <= UInt<1>(0) - in.ready <= UInt<1>(1) - when outs[in.bits].ready : - outs[in.bits].bits <= UInt<7>(99) - outs[in.bits].valid <= UInt<1>(1) diff --git a/test/features/IsInvalid.fir b/test/features/IsInvalid.fir deleted file mode 100644 index dc7c56b4..00000000 --- a/test/features/IsInvalid.fir +++ /dev/null @@ -1,74 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -circuit Top : - module Top : - input clk : Clock - input reset : UInt<1> - input a : { w : UInt<42>, flip x : UInt<30>}[2] - output b : { w : UInt<42>, flip x : UInt<30>}[2] - mem m : - depth => 10 - data-type => UInt<32>[4] - read-latency => 0 - write-latency => 1 - reader => r - writer => w - readwriter => rw - wire x : { w : UInt<42>, x : UInt<20>} - reg c : { w : UInt<42>, x : UInt<20>},clk with : - reset => (reset,x) - inst other of Other - - clk is invalid - reset is invalid - a is invalid - b is invalid - m is invalid - x is invalid - c is invalid - other is invalid - module Other : - input a : { w : UInt<42>, flip x : UInt<30>} - output b : { w : UInt<42>, flip x : UInt<30>} - b <= a - - -;CHECK: Expand Connects -;CHECK: skip -;CHECK: skip -;CHECK: a[0].x is invalid -;CHECK: a[1].x is invalid -;CHECK: b[0].w is invalid -;CHECK: b[1].w is invalid -;CHECK: m.r.addr is invalid -;CHECK: m.r.en is invalid -;CHECK: m.r.clk is invalid -;CHECK: m.w.data[0] is invalid -;CHECK: m.w.data[1] is invalid -;CHECK: m.w.data[2] is invalid -;CHECK: m.w.data[3] is invalid -;CHECK: m.w.mask[0] is invalid -;CHECK: m.w.mask[1] is invalid -;CHECK: m.w.mask[2] is invalid -;CHECK: m.w.mask[3] is invalid -;CHECK: m.w.addr is invalid -;CHECK: m.w.en is invalid -;CHECK: m.w.clk is invalid -;CHECK: m.rw.wmode is invalid -;CHECK: m.rw.data[0] is invalid -;CHECK: m.rw.data[1] is invalid -;CHECK: m.rw.data[2] is invalid -;CHECK: m.rw.data[3] is invalid -;CHECK: m.rw.mask[0] is invalid -;CHECK: m.rw.mask[1] is invalid -;CHECK: m.rw.mask[2] is invalid -;CHECK: m.rw.mask[3] is invalid -;CHECK: m.rw.addr is invalid -;CHECK: m.rw.en is invalid -;CHECK: m.rw.clk is invalid -;CHECK: x.w is invalid -;CHECK: x.x is invalid -;CHECK: c.w is invalid -;CHECK: c.x is invalid -;CHECK: other.a.w is invalid -;CHECK: other.b.x is invalid -;CHECK: Done! diff --git a/test/features/Link.fir b/test/features/Link.fir deleted file mode 100644 index 57fb8605..00000000 --- a/test/features/Link.fir +++ /dev/null @@ -1,14 +0,0 @@ -; RUN: firrtl -i %s -m %S/Queue.fir -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: Done! -circuit Top : - module Top : - input clk : Clock - input reset : UInt<1> - output out : UInt<10> - - inst q of Queue - q.clk <= clk - q.reset <= reset - q.in <= UInt(1) - out <= q.out - diff --git a/test/features/Long.fir b/test/features/Long.fir deleted file mode 100644 index 7ac5ad6c..00000000 --- a/test/features/Long.fir +++ /dev/null @@ -1,6 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: Done -circuit Top : - module Top : - wire a : UInt - a <= UInt("h4261441663") diff --git a/test/features/MemSize1.fir b/test/features/MemSize1.fir deleted file mode 100644 index a29d3fc5..00000000 --- a/test/features/MemSize1.fir +++ /dev/null @@ -1,11 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: Done! -circuit Top : - module Top : - input clk : Clock - output out : UInt<32> - input i : UInt<1> - cmem m : UInt<32>[1] - read mport r = m[i],clk - out <= r - diff --git a/test/features/MuxBundle.fir b/test/features/MuxBundle.fir deleted file mode 100644 index 764078d5..00000000 --- a/test/features/MuxBundle.fir +++ /dev/null @@ -1,16 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: Expand Connects -circuit Top : - module Top : - input a: {w:UInt<42>,x:UInt<20>} - input b: {w:UInt<42>,x:UInt<20>} - input c: {w:UInt<42>,x:UInt<20>} - input p : UInt<1> - output d: {w:UInt<42>,x:UInt<20>} - d <= mux(p,mux(p,a,b),c) -;CHECK: d.w <= mux(p, mux(p, a.w, b.w), c.w) -;CHECK: d.x <= mux(p, mux(p, a.x, b.x), c.x) - -;CHECK: Finished Expand Connects -;CHECK: Done! - diff --git a/test/features/MuxNodeExamples.fir b/test/features/MuxNodeExamples.fir deleted file mode 100644 index 07fa16b4..00000000 --- a/test/features/MuxNodeExamples.fir +++ /dev/null @@ -1,28 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: Expand Connects -circuit Top : - module Top : - input a : {f:UInt<3>[3], flip g:UInt<3>[3]}[2] - input b : {f:UInt<3>[3], flip g:UInt<3>[3]}[2] - input p : UInt<1> - input i : UInt<1> - b[0].g[0] <= UInt(0) - b[0].g[1] <= UInt(0) - b[0].g[2] <= UInt(0) - b[1].g[0] <= UInt(0) - b[1].g[1] <= UInt(0) - b[1].g[2] <= UInt(0) - a[0].g[0] <= UInt(0) - a[0].g[1] <= UInt(0) - a[0].g[2] <= UInt(0) - a[1].g[0] <= UInt(0) - a[1].g[1] <= UInt(0) - a[1].g[2] <= UInt(0) - node x = mux(p,a[i].f,b[i].f) - - - -;CHECK: Finished Expand Connects -;CHECK: Done! - - diff --git a/test/features/MuxType.fir b/test/features/MuxType.fir deleted file mode 100644 index b0e7e7ef..00000000 --- a/test/features/MuxType.fir +++ /dev/null @@ -1,12 +0,0 @@ - -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: Expand Connects -circuit Top : - module Top : - input a: UInt<1> - input b: UInt<32> - input p : UInt<1> - output d: UInt - node y = mux(p, a, b) - d <= y -;CHECK:Done! diff --git a/test/features/NestedAccess.fir b/test/features/NestedAccess.fir deleted file mode 100644 index bd3c436d..00000000 --- a/test/features/NestedAccess.fir +++ /dev/null @@ -1,31 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p cw 2>&1 | tee %s.out | FileCheck %s -;CHECK: Expand Connects -circuit Top : - module Top : - input i : UInt<1> - input j : UInt<1> - wire a : { x : UInt<42> flip y : UInt<42>[2]}[2][3] - wire b : { x : UInt<42> flip y : UInt<42>[2]} - a[0][0].x <= UInt(0) - a[0][0].y[0] <= UInt(0) - a[0][0].y[1] <= UInt(0) - a[0][1].x <= UInt(0) - a[0][1].y[0] <= UInt(0) - a[0][1].y[1] <= UInt(0) - a[1][0].x <= UInt(0) - a[1][0].y[0] <= UInt(0) - a[1][0].y[1] <= UInt(0) - a[1][1].x <= UInt(0) - a[1][1].y[0] <= UInt(0) - a[1][1].y[1] <= UInt(0) - a[2][0].x <= UInt(0) - a[2][0].y[0] <= UInt(0) - a[2][0].y[1] <= UInt(0) - a[2][1].x <= UInt(0) - a[2][1].y[0] <= UInt(0) - a[2][1].y[1] <= UInt(0) - b.x <= UInt(0) - a[i][j] <= b -;CHECK: Finished Expand Connects -;CHECK: Done! - diff --git a/test/features/NestedSubAccessTester.fir b/test/features/NestedSubAccessTester.fir deleted file mode 100644 index 36465012..00000000 --- a/test/features/NestedSubAccessTester.fir +++ /dev/null @@ -1,27 +0,0 @@ -circuit NestedSubAccessTester : - module NestedSubAccess : - input foo : UInt<1>[4] - input index : UInt<2> - output out : UInt<4> - - wire vec : UInt<4>[2] - vec[0] <= UInt(3) - vec[1] <= UInt(4) - - out <= vec[foo[index]] - - module NestedSubAccessTester : - input clk : Clock - input reset : UInt<1> - - inst dut of NestedSubAccess - - dut.foo is invalid - dut.index <= UInt(2) - dut.foo[2] <= UInt(1) - - when neq(dut.out, UInt(4)) : - printf(clk, not(reset), "Assertion failed\nTest Failed!\n") - stop(clk, not(reset), 1) - else : - stop(clk, not(reset), 0) diff --git a/test/features/NodeBundle.fir b/test/features/NodeBundle.fir deleted file mode 100644 index c4c33107..00000000 --- a/test/features/NodeBundle.fir +++ /dev/null @@ -1,12 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: Lower Types -circuit Top : - module Top : - input a: {w:UInt<42>,x:UInt<20>} - node d = a -;CHECK: node d_w = a_w -;CHECK: node d_x = a_x - -;CHECK: Finished Lower Types -;CHECK: Done! - diff --git a/test/features/OptionalRegisterReset.fir b/test/features/OptionalRegisterReset.fir deleted file mode 100644 index 54a90b67..00000000 --- a/test/features/OptionalRegisterReset.fir +++ /dev/null @@ -1,17 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -circuit Top : - module Top : - input clk : Clock - input reset : UInt<1> - input a : UInt<32> - input p : UInt<1> - output b : UInt<32> - reg r1:UInt<32> clk with : - reset => (reset, a) - when p : - b <= r1 - else : - b <= r1 - - -;CHECK: Done! diff --git a/test/features/Poison.fir b/test/features/Poison.fir deleted file mode 100644 index 9aafe63f..00000000 --- a/test/features/Poison.fir +++ /dev/null @@ -1,39 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; CHECK: Done! -circuit Poison : - module Poison : - input clk : Clock - input reset : UInt<1> - input index : UInt<7> - input wmask : {x:UInt<1>, y:UInt<1>} - input p : UInt<1> - output out : {x : UInt<10>, y : UInt<10>} - poison q : {x : UInt<10>, y : UInt<10>} - mem m : - data-type => {x : UInt<10>, y : UInt<10>} - depth => 128 - read-latency => 1 - write-latency => 2 - reader => r - writer => w - readwriter => rw - m.r.addr <= index - m.r.en <= UInt(1) - m.r.clk <= clk - m.w.addr <= index - m.w.en <= UInt(1) - m.w.mask <= wmask - m.w.clk <= clk - m.w.data <= q - - m.rw.clk <= clk - m.rw.addr <= index - m.rw.en <= UInt(1) - m.rw.wmode <= UInt(1) - m.rw.mask <= wmask - m.rw.data <= q - when p : - out <= m.r.data - else : - out <= q - diff --git a/test/features/Printf.fir b/test/features/Printf.fir deleted file mode 100644 index 912023af..00000000 --- a/test/features/Printf.fir +++ /dev/null @@ -1,21 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s - -;CHECK: Expand Whens -circuit Top : - module Top : - input x : {y : UInt<1>} - input p : UInt<1> - input clk : Clock - input en : UInt<1> - printf(clk,en,"Hello World!\n") - printf(clk,en,"Hello World! %x\n", x.y) - when p : - printf(clk,en,"In consequence\n") - else : - printf(clk,en,"In alternate\n") - -;CHECK: printf(clk, en, "Hello World!\n") -;CHECK: printf(clk, en, "Hello World! %x\n", x.y) -;CHECK: printf(clk, and(p, en), "In consequence\n") -;CHECK: printf(clk, and(eq(p, UInt<1>("h0")), en), "In alternate\n") -;CHECK: Done! diff --git a/test/features/Queue.fir b/test/features/Queue.fir deleted file mode 100644 index 3ce58e31..00000000 --- a/test/features/Queue.fir +++ /dev/null @@ -1,13 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; CHECK: Done! -circuit Queue : - module Queue : - input in : UInt<10> - output out : UInt<10> - input clk : Clock - input reset : UInt<1> - - reg r : UInt<10>,clk with : - reset => (reset,in) - r <= in - out <= r diff --git a/test/features/SeqMem.fir b/test/features/SeqMem.fir deleted file mode 100644 index d97435af..00000000 --- a/test/features/SeqMem.fir +++ /dev/null @@ -1,46 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: Done! -circuit Top : - module Top : - input clk : Clock - wire i : UInt<5> - i <= UInt(1) - wire i0 : UInt<5> - wire j : UInt<128> - - i0 <= UInt(10) - - mem m-com : - data-type => UInt<128> - depth => 32 - reader => r - writer => w - read-latency => 0 - write-latency => 1 - m-com.r.addr <= i - m-com.r.en <= UInt(1) - m-com.r.clk <= clk - m-com.w.addr <= i - m-com.w.mask <= UInt(1) - m-com.w.en <= UInt(1) - m-com.w.clk <= clk - j <= m-com.r.data - m-com.w.data <= j - - - mem m-seq : - data-type => UInt<128> - depth => 32 - reader => r - writer => w - read-latency => 1 - write-latency => 1 - m-seq.r.addr <= i - m-seq.r.en <= UInt(1) - m-seq.r.clk <= clk - m-seq.w.addr <= i - m-seq.w.mask <= UInt(1) - m-seq.w.en <= UInt(1) - m-seq.w.clk <= clk - j <= m-seq.r.data - m-seq.w.data <= j diff --git a/test/features/Stop.fir b/test/features/Stop.fir deleted file mode 100644 index 888da3d7..00000000 --- a/test/features/Stop.fir +++ /dev/null @@ -1,20 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s - -;CHECK: Expand Whens - -circuit Top : - module Top : - input p : UInt<1> - input q : UInt<1> - input clk : Clock - when p : - stop(clk,UInt(1),0) - when q : - stop(clk,UInt(1),1) - stop(clk,UInt(1),3) - -;CHECK: stop(clk, p, 0) -;CHECK: stop(clk, q, 1) -;CHECK: stop(clk, UInt<1>("h1"), 3) -;CHECK: Done! - diff --git a/test/features/TwoClocks.fir b/test/features/TwoClocks.fir deleted file mode 100644 index 3753ee8d..00000000 --- a/test/features/TwoClocks.fir +++ /dev/null @@ -1,24 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -circuit Top : - module Top : - input clk1 : Clock - input clk2 : Clock - input reset1 : UInt<1> - input reset2 : UInt<1> - reg src : UInt<10>, clk1 with : - reset => ( reset1, UInt(0)) - reg sink : UInt<10>, clk2 with : - reset => ( reset2, UInt(0)) - - src <= add(src,UInt(1)) - - reg sync_A : UInt<10>, clk2 with : - reset => ( reset2, UInt(0)) - sync_A <= src - reg sync_B : UInt<10>, clk2 with : - reset => ( reset2, UInt(0)) - sync_B <= sync_A - - sink <= sync_B - -;CHECK: Done! diff --git a/test/features/ValidIf.fir b/test/features/ValidIf.fir deleted file mode 100644 index 70c69313..00000000 --- a/test/features/ValidIf.fir +++ /dev/null @@ -1,21 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -circuit Top : - module Top : - input clk : Clock - input reset : UInt<1> - input a : { w : UInt<42>, x : UInt<30>}[2] - input b : { w : UInt<42>, x : UInt<30>}[2] - input p: UInt<1> - input q: UInt<1> - output c : { w : UInt<42>, x : UInt<30>}[2] - output d : { w : UInt<42>, x : UInt<30>}[2] - - c is invalid - when p : - when q : - c <= a - else : - c <= b - d <= validif(p,b) - -;CHECK: Done! diff --git a/test/features/VerilogReg.fir b/test/features/VerilogReg.fir deleted file mode 100644 index 96022933..00000000 --- a/test/features/VerilogReg.fir +++ /dev/null @@ -1,18 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; CHECK: Done! -circuit Poison : - module Poison : - input clk : Clock - input reset : UInt<1> - input p1 : UInt<1> - input p2 : UInt<1> - input p3 : UInt<1> - reg r : UInt<32>,clk with : - reset => (reset,r) - when p1 : - r <= UInt(1) - when p2 : - r <= UInt(2) - when p3 : - r <= UInt(3) - diff --git a/test/features/VerilogRename.fir b/test/features/VerilogRename.fir deleted file mode 100644 index f8fceaa9..00000000 --- a/test/features/VerilogRename.fir +++ /dev/null @@ -1,18 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -circuit Top : - module Top : - input with : Clock - output unsigned : Clock - wire trireg : Clock - unsigned <= with - trireg <= with - -;CHECK: Verilog Rename - -;CHECK: input with$ : Clock -;CHECK: output unsigned$ : Clock -;CHECK: wire trireg$ : Clock -;CHECK: trireg$ <= with$ -;CHECK: unsigned$ <= with$ - -;CHECK: Done! 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