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Diffstat (limited to 'test/features/NestedAccess.fir')
| -rw-r--r-- | test/features/NestedAccess.fir | 31 |
1 files changed, 0 insertions, 31 deletions
diff --git a/test/features/NestedAccess.fir b/test/features/NestedAccess.fir deleted file mode 100644 index bd3c436d..00000000 --- a/test/features/NestedAccess.fir +++ /dev/null @@ -1,31 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p cw 2>&1 | tee %s.out | FileCheck %s -;CHECK: Expand Connects -circuit Top : - module Top : - input i : UInt<1> - input j : UInt<1> - wire a : { x : UInt<42> flip y : UInt<42>[2]}[2][3] - wire b : { x : UInt<42> flip y : UInt<42>[2]} - a[0][0].x <= UInt(0) - a[0][0].y[0] <= UInt(0) - a[0][0].y[1] <= UInt(0) - a[0][1].x <= UInt(0) - a[0][1].y[0] <= UInt(0) - a[0][1].y[1] <= UInt(0) - a[1][0].x <= UInt(0) - a[1][0].y[0] <= UInt(0) - a[1][0].y[1] <= UInt(0) - a[1][1].x <= UInt(0) - a[1][1].y[0] <= UInt(0) - a[1][1].y[1] <= UInt(0) - a[2][0].x <= UInt(0) - a[2][0].y[0] <= UInt(0) - a[2][0].y[1] <= UInt(0) - a[2][1].x <= UInt(0) - a[2][1].y[0] <= UInt(0) - a[2][1].y[1] <= UInt(0) - b.x <= UInt(0) - a[i][j] <= b -;CHECK: Finished Expand Connects -;CHECK: Done! - |
