Updated all tests to pass

47 files changed, 270 insertions, 222 deletions

diff --git a/test/chirrtl/wacc-wdc.fir b/test/chirrtl/wacc-wdc.fir
index 779722da..b66799b3 100644
--- a/test/chirrtl/wacc-wdc.fir
+++ b/test/chirrtl/wacc-wdc.fir
@@ -24,11 +24,11 @@ circuit top :
 ; CHECK:       wire p : UInt
 ; CHECK:       wire q : UInt
 ; CHECK:       mem m :          
-; CHECK:          data-type: { a : UInt<4>,  b : UInt<4>}
-; CHECK:          depth: 10
-; CHECK:          write-latency: 1
-; CHECK:          read-latency: 0
-; CHECK:          writer: a
+; CHECK:          data-type => { a : UInt<4>,  b : UInt<4>}
+; CHECK:          depth => 10
+; CHECK:          write-latency => 1
+; CHECK:          read-latency => 0
+; CHECK:          writer => a
 ; CHECK:       poison GEN_0 : UInt<4>
 ; CHECK:       poison GEN_1 : { a : UInt<4>,  b : UInt<4>}
 ; CHECK:       m.a.addr <= GEN_0
diff --git a/test/errors/gender/BulkWrong.fir b/test/errors/gender/BulkWrong.fir
index 1becd104..c9b24aa2 100644
--- a/test/errors/gender/BulkWrong.fir
+++ b/test/errors/gender/BulkWrong.fir
@@ -18,7 +18,7 @@ circuit BTB :
     in.y <- w.y
     in.y.z <- w.y.z
 
-    w.x <= addw(in.x,in.y.z)
+    w.x <= add(in.x,in.y.z)
 
     out <- in
     in.y <- out.y
diff --git a/test/errors/high-form/RemoveChar.fir b/test/errors/high-form/RemoveChar.fir
index 9341468c..aa5e8227 100644
--- a/test/errors/high-form/RemoveChar.fir
+++ b/test/errors/high-form/RemoveChar.fir
@@ -6,7 +6,7 @@ circuit Top :
     wire x_1 : UInt<1>
     x_1 <= UInt(1)
     wire x : UInt<1>
-    x <= addw(addw(UInt(1),UInt(1)),UInt(1))
+    x <= add(add(UInt(1),UInt(1)),UInt(1))
 
 
 
diff --git a/test/features/IsInvalid.fir b/test/features/IsInvalid.fir
index cf898fe9..f6766bf2 100644
--- a/test/features/IsInvalid.fir
+++ b/test/features/IsInvalid.fir
@@ -12,9 +12,10 @@ circuit Top :
        write-latency => 1
        reader => r
        writer => w
-       read-writer => rw
+       readwriter => rw
     wire x : { w : UInt<42>, x : UInt<20>}
-    reg c : { w : UInt<42>, x : UInt<20>},clk,reset,x
+    reg c : { w : UInt<42>, x : UInt<20>},clk with :
+       reset => (reset,x)
     inst other of Other
    
     clk is invalid
diff --git a/test/features/Poison.fir b/test/features/Poison.fir
index a4cb1a25..a2e0acfb 100644
--- a/test/features/Poison.fir
+++ b/test/features/Poison.fir
@@ -16,7 +16,7 @@ circuit Poison :
        write-latency => 2
        reader => r
        writer => w
-       read-writer => rw
+       readwriter => rw
     m.r.addr <= index
     m.r.en <= UInt(1)
     m.r.clk <= clk
diff --git a/test/features/Printf.fir b/test/features/Printf.fir
index 4e8682ff..d4d2f77d 100644
--- a/test/features/Printf.fir
+++ b/test/features/Printf.fir
@@ -17,5 +17,5 @@ circuit Top :
 ;CHECK: printf(clk, en, "Hello World!\n")
 ;CHECK: printf(clk, en, "Hello World! %x\n", x.y)
 ;CHECK: printf(clk, and(p, en), "In consequence\n")
-;CHECK: printf(clk, and(eqv(p, UInt("h0")), en), "In alternate\n")   
+;CHECK: printf(clk, and(eq(p, UInt("h0")), en), "In alternate\n")   
 ;CHECK: Done!
diff --git a/test/features/Queue.fir b/test/features/Queue.fir
index 9b19caf4..3ce58e31 100644
--- a/test/features/Queue.fir
+++ b/test/features/Queue.fir
@@ -7,6 +7,7 @@ circuit Queue :
     input clk : Clock
     input reset : UInt<1>
   
-    reg r : UInt<10>,clk,reset,in
+    reg r : UInt<10>,clk with :
+       reset => (reset,in)
     r <= in
     out <= r
diff --git a/test/features/TwoClocks.fir b/test/features/TwoClocks.fir
index 6562d3e1..3753ee8d 100644
--- a/test/features/TwoClocks.fir
+++ b/test/features/TwoClocks.fir
@@ -5,14 +5,18 @@ circuit Top :
     input clk2 : Clock
     input reset1 : UInt<1>
     input reset2 : UInt<1>
-    reg src : UInt<10>, clk1, reset1, UInt(0)
-    reg sink : UInt<10>, clk2, reset2, UInt(0)
+    reg src : UInt<10>, clk1 with :
+       reset => ( reset1, UInt(0))
+    reg sink : UInt<10>, clk2 with :
+       reset => ( reset2, UInt(0))
 
-    src <= addw(src,UInt(1))
+    src <= add(src,UInt(1))
 
-    reg sync_A : UInt<10>, clk2, reset2, UInt(0)
+    reg sync_A : UInt<10>, clk2 with :
+       reset => ( reset2, UInt(0))
     sync_A <= src
-    reg sync_B : UInt<10>, clk2, reset2, UInt(0)
+    reg sync_B : UInt<10>, clk2 with :
+       reset => ( reset2, UInt(0))
     sync_B <= sync_A
 
     sink <= sync_B
diff --git a/test/features/VerilogReg.fir b/test/features/VerilogReg.fir
index 33c4417f..96022933 100644
--- a/test/features/VerilogReg.fir
+++ b/test/features/VerilogReg.fir
@@ -7,7 +7,8 @@ circuit Poison :
     input p1 : UInt<1>
     input p2 : UInt<1>
     input p3 : UInt<1>
-    reg r : UInt<32>,clk,reset,r
+    reg r : UInt<32>,clk with :
+       reset => (reset,r)
     when p1 :
        r <= UInt(1)
     when p2 :
diff --git a/test/passes/expand-whens/bundle-init.fir b/test/passes/expand-whens/bundle-init.fir
index c4b9f314..f4ae9f6a 100644
--- a/test/passes/expand-whens/bundle-init.fir
+++ b/test/passes/expand-whens/bundle-init.fir
@@ -5,7 +5,8 @@ circuit top :
       input clk : Clock
       input reset : UInt<1>
       wire w : { x : UInt, y : UInt}
-      reg r : { x : UInt, y : UInt},clk,reset,w
+      reg r : { x : UInt, y : UInt},clk with :
+         reset => (reset,w)
       wire a : UInt
       wire b : UInt
       a <= UInt(1)
diff --git a/test/passes/expand-whens/nested-whens.fir b/test/passes/expand-whens/nested-whens.fir
index 9a9d56d4..68409931 100644
--- a/test/passes/expand-whens/nested-whens.fir
+++ b/test/passes/expand-whens/nested-whens.fir
@@ -12,7 +12,8 @@ circuit top :
       wire y : UInt
       wire z : UInt
       wire w : UInt
-      reg r : UInt, clk, reset, w
+      reg r : UInt, clk with :
+         reset => (reset, w)
       p <= UInt(1)
       q <= UInt(1)
       a <= UInt(1)
diff --git a/test/passes/expand-whens/partial-init.fir b/test/passes/expand-whens/partial-init.fir
index 490ac995..2fb54717 100644
--- a/test/passes/expand-whens/partial-init.fir
+++ b/test/passes/expand-whens/partial-init.fir
@@ -17,7 +17,8 @@ circuit top :
       init[7] <= x
       init[8] <= x
       init[9] <= x
-      reg r : UInt<1>[10],clk,reset,init
+      reg r : UInt<1>[10],clk with :
+         reset => (reset,init)
       r[0] <= UInt(1)
       r[1] <= UInt(1)
       r[2] <= UInt(1)
diff --git a/test/passes/expand-whens/reg-dwc.fir b/test/passes/expand-whens/reg-dwc.fir
index 024b527c..e8267861 100644
--- a/test/passes/expand-whens/reg-dwc.fir
+++ b/test/passes/expand-whens/reg-dwc.fir
@@ -5,7 +5,8 @@ circuit top :
       input reset : UInt<1>
       wire p : UInt
       p <= UInt(1)
-      reg r : UInt,clk,reset,r
+      reg r : UInt,clk with :
+         reset => (reset,r)
       when p :
          r <= UInt(2)
 
diff --git a/test/passes/expand-whens/reg-wdc.fir b/test/passes/expand-whens/reg-wdc.fir
index 4ddea427..b19b8bca 100644
--- a/test/passes/expand-whens/reg-wdc.fir
+++ b/test/passes/expand-whens/reg-wdc.fir
@@ -6,7 +6,8 @@ circuit top :
       wire p : UInt
       p <= UInt(1)
       when p :
-         reg r : UInt,clk,reset,r
+         reg r : UInt,clk with :
+            reset => (reset,r)
          r <= UInt(2)
 
 ; CHECK: Expand Whens
@@ -14,7 +15,8 @@ circuit top :
 ; CHECK: circuit top :
 ; CHECK:   module top :
 ; CHECK:     wire p : UInt
-; CHECK:     reg r : UInt<2>, clk, reset, r
+; CHECK:     reg r : UInt<2>, clk with :
+; CHECK:       reset => (reset, r)
 ; CHECK:     p <= UInt("h1")
 ; CHECK-NOT: r <= mux(p, UInt("h2"), r)
 ; CHECK:     r <= UInt("h2")
diff --git a/test/passes/infer-types/gcd.fir b/test/passes/infer-types/gcd.fir
index 938cb345..d419ce35 100644
--- a/test/passes/infer-types/gcd.fir
+++ b/test/passes/infer-types/gcd.fir
@@ -6,8 +6,8 @@ circuit top :
       input x : UInt
       input y : UInt
       output z : UInt
-      z <= subw(x, y)
-      ;CHECK: z@<t:UInt> <= subw(x@<t:UInt>, y@<t:UInt>)@<t:UInt>
+      z <= tail(sub(x, y),1)
+      ;CHECK: z@<t:UInt> <= tail(sub(x@<t:UInt>, y@<t:UInt>)@<t:SInt>, 1)@<t:UInt>   
    module gcd :
       input a : UInt<16>
       input b : UInt<16>
@@ -15,9 +15,12 @@ circuit top :
       input clk : Clock
       input reset : UInt<1>
       output z : UInt<16>
-      reg x : UInt,clk,reset,UInt(0)
-      reg y : UInt,clk,reset,UInt(42)
-      ; CHECK: reg x : UInt, clk@<t:Clock>, reset@<t:UInt>, UInt("h0")@<t:UInt>@<t:UInt>
+      reg x : UInt,clk with :
+         reset => (reset,UInt(0))
+      reg y : UInt,clk with :
+         reset => (reset,UInt(42))
+      ; CHECK: reg x : UInt, clk@<t:Clock> with :
+         ;CHECK:reset => (reset@<t:UInt>, UInt("h0")@<t:UInt>)
       when gt(x, y) :
       ;CHECK: when gt(x@<t:UInt>, y@<t:UInt>)@<t:UInt> :
          inst s of subtracter
diff --git a/test/passes/infer-types/primops.fir b/test/passes/infer-types/primops.fir
index 102a94ae..31846b88 100644
--- a/test/passes/infer-types/primops.fir
+++ b/test/passes/infer-types/primops.fir
@@ -3,6 +3,7 @@
 ;CHECK: Infer Types
 circuit top :
    module top :
+      input clk : Clock
       wire a : UInt<16>
       wire b : UInt<8>
       wire c : SInt<16>
@@ -45,30 +46,6 @@ circuit top :
       node ymod = mod(c, b) ;CHECK: node ymod = mod(c@<t:SInt>, b@<t:UInt>)@<t:SInt>
       node zmod = mod(c, d) ;CHECK: node zmod = mod(c@<t:SInt>, d@<t:SInt>)@<t:SInt>
    
-      node vquo = quo(a, c)    ;CHECK: node vquo = quo(a@<t:UInt>, c@<t:SInt>)@<t:SInt>
-      node wquo = quo(a, b) ;CHECK: node wquo = quo(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
-      node xquo = quo(a, d) ;CHECK: node xquo = quo(a@<t:UInt>, d@<t:SInt>)@<t:SInt>
-      node yquo = quo(c, b) ;CHECK: node yquo = quo(c@<t:SInt>, b@<t:UInt>)@<t:SInt>
-      node zquo = quo(c, d) ;CHECK: node zquo = quo(c@<t:SInt>, d@<t:SInt>)@<t:SInt>
-   
-      node vrem = rem(a, c)    ;CHECK: node vrem = rem(a@<t:UInt>, c@<t:SInt>)@<t:SInt>
-      node wrem = rem(a, b) ;CHECK: node wrem = rem(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
-      node xrem = rem(a, d) ;CHECK: node xrem = rem(a@<t:UInt>, d@<t:SInt>)@<t:SInt>
-      node yrem = rem(c, b) ;CHECK: node yrem = rem(c@<t:SInt>, b@<t:UInt>)@<t:UInt>
-      node zrem = rem(c, d) ;CHECK: node zrem = rem(c@<t:SInt>, d@<t:SInt>)@<t:SInt>
-   
-      node vaddw = addw(a, c)    ;CHECK: node vaddw = addw(a@<t:UInt>, c@<t:SInt>)@<t:SInt>
-      node waddw = addw(a, b) ;CHECK: node waddw = addw(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
-      node xaddw = addw(a, d) ;CHECK: node xaddw = addw(a@<t:UInt>, d@<t:SInt>)@<t:SInt>
-      node yaddw = addw(c, b) ;CHECK: node yaddw = addw(c@<t:SInt>, b@<t:UInt>)@<t:SInt>
-      node zaddw = addw(c, d) ;CHECK: node zaddw = addw(c@<t:SInt>, d@<t:SInt>)@<t:SInt>
-   
-      node vsubw = subw(a, c)    ;CHECK: node vsubw = subw(a@<t:UInt>, c@<t:SInt>)@<t:SInt>
-      node wsubw = subw(a, b) ;CHECK: node wsubw = subw(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
-      node xsubw = subw(a, d) ;CHECK: node xsubw = subw(a@<t:UInt>, d@<t:SInt>)@<t:SInt>
-      node ysubw = subw(c, b) ;CHECK: node ysubw = subw(c@<t:SInt>, b@<t:UInt>)@<t:SInt>
-      node zsubw = subw(c, d) ;CHECK: node zsubw = subw(c@<t:SInt>, d@<t:SInt>)@<t:SInt>
-   
       node vlt = lt(a, c)    ;CHECK: node vlt = lt(a@<t:UInt>, c@<t:SInt>)@<t:UInt>
       node wlt = lt(a, b) ;CHECK: node wlt = lt(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
       node xlt = lt(a, d) ;CHECK: node xlt = lt(a@<t:UInt>, d@<t:SInt>)@<t:UInt>
@@ -105,29 +82,21 @@ circuit top :
       node yneq = neq(c, b) ;CHECK: node yneq = neq(c@<t:SInt>, b@<t:UInt>)@<t:UInt>
       node zneq = neq(c, d) ;CHECK: node zneq = neq(c@<t:SInt>, d@<t:SInt>)@<t:UInt>
    
-      node vneqv = neqv(a, b)    ;CHECK: node vneqv = neqv(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
-      node wneqv = neqv(a, b) ;CHECK: node wneqv = neqv(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
-      node zneqv = neqv(c, d) ;CHECK: node zneqv = neqv(c@<t:SInt>, d@<t:SInt>)@<t:UInt>
-   
-      node veqv = eqv(a, b)    ;CHECK: node veqv = eqv(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
-      node weqv = eqv(a, b) ;CHECK: node weqv = eqv(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
-      node zeqv = eqv(c, d) ;CHECK: node zeqv = eqv(c@<t:SInt>, d@<t:SInt>)@<t:UInt>
-   
-      node vmux = mux(e, a, b)    ;CHECK: node vmux = mux(e@<t:UInt>, a@<t:UInt>, b@<t:UInt>)@<t:UInt>
-      node wmux = mux(e, a, b) ;CHECK: node wmux = mux(e@<t:UInt>, a@<t:UInt>, b@<t:UInt>)@<t:UInt>
-      node zmux = mux(e, c, d) ;CHECK: node zmux = mux(e@<t:UInt>, c@<t:SInt>, d@<t:SInt>)@<t:SInt>
-   
       node vpad = pad(a, 10)   ;CHECK: node vpad = pad(a@<t:UInt>, 10)@<t:UInt>
       node wpad = pad(a, 10) ;CHECK: node wpad = pad(a@<t:UInt>, 10)@<t:UInt>
       node zpad = pad(c, 10) ;CHECK: node zpad = pad(c@<t:SInt>, 10)@<t:SInt>
    
-      node vasUInt = asUInt(d)   ;CHECK: node vasUInt = asUInt(d@<t:SInt>)@<t:UInt>
+      node vasUInt = asUInt(d) ;CHECK: node vasUInt = asUInt(d@<t:SInt>)@<t:UInt>
       node wasUInt = asUInt(a) ;CHECK: node wasUInt = asUInt(a@<t:UInt>)@<t:UInt>
-      node zasUInt = asUInt(c) ;CHECK: node zasUInt = asUInt(c@<t:SInt>)@<t:UInt>
+      node zasUInt = asUInt(clk) ;CHECK: node zasUInt = asUInt(clk@<t:Clock>)@<t:UInt>
+   
+      node vasSInt = asSInt(a) ;CHECK: node vasSInt = asSInt(a@<t:UInt>)@<t:SInt>
+      node wasSInt = asSInt(c) ;CHECK: node wasSInt = asSInt(c@<t:SInt>)@<t:SInt>
+      node zasSInt = asSInt(clk) ;CHECK: node zasSInt = asSInt(clk@<t:Clock>)@<t:SInt>
    
-      node vasSInt = asSInt(a)   ;CHECK: node vasSInt = asSInt(a@<t:UInt>)@<t:SInt>
-      node wasSInt = asSInt(a) ;CHECK: node wasSInt = asSInt(a@<t:UInt>)@<t:SInt>
-      node zasSInt = asSInt(c) ;CHECK: node zasSInt = asSInt(c@<t:SInt>)@<t:SInt>
+      node vasClock = asClock(a) ;CHECK: node vasClock = asClock(a@<t:UInt>)@<t:Clock>
+      node wasClock = asClock(c) ;CHECK: node wasClock = asClock(c@<t:SInt>)@<t:Clock>
+      node zasClock = asClock(clk) ;CHECK: node zasClock = asClock(clk@<t:Clock>)@<t:Clock>
    
       node vshl = shl(a, 10)   ;CHECK: node vshl = shl(a@<t:UInt>, 10)@<t:UInt>
       node wshl = shl(a, 10) ;CHECK: node wshl = shl(a@<t:UInt>, 10)@<t:UInt>
@@ -145,7 +114,6 @@ circuit top :
       node wshr = shr(a, 10) ;CHECK: node wshr = shr(a@<t:UInt>, 10)@<t:UInt>
       node zshr = shr(c, 10) ;CHECK: node zshr = shr(c@<t:SInt>, 10)@<t:SInt>
    
-
       node vcvt = cvt(a)   ;CHECK: node vcvt = cvt(a@<t:UInt>)@<t:SInt>
       node wcvt = cvt(a) ;CHECK: node wcvt = cvt(a@<t:UInt>)@<t:SInt>
       node zcvt = cvt(c) ;CHECK: node zcvt = cvt(c@<t:SInt>)@<t:SInt>
@@ -155,19 +123,16 @@ circuit top :
       node zneg = neg(c) ;CHECK: node zneg = neg(c@<t:SInt>)@<t:SInt>
    
       node wnot = not(a) ;CHECK: node wnot = not(a@<t:UInt>)@<t:UInt>
-      node unot = not(c) ;CHECK: node unot = not(c@<t:SInt>)@<t:SInt>
+      node unot = not(c) ;CHECK: node unot = not(c@<t:SInt>)@<t:UInt>
 
       node WAND = and(a, b) ;CHECK: node WAND = and(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
-      node uand = and(c, d) ;CHECK: node uand = and(c@<t:SInt>, d@<t:SInt>)@<t:SInt>
+      node uand = and(c, d) ;CHECK: node uand = and(c@<t:SInt>, d@<t:SInt>)@<t:UInt>
 
       node WOR = or(a, b)  ;CHECK: node WOR = or(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
-      node uor = or(c, d)  ;CHECK: node uor = or(c@<t:SInt>, d@<t:SInt>)@<t:SInt>
+      node uor = or(c, d)  ;CHECK: node uor = or(c@<t:SInt>, d@<t:SInt>)@<t:UInt>
 
       node wxor = xor(a, b) ;CHECK: node wxor = xor(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
-      node uxor = xor(c, d) ;CHECK: node uxor = xor(c@<t:SInt>, d@<t:SInt>)@<t:SInt>
-
-      node wbit = bit(a, 0) ;CHECK: node wbit = bit(a@<t:UInt>, 0)@<t:UInt>
-      node ubit = bit(c, 0) ;CHECK: node ubit = bit(c@<t:SInt>, 0)@<t:UInt>
+      node uxor = xor(c, d) ;CHECK: node uxor = xor(c@<t:SInt>, d@<t:SInt>)@<t:UInt>
 
       node wbits = bits(a, 2, 0) ;CHECK: node wbits = bits(a@<t:UInt>, 2, 0)@<t:UInt>
       node ubits = bits(c, 2, 0) ;CHECK: node ubits = bits(c@<t:SInt>, 2, 0)@<t:UInt>
@@ -178,4 +143,10 @@ circuit top :
       node uorr = orr(a, b, a) ;CHECK: node uorr = orr(a@<t:UInt>, b@<t:UInt>, a@<t:UInt>)@<t:UInt>
       node uxorr = xorr(a, b, a) ;CHECK: node uxorr = xorr(a@<t:UInt>, b@<t:UInt>, a@<t:UInt>)@<t:UInt>
 
+      node whead = head(a, 2) ;CHECK: node whead = head(a@<t:UInt>, 2)@<t:UInt>
+      node uhead = head(c, 2) ;CHECK: node uhead = head(c@<t:SInt>, 2)@<t:UInt>
+
+      node wtail = tail(a, 2) ;CHECK: node wtail = tail(a@<t:UInt>, 2)@<t:UInt>
+      node utail = tail(c, 2) ;CHECK: node utail = tail(c@<t:SInt>, 2)@<t:UInt>
+
 ;CHECK: Finished Infer Types
diff --git a/test/passes/infer-widths/gcd.fir b/test/passes/infer-widths/gcd.fir
index 7745a933..1333fbda 100644
--- a/test/passes/infer-widths/gcd.fir
+++ b/test/passes/infer-widths/gcd.fir
@@ -6,7 +6,7 @@ circuit top :
       input x : UInt
       input y : UInt
       output q : UInt
-      q <= subw(x, y)
+      q <= tail(sub(x, y),1)
    module gcd :
       input a : UInt<16>
       input b : UInt<16>
@@ -14,8 +14,10 @@ circuit top :
       input clk : Clock
       input reset : UInt<1>
       output z : UInt<16>
-      reg x : UInt,clk,reset,UInt(0)
-      reg y : UInt,clk,reset,UInt(42)
+      reg x : UInt,clk with :
+         reset => (reset,UInt(0))
+      reg y : UInt,clk with :
+         reset => (reset,UInt(42))
       when gt(x, y) :
          inst s of subtracter
          s.x <= x
diff --git a/test/passes/infer-widths/shr.fir b/test/passes/infer-widths/shr.fir
index 67b6896e..6a918ba9 100644
--- a/test/passes/infer-widths/shr.fir
+++ b/test/passes/infer-widths/shr.fir
@@ -20,11 +20,16 @@ circuit MemSerdes :
     
     node T_218961 = cat(wide.req_cmd.bits.tag, wide.req_cmd.bits.rw)
     node T_218962 = cat(wide.req_cmd.bits.addr, T_218961)
-    reg out_buf : UInt, clock, reset, out_buf
-    reg in_buf : UInt, clock, reset, in_buf
-    reg state : UInt<3>, clock, reset,UInt<3>("h00")
-    reg send_cnt : UInt<3>, clock, reset, UInt<3>("h00")
-    reg data_send_cnt : UInt<2>, clock, reset, UInt<2>("h00")
+    reg out_buf : UInt, clock with :
+       reset => ( reset, out_buf)
+    reg in_buf : UInt, clock with :
+       reset => ( reset, in_buf)
+    reg state : UInt<3>, clock with :
+       reset => ( reset,UInt<3>("h00"))
+    reg send_cnt : UInt<3>, clock with :
+       reset => ( reset, UInt<3>("h00"))
+    reg data_send_cnt : UInt<2>, clock with :
+       reset => ( reset, UInt<2>("h00"))
     node T_218984 = eq(send_cnt, UInt<2>("h02"))
     node adone = and(narrow.req.ready, T_218984)
     node T_218987 = eq(send_cnt, UInt<3>("h07"))
@@ -32,7 +37,7 @@ circuit MemSerdes :
     
     node T_218989 = and(narrow.req.valid, narrow.req.ready)
     when T_218989 : 
-      node T_218991 = addw(send_cnt, UInt<1>("h01"))
+      node T_218991 = tail(add(send_cnt, UInt<1>("h01")),1)
       send_cnt <= T_218991
       node T_218992 = shr(out_buf, 16)
       out_buf <= T_218992
@@ -87,24 +92,27 @@ circuit MemSerdes :
     node T_219015 = eq(state, UInt<3>("h04"))
     node T_219016 = and(T_219015, ddone)
     when T_219016 : 
-      node T_219018 = addw(data_send_cnt, UInt<1>("h01"))
+      node T_219018 = tail(add(data_send_cnt, UInt<1>("h01")),1)
       data_send_cnt <= T_219018
       node T_219020 = eq(data_send_cnt, UInt<2>("h03"))
       node T_219021 = mux(T_219020, UInt<3>("h00"), UInt<3>("h03"))
       state <= T_219021
       send_cnt <= UInt<1>("h00")
-    reg recv_cnt : UInt<4>, clock, reset, UInt<4>("h00")
-    reg data_recv_cnt : UInt<2>, clock, reset, UInt<2>("h00")
-    reg resp_val : UInt<1>, clock, reset, UInt<1>("h00")
+    reg recv_cnt : UInt<4>, clock with :
+       reset => ( reset, UInt<4>("h00"))
+    reg data_recv_cnt : UInt<2>, clock with :
+       reset => ( reset, UInt<2>("h00"))
+    reg resp_val : UInt<1>, clock with :
+       reset => ( reset, UInt<1>("h00"))
     resp_val <= UInt<1>("h00")
     when narrow.resp.valid : 
-      node T_219031 = addw(recv_cnt, UInt<1>("h01"))
+      node T_219031 = tail(add(recv_cnt, UInt<1>("h01")),1)
       recv_cnt <= T_219031
       
       node T_219033 = eq(recv_cnt, UInt<4>("h08"))
       when T_219033 : 
         recv_cnt <= UInt<1>("h00")
-        node T_219036 = addw(data_recv_cnt, UInt<1>("h01"))
+        node T_219036 = tail(add(data_recv_cnt, UInt<1>("h01")),1)
         data_recv_cnt <= T_219036
         resp_val <= UInt<1>("h01")
       node T_219038 = bits(in_buf, 143, 16)
diff --git a/test/passes/infer-widths/simple.fir b/test/passes/infer-widths/simple.fir
index dc3007f9..63b31a32 100644
--- a/test/passes/infer-widths/simple.fir
+++ b/test/passes/infer-widths/simple.fir
@@ -7,7 +7,8 @@ circuit top :
       input reset : UInt<1>
       wire e : UInt<30>
       e <= UInt(1)
-      reg y : UInt,clk,reset,y
+      reg y : UInt,clk with :
+         reset => (reset,y)
       y <= e
 
       wire a : UInt<20>
diff --git a/test/passes/jacktest/ALUTop.fir b/test/passes/jacktest/ALUTop.fir
index 74abe0bd..a0aadb11 100644
--- a/test/passes/jacktest/ALUTop.fir
+++ b/test/passes/jacktest/ALUTop.fir
@@ -9,8 +9,8 @@ circuit ALUTop :
     input alu_op : UInt<4>
     
     node shamt = bits(B, 4, 0)
-    node T_157 = addw(A, B)
-    node T_158 = subw(A, B)
+    node T_157 = tail(add(A, B),1)
+    node T_158 = tail(sub(A, B),1)
     node T_159 = cvt(A)
     node T_160 = dshr(T_159, shamt)
     node T_161 = asUInt(T_160)
@@ -50,10 +50,10 @@ circuit ALUTop :
     node oot = mux(T_194, T_157, T_193)
     node T_195 = bits(oot, 31, 0)
     out <= T_195
-    node T_196 = bit(alu_op, 0)
-    node T_197 = subw(UInt<1>(0), B)
+    node T_196 = bits(alu_op, 0, 0)
+    node T_197 = tail(sub(UInt<1>(0), B),1)
     node T_198 = mux(T_196, T_197, B)
-    node T_199 = addw(A, T_198)
+    node T_199 = tail(add(A, T_198),1)
     sum <= T_199
   module ALUdec : 
     input opcode : UInt<7>
diff --git a/test/passes/jacktest/Counter.fir b/test/passes/jacktest/Counter.fir
index 4e23ba26..266c1849 100644
--- a/test/passes/jacktest/Counter.fir
+++ b/test/passes/jacktest/Counter.fir
@@ -8,9 +8,10 @@ circuit Counter :
     output tot : UInt<8>
     input amt : UInt<4>
     
-    reg T_13 : UInt<8>,clk,reset,UInt<8>(0)
+    reg T_13 : UInt<8>,clk with :
+       reset => (reset,UInt<8>(0))
     when inc : 
-      node T_14 = addw(T_13, amt)
+      node T_14 = tail(add(T_13, amt),1)
       node T_15 = gt(T_14, UInt<8>(255))
       node T_16 = mux(T_15, UInt<1>(0), T_14)
       T_13 <= T_16
diff --git a/test/passes/jacktest/EnableShiftRegister.fir b/test/passes/jacktest/EnableShiftRegister.fir
index d7e91665..9927e83f 100644
--- a/test/passes/jacktest/EnableShiftRegister.fir
+++ b/test/passes/jacktest/EnableShiftRegister.fir
@@ -8,10 +8,14 @@ circuit EnableShiftRegister :
     output out : UInt<4>
     input shift : UInt<1>
     
-    reg r0 : UInt<4>,clk,reset,UInt<4>(0)
-    reg r1 : UInt<4>,clk,reset,UInt<4>(0)
-    reg r2 : UInt<4>,clk,reset,UInt<4>(0)
-    reg r3 : UInt<4>,clk,reset,UInt<4>(0)
+    reg r0 : UInt<4>,clk with :
+       reset => (reset,UInt<4>(0))
+    reg r1 : UInt<4>,clk with :
+       reset => (reset,UInt<4>(0))
+    reg r2 : UInt<4>,clk with :
+       reset => (reset,UInt<4>(0))
+    reg r3 : UInt<4>,clk with :
+       reset => (reset,UInt<4>(0))
     when shift : 
       r0 <= in
       r1 <= r0
diff --git a/test/passes/jacktest/LFSR16.fir b/test/passes/jacktest/LFSR16.fir
index a4052623..b3fb05cc 100644
--- a/test/passes/jacktest/LFSR16.fir
+++ b/test/passes/jacktest/LFSR16.fir
@@ -7,14 +7,15 @@ circuit LFSR16 :
     input clk : Clock
     input reset : UInt<1>
     
-    reg res : UInt<16>,clk,reset,UInt<16>(1)
+    reg res : UInt<16>,clk with :
+       reset => (reset,UInt<16>(1))
     when inc : 
-      node T_16 = bit(res, 0)
-      node T_17 = bit(res, 2)
+      node T_16 = bits(res, 0, 0)
+      node T_17 = bits(res, 2, 2)
       node T_18 = xor(T_16, T_17)
-      node T_19 = bit(res, 3)
+      node T_19 = bits(res, 3, 3)
       node T_20 = xor(T_18, T_19)
-      node T_21 = bit(res, 5)
+      node T_21 = bits(res, 5, 5)
       node T_22 = xor(T_20, T_21)
       node T_23 = bits(res, 15, 1)
       node T_24 = cat(T_22, T_23)
diff --git a/test/passes/jacktest/MemorySearch.fir b/test/passes/jacktest/MemorySearch.fir
index 1abc50a2..39c19dda 100644
--- a/test/passes/jacktest/MemorySearch.fir
+++ b/test/passes/jacktest/MemorySearch.fir
@@ -9,7 +9,8 @@ circuit MemorySearch :
     input reset : UInt<1>
     output done : UInt<1>
     
-    reg index : UInt<3>,clk,reset,UInt<3>(0)
+    reg index : UInt<3>,clk with :
+       reset => (reset,UInt<3>(0))
     wire elts : UInt<4>[7]
     elts[0] <= UInt<4>(0)
     elts[1] <= UInt<4>(4)
@@ -28,7 +29,7 @@ circuit MemorySearch :
     else : 
       node T_39 = not(end)
       when T_39 : 
-        node T_40 = addw(index, UInt<1>(1))
+        node T_40 = tail(add(index, UInt<1>(1)),1)
         index <= T_40
     done <= end
     address <= index
diff --git a/test/passes/jacktest/ModuleVec.fir b/test/passes/jacktest/ModuleVec.fir
index 9a8e7f2c..6f9b699b 100644
--- a/test/passes/jacktest/ModuleVec.fir
+++ b/test/passes/jacktest/ModuleVec.fir
@@ -5,13 +5,13 @@ circuit ModuleVec :
     input in : UInt<32>
     output out : UInt<32>
     
-    node T_33 = addw(in, UInt<1>(1))
+    node T_33 = tail(add(in, UInt<1>(1)),1)
     out <= T_33
   module PlusOne_25 : 
     input in : UInt<32>
     output out : UInt<32>
     
-    node T_34 = addw(in, UInt<1>(1))
+    node T_34 = tail(add(in, UInt<1>(1)),1)
     out <= T_34
   module ModuleVec : 
     input ins : UInt<32>[2]
diff --git a/test/passes/jacktest/RegisterVecShift.fir b/test/passes/jacktest/RegisterVecShift.fir
index 61376a62..f138d00a 100644
--- a/test/passes/jacktest/RegisterVecShift.fir
+++ b/test/passes/jacktest/RegisterVecShift.fir
@@ -9,7 +9,8 @@ circuit RegisterVecShift :
     input shift : UInt<1>
     input ins : UInt<4>[4]
     
-    reg delays : UInt<4>[4],clk,reset,delays
+    reg delays : UInt<4>[4],clk with :
+       reset => (reset,delays)
     when reset : 
       wire T_33 : UInt<4>[4]
       T_33[0] <= UInt<4>(0)
diff --git a/test/passes/jacktest/Stack.fir b/test/passes/jacktest/Stack.fir
index 319e87d5..162bac25 100644
--- a/test/passes/jacktest/Stack.fir
+++ b/test/passes/jacktest/Stack.fir
@@ -11,25 +11,27 @@ circuit Stack :
     input dataIn : UInt<32>
     
     cmem stack_mem : UInt<32>[16]
-    reg sp : UInt<5>,clk,reset,UInt<5>(0)
-    reg out : UInt<32>,clk,reset,UInt<32>(0)
+    reg sp : UInt<5>,clk with :
+       reset => (reset,UInt<5>(0))
+    reg out : UInt<32>,clk with :
+       reset => (reset,UInt<32>(0))
     when en : 
       node T_30 = lt(sp, UInt<5>(16))
       node T_31 = and(push, T_30)
       when T_31 : 
         write mport T_32 = stack_mem[sp],clk
         T_32 <= dataIn
-        node T_33 = addw(sp, UInt<1>(1))
+        node T_33 = tail(add(sp, UInt<1>(1)),1)
         sp <= T_33
       else : 
         node T_34 = gt(sp, UInt<1>(0))
         node T_35 = and(pop, T_34)
         when T_35 : 
-          node T_36 = subw(sp, UInt<1>(1))
+          node T_36 = tail(sub(sp, UInt<1>(1)),1)
           sp <= T_36
       node T_37 = gt(sp, UInt<1>(0))
       when T_37 : 
-        node T_38 = subw(sp, UInt<1>(1))
+        node T_38 = tail(sub(sp, UInt<1>(1)),1)
         read mport T_39 = stack_mem[T_38],clk
         out <= T_39
     dataOut <= out
diff --git a/test/passes/jacktest/VendingMachine.fir b/test/passes/jacktest/VendingMachine.fir
index 79cebbe1..d7822a17 100644
--- a/test/passes/jacktest/VendingMachine.fir
+++ b/test/passes/jacktest/VendingMachine.fir
@@ -8,7 +8,8 @@ circuit VendingMachine :
     input clk : Clock
     input reset : UInt<1>
     
-    reg state : UInt<3>,clk,reset,UInt<3>(0)
+    reg state : UInt<3>,clk with :
+       reset => (reset,UInt<3>(0))
     node T_22 = eq(state, UInt<3>(0))
     when T_22 : 
       when nickel : state <= UInt<3>(1)
diff --git a/test/passes/jacktest/gcd.fir b/test/passes/jacktest/gcd.fir
index dd3443f1..31ca30b2 100644
--- a/test/passes/jacktest/gcd.fir
+++ b/test/passes/jacktest/gcd.fir
@@ -10,14 +10,16 @@ circuit GCD :
     input a : UInt<16>
     input b : UInt<16>
     
-    reg x : UInt<16>,clk,reset,x
-    reg y : UInt<16>,clk,reset,y
+    reg x : UInt<16>,clk with :
+       reset => (reset,x)
+    reg y : UInt<16>,clk with :
+       reset => (reset,y)
     node T_17 = gt(x, y)
     when T_17 : 
-      node T_18 = subw(x, y)
+      node T_18 = tail(sub(x, y),1)
       x <= T_18
     else : 
-      node T_19 = subw(y, x)
+      node T_19 = tail(sub(y, x),1)
       y <= T_19
     when e : 
       x <= a
diff --git a/test/passes/jacktest/risc.fir b/test/passes/jacktest/risc.fir
index 46f5a1c2..f722cf97 100644
--- a/test/passes/jacktest/risc.fir
+++ b/test/passes/jacktest/risc.fir
@@ -13,7 +13,8 @@ circuit Risc :
     
     cmem file : UInt<32>[256]
     cmem code : UInt<32>[256]
-    reg pc : UInt<8>,clk,reset,UInt<8>(0)
+    reg pc : UInt<8>,clk with :
+       reset => (reset,UInt<8>(0))
     read mport inst = code[pc],clk
     node op = bits(inst, 31, 24)
     node rci = bits(inst, 23, 16)
@@ -36,7 +37,7 @@ circuit Risc :
       else : 
         node T_56 = eq(UInt<1>(0), op)
         when T_56 : 
-          node T_57 = addw(ra, rb)
+          node T_57 = tail(add(ra, rb),1)
           rc <= T_57
         node T_58 = eq(UInt<1>(1), op)
         when T_58 : 
@@ -49,5 +50,5 @@ circuit Risc :
         else : 
           write mport T_62 = file[rci],clk
           T_62 <= rc
-        node T_63 = addw(pc, UInt<1>(1))
+        node T_63 = tail(add(pc, UInt<1>(1)),1)
         pc <= T_63
diff --git a/test/passes/lower-to-ground/bundle-vecs.fir b/test/passes/lower-to-ground/bundle-vecs.fir
index 64a4a4b6..c42766ad 100644
--- a/test/passes/lower-to-ground/bundle-vecs.fir
+++ b/test/passes/lower-to-ground/bundle-vecs.fir
@@ -25,19 +25,19 @@ circuit top :
 ;CHECK: wire GEN_3 : UInt<32>
 ;CHECK: j_x <= GEN_0
 ;CHECK: j_y <= GEN_3
-;CHECK: node GEN_4 = eqv(UInt("h0"), i)
+;CHECK: node GEN_4 = eq(UInt("h0"), i)
 ;CHECK: a_0_x <= mux(GEN_4, GEN_2, UInt("h0"))
-;CHECK: node GEN_5 = eqv(UInt("h0"), i)
+;CHECK: node GEN_5 = eq(UInt("h0"), i)
 ;CHECK: a_0_y <= mux(GEN_5, GEN_1, UInt("h0"))
-;CHECK: node GEN_6 = eqv(UInt("h1"), i)
+;CHECK: node GEN_6 = eq(UInt("h1"), i)
 ;CHECK: a_1_x <= mux(GEN_6, GEN_2, UInt("h0"))
-;CHECK: node GEN_7 = eqv(UInt("h1"), i)
+;CHECK: node GEN_7 = eq(UInt("h1"), i)
 ;CHECK: a_1_y <= mux(GEN_7, GEN_1, UInt("h0"))
-;CHECK: node GEN_8 = eqv(UInt("h1"), i)
+;CHECK: node GEN_8 = eq(UInt("h1"), i)
 ;CHECK: GEN_0 <= mux(GEN_8, a_1_x, a_0_x)
 ;CHECK: GEN_1 <= j_y
 ;CHECK: GEN_2 <= j_x
-;CHECK: node GEN_9 = eqv(UInt("h1"), i)
+;CHECK: node GEN_9 = eq(UInt("h1"), i)
 ;CHECK: GEN_3 <= mux(GEN_9, a_1_y, a_0_y)   
 
 ; CHECK: Finished Lower Types
diff --git a/test/passes/lower-to-ground/nested-vec.fir b/test/passes/lower-to-ground/nested-vec.fir
index 0d4f5bf0..fcdee5bc 100644
--- a/test/passes/lower-to-ground/nested-vec.fir
+++ b/test/passes/lower-to-ground/nested-vec.fir
@@ -41,17 +41,17 @@ circuit top :
       m.c.data <= k
 
 ;CHECK: mem m_x :          
-;CHECK:    data-type: UInt<32>
-;CHECK:    depth: 2
-;CHECK:    write-latency: 1
-;CHECK:    read-latency: 0
-;CHECK:    writer: c
+;CHECK:    data-type => UInt<32>
+;CHECK:    depth => 2
+;CHECK:    write-latency => 1
+;CHECK:    read-latency => 0
+;CHECK:    writer => c
 ;CHECK: mem m_y :          
-;CHECK:    data-type: UInt<32>
-;CHECK:    depth: 2
-;CHECK:    write-latency: 1
-;CHECK:    read-latency: 0
-;CHECK:    writer: c
+;CHECK:    data-type => UInt<32>
+;CHECK:    depth => 2
+;CHECK:    write-latency => 1
+;CHECK:    read-latency => 0
+;CHECK:    writer => c
 ;CHECK: m_x.c.data <= k_x
 ;CHECK: m_y.c.data <= k_y
 ;CHECK: m_x.c.mask <= UInt("h1")
diff --git a/test/passes/lower-to-ground/register.fir b/test/passes/lower-to-ground/register.fir
index 66d1cfb3..648964bd 100644
--- a/test/passes/lower-to-ground/register.fir
+++ b/test/passes/lower-to-ground/register.fir
@@ -11,11 +11,14 @@
                wire q : { x : UInt, y : SInt }
                q.x <= UInt(0)
                q.y <= SInt(0)
-               reg r1 : { x : UInt, y : SInt },clk,reset,q
+               reg r1 : { x : UInt, y : SInt } clk with :
+                  reset => (reset,q)
 
       ; CHECK: wire q{{[_$]+}}x : UInt
       ; CHECK: wire q{{[_$]+}}y : SInt
-      ; CHECK: reg r1{{[_$]+}}x : UInt<1>, clk, reset, q_x
-      ; CHECK: reg r1{{[_$]+}}y : SInt<1>, clk, reset, q_y
+      ; CHECK: reg r1{{[_$]+}}x : UInt<1>, clk with :
+         ;CHECK: reset => (reset, q_x)
+      ; CHECK: reg r1{{[_$]+}}y : SInt<1>, clk with :
+         ;CHECK: reset => (reset, q_y)
 
 ; CHECK: Finished Lower Types
diff --git a/test/passes/remove-accesses/bundle-vecs.fir b/test/passes/remove-accesses/bundle-vecs.fir
index e916bfa8..e618892e 100644
--- a/test/passes/remove-accesses/bundle-vecs.fir
+++ b/test/passes/remove-accesses/bundle-vecs.fir
@@ -31,11 +31,11 @@ circuit top :
 ; CHECK: wire b : { x : UInt<32>, flip y : UInt<32>}
 ; CHECK: wire GEN_0 : UInt<32>
 ; CHECK: GEN_0 <= a[0].x
-; CHECK: when eqv(UInt("h1"), i) : GEN_0 <= a[1].x
+; CHECK: when eq(UInt("h1"), i) : GEN_0 <= a[1].x
 ; CHECK: b.x <= GEN_0
 ; CHECK: wire GEN_1 : UInt<32>
-; CHECK: when eqv(UInt("h0"), i) : a[0].y <= GEN_1
-; CHECK: when eqv(UInt("h1"), i) : a[1].y <= GEN_1
+; CHECK: when eq(UInt("h0"), i) : a[0].y <= GEN_1
+; CHECK: when eq(UInt("h1"), i) : a[1].y <= GEN_1
 ; CHECK: GEN_1 <= b.y
 ; CHECK: j <= b.x
 ; CHECK: b.y <= UInt("h1")   
diff --git a/test/passes/remove-accesses/simple11.fir b/test/passes/remove-accesses/simple11.fir
index e35bfb3c..b27f1a46 100644
--- a/test/passes/remove-accesses/simple11.fir
+++ b/test/passes/remove-accesses/simple11.fir
@@ -11,10 +11,14 @@ circuit DecoupledAdderTests :
     io.out.bits.c <= UInt<1>("h00")
     io.out.valid <= UInt<1>("h00")
     io.in.ready <= UInt<1>("h00")
-    reg ready : UInt<1>, clock, reset, ready
-    reg busy : UInt<1>, clock, reset, busy
-    reg a_reg : UInt<16>, clock, reset, a_reg
-    reg b_reg : UInt<16>, clock, reset, b_reg
+    reg ready : UInt<1>, clock with :
+       reset => ( reset, ready)
+    reg busy : UInt<1>, clock with :
+       reset => ( reset, busy)
+    reg a_reg : UInt<16>, clock with :
+       reset => ( reset, a_reg)
+    reg b_reg : UInt<16>, clock with :
+       reset => ( reset, b_reg)
     io.in.ready <= ready
     when io.in.valid :
       a_reg <= io.in.bits.a
@@ -25,7 +29,7 @@ circuit DecoupledAdderTests :
       skip
     node T_45 = and(busy, io.out.ready)
     when T_45 :
-      node T_46 = addw(a_reg, b_reg)
+      node T_46 = tail(add(a_reg, b_reg),1)
       io.out.bits.c <= T_46
       io.out.valid <= UInt<1>("h01")
       io.in.ready <= UInt<1>("h01")
@@ -44,8 +48,9 @@ circuit DecoupledAdderTests :
     device_under_test.io.in.valid <= UInt<1>("h00")
     device_under_test.clock <= clock
     device_under_test.reset <= reset
-    reg T_10 : UInt<33>, clock, reset, UInt<33>("h00")
-    node T_12 = addw(T_10, UInt<1>("h01"))
+    reg T_10 : UInt<33>, clock with :
+       reset => ( reset, UInt<33>("h00"))
+    node T_12 = tail(add(T_10, UInt<1>("h01")),1)
     T_10 <= T_12
     node T_14 = eq(reset, UInt<1>("h00"))
     when T_14 :
@@ -66,8 +71,10 @@ circuit DecoupledAdderTests :
     when T_22 :
       printf(clock,UInt(1), "device in ready %d, valid %d", device_under_test.io.in.ready, device_under_test.io.in.valid)
       skip
-    reg T_24 : UInt<1>, clock, reset, UInt<1>("h00")
-    reg T_26 : UInt<1>, clock, reset, UInt<1>("h00")
+    reg T_24 : UInt<1>, clock with :
+       reset => ( reset, UInt<1>("h00"))
+    reg T_26 : UInt<1>, clock with :
+       reset => ( reset, UInt<1>("h00"))
     node T_27 = and(T_24, T_26)
     when T_27 :
       node T_29 = eq(reset, UInt<1>("h00"))
@@ -75,8 +82,10 @@ circuit DecoupledAdderTests :
         stop(clock,UInt(1), 0)
         skip
       skip
-    reg T_31 : UInt<1>, clock, reset, UInt<1>("h00")
-    reg T_33 : UInt<1>, clock, reset, UInt<1>("h00")
+    reg T_31 : UInt<1>, clock with :
+       reset => ( reset, UInt<1>("h00"))
+    reg T_33 : UInt<1>, clock with :
+       reset => ( reset, UInt<1>("h00"))
     wire T_43 : {flip ready : UInt<1>, valid : UInt<1>, bits : {a : UInt<16>, b : UInt<16>}}[1]
     T_43[0].bits.b <= UInt(0)
     T_43[0].bits.a <= UInt(1)
@@ -108,14 +117,14 @@ circuit DecoupledAdderTests :
     node T_113 = and(T_103, T_43[T_31].ready)
     when T_113 :
       T_43[T_31].valid <= UInt<1>("h01")
-      node T_125 = addw(T_31, UInt<1>("h01"))
+      node T_125 = tail(add(T_31, UInt<1>("h01")),1)
       T_31 <= T_125
       node T_127 = geq(T_31, UInt<1>("h00"))
       T_24 <= T_127
       skip
     node T_129 = eq(T_26, UInt<1>("h00"))
     when T_129 :
-      node T_131 = addw(T_33, UInt<1>("h01"))
+      node T_131 = tail(add(T_33, UInt<1>("h01")),1)
       T_33 <= T_131
       node T_133 = geq(T_33, UInt<1>("h00"))
       T_26 <= T_133
diff --git a/test/passes/remove-accesses/simple3.fir b/test/passes/remove-accesses/simple3.fir
index b19c4130..6305e0c9 100644
--- a/test/passes/remove-accesses/simple3.fir
+++ b/test/passes/remove-accesses/simple3.fir
@@ -13,8 +13,8 @@ circuit top :
       a <= in
 
 ;CHECK: wire GEN_0 : UInt<32>
-;CHECK: when eqv(UInt("h0"), i) : m[0] <= GEN_0
-;CHECK: when eqv(UInt("h1"), i) : m[1] <= GEN_0
+;CHECK: when eq(UInt("h0"), i) : m[0] <= GEN_0
+;CHECK: when eq(UInt("h1"), i) : m[1] <= GEN_0
 ;CHECK: GEN_0 <= a
 
 ;CHECK: Finished Remove Accesses
diff --git a/test/passes/remove-accesses/simple4.fir b/test/passes/remove-accesses/simple4.fir
index 06ff7481..4766214c 100644
--- a/test/passes/remove-accesses/simple4.fir
+++ b/test/passes/remove-accesses/simple4.fir
@@ -12,8 +12,8 @@ circuit top :
       m[1].y <= UInt("h1")
       m[i].x <= in.x
 
-;CHECK: when eqv(UInt("h0"), i) : m[0].x <= GEN_0
-;CHECK: when eqv(UInt("h1"), i) : m[1].x <= GEN_0
+;CHECK: when eq(UInt("h0"), i) : m[0].x <= GEN_0
+;CHECK: when eq(UInt("h1"), i) : m[1].x <= GEN_0
 ;CHECK: GEN_0 <= in
 ;CHECK: Finished Remove Accesses
 ;CHECK: Done!
diff --git a/test/passes/remove-accesses/simple5.fir b/test/passes/remove-accesses/simple5.fir
index 0a1baed6..d2e31537 100644
--- a/test/passes/remove-accesses/simple5.fir
+++ b/test/passes/remove-accesses/simple5.fir
@@ -15,7 +15,7 @@ circuit top :
 
 ;CHECK: when i :
 ;CHECK: GEN_0 <= m[0]
-;CHECK: when eqv(UInt("h1"), i) : GEN_0 <= m[1]
+;CHECK: when eq(UInt("h1"), i) : GEN_0 <= m[1]
 ;CHECK: o <= GEN_0
 ;CHECK: Finished Remove Accesses
 ;CHECK: Done!
diff --git a/test/passes/remove-accesses/simple8.fir b/test/passes/remove-accesses/simple8.fir
index 6b084ed3..1d275618 100644
--- a/test/passes/remove-accesses/simple8.fir
+++ b/test/passes/remove-accesses/simple8.fir
@@ -21,25 +21,26 @@ circuit top :
     wire T_75 : UInt<128>[2]
     T_75[0] <= UInt<1>("h00")
     T_75[1] <= UInt<1>("h00")
-    reg T_81 : UInt<12>, clock, reset, T_81
+    reg T_81 : UInt<12>, clock with :
+       reset => ( reset, T_81)
     when read.valid :
       T_81 <= read.bits.addr
       skip
     cmem T_84 : UInt<128>[256]
     node T_86 = neq(T_65, UInt<1>("h00"))
     node T_87 = and(T_86, write.valid)
-    node T_88 = bit(write.bits.wmask, 0)
+    node T_88 = bits(write.bits.wmask, 0, 0)
     node T_89 = and(T_87, T_88)
     when T_89 :
       node T_90 = bits(write.bits.data, 63, 0)
       node T_91 = cat(T_90, T_90)
-      node T_92 = bit(T_65, 0)
-      node T_93 = bit(T_65, 1)
+      node T_92 = bits(T_65, 0, 0)
+      node T_93 = bits(T_65, 1, 1)
       wire T_95 : UInt<1>[2]
       T_95[0] <= T_92
       T_95[1] <= T_93
-      node T_100 = subw(UInt<64>("h00"), T_95[0])
-      node T_102 = subw(UInt<64>("h00"), T_95[1])
+      node T_100 = tail(sub(UInt<64>("h00"), T_95[0]),1)
+      node T_102 = tail(sub(UInt<64>("h00"), T_95[1]),1)
       wire T_104 : UInt<64>[2]
       T_104[0] <= T_100
       T_104[1] <= T_102
@@ -57,7 +58,8 @@ circuit top :
       skip
     node T_118 = neq(T_66, UInt<1>("h00"))
     node T_119 = and(T_118, read.valid)
-    reg T_120 : UInt<8>, clock, reset, T_120
+    reg T_120 : UInt<8>, clock with :
+       reset => ( reset, T_120)
     when T_119 :
       T_120 <= raddr
       skip
@@ -66,18 +68,18 @@ circuit top :
     cmem T_124 : UInt<128>[256]
     node T_126 = neq(T_65, UInt<1>("h00"))
     node T_127 = and(T_126, write.valid)
-    node T_128 = bit(write.bits.wmask, 1)
+    node T_128 = bits(write.bits.wmask, 1, 1)
     node T_129 = and(T_127, T_128)
     when T_129 :
       node T_130 = bits(write.bits.data, 127, 64)
       node T_131 = cat(T_130, T_130)
-      node T_132 = bit(T_65, 0)
-      node T_133 = bit(T_65, 1)
+      node T_132 = bits(T_65, 0, 0)
+      node T_133 = bits(T_65, 1, 1)
       wire T_135 : UInt<1>[2]
       T_135[0] <= T_132
       T_135[1] <= T_133
-      node T_140 = subw(UInt<64>("h00"), T_135[0])
-      node T_142 = subw(UInt<64>("h00"), T_135[1])
+      node T_140 = tail(sub(UInt<64>("h00"), T_135[0]),1)
+      node T_142 = tail(sub(UInt<64>("h00"), T_135[1]),1)
       wire T_144 : UInt<64>[2]
       T_144[0] <= T_140
       T_144[1] <= T_142
@@ -95,7 +97,8 @@ circuit top :
       skip
     node T_158 = neq(T_66, UInt<1>("h00"))
     node T_159 = and(T_158, read.valid)
-    reg T_160 : UInt<8>, clock, reset, T_160
+    reg T_160 : UInt<8>, clock with :
+       reset => ( reset, T_160)
     when T_159 :
       T_160 <= raddr
       skip
@@ -128,25 +131,26 @@ circuit top :
     wire T_202 : UInt<128>[2]
     T_202[0] <= UInt<1>("h00")
     T_202[1] <= UInt<1>("h00")
-    reg T_208 : UInt<12>, clock, reset, T_208
+    reg T_208 : UInt<12>, clock with :
+       reset => ( reset, T_208)
     when read.valid :
       T_208 <= read.bits.addr
       skip
     cmem T_211 : UInt<128>[256]
     node T_213 = neq(T_192, UInt<1>("h00"))
     node T_214 = and(T_213, write.valid)
-    node T_215 = bit(write.bits.wmask, 0)
+    node T_215 = bits(write.bits.wmask, 0, 0)
     node T_216 = and(T_214, T_215)
     when T_216 :
       node T_217 = bits(write.bits.data, 63, 0)
       node T_218 = cat(T_217, T_217)
-      node T_219 = bit(T_192, 0)
-      node T_220 = bit(T_192, 1)
+      node T_219 = bits(T_192, 0, 0)
+      node T_220 = bits(T_192, 1, 1)
       wire T_222 : UInt<1>[2]
       T_222[0] <= T_219
       T_222[1] <= T_220
-      node T_227 = subw(UInt<64>("h00"), T_222[0])
-      node T_229 = subw(UInt<64>("h00"), T_222[1])
+      node T_227 = tail(sub(UInt<64>("h00"), T_222[0]),1)
+      node T_229 = tail(sub(UInt<64>("h00"), T_222[1]),1)
       wire T_231 : UInt<64>[2]
       T_231[0] <= T_227
       T_231[1] <= T_229
@@ -164,7 +168,8 @@ circuit top :
       skip
     node T_245 = neq(T_193, UInt<1>("h00"))
     node T_246 = and(T_245, read.valid)
-    reg T_247 : UInt<8>, clock, reset, T_247
+    reg T_247 : UInt<8>, clock with :
+       reset => ( reset, T_247)
     when T_246 :
       T_247 <= raddr
       skip
@@ -173,18 +178,18 @@ circuit top :
     cmem T_251 : UInt<128>[256]
     node T_253 = neq(T_192, UInt<1>("h00"))
     node T_254 = and(T_253, write.valid)
-    node T_255 = bit(write.bits.wmask, 1)
+    node T_255 = bits(write.bits.wmask, 1, 1)
     node T_256 = and(T_254, T_255)
     when T_256 :
       node T_257 = bits(write.bits.data, 127, 64)
       node T_258 = cat(T_257, T_257)
-      node T_259 = bit(T_192, 0)
-      node T_260 = bit(T_192, 1)
+      node T_259 = bits(T_192, 0, 0)
+      node T_260 = bits(T_192, 1, 1)
       wire T_262 : UInt<1>[2]
       T_262[0] <= T_259
       T_262[1] <= T_260
-      node T_267 = subw(UInt<64>("h00"), T_262[0])
-      node T_269 = subw(UInt<64>("h00"), T_262[1])
+      node T_267 = tail(sub(UInt<64>("h00"), T_262[0]),1)
+      node T_269 = tail(sub(UInt<64>("h00"), T_262[1]),1)
       wire T_271 : UInt<64>[2]
       T_271[0] <= T_267
       T_271[1] <= T_269
@@ -202,7 +207,8 @@ circuit top :
       skip
     node T_285 = neq(T_193, UInt<1>("h00"))
     node T_286 = and(T_285, read.valid)
-    reg T_287 : UInt<8>, clock, reset, T_287
+    reg T_287 : UInt<8>, clock with :
+       reset => ( reset, T_287)
     when T_286 :
       T_287 <= raddr
       skip
diff --git a/test/passes/remove-accesses/simple9.fir b/test/passes/remove-accesses/simple9.fir
index 5405c42a..d1aec9f1 100644
--- a/test/passes/remove-accesses/simple9.fir
+++ b/test/passes/remove-accesses/simple9.fir
@@ -7,7 +7,8 @@ circuit top :
     input reset : UInt<1>
     input clock : Clock
     output out : UInt<1>
-    reg T_4590 : UInt<1>[2], clock, reset, T_4590
+    reg T_4590 : UInt<1>[2], clock with :
+       reset => ( reset, T_4590)
     T_4590[0] <= UInt(0)
     T_4590[1] <= UInt(0)
     out <= UInt(0)
diff --git a/test/passes/resolve-genders/gcd.fir b/test/passes/resolve-genders/gcd.fir
index 4d7772d9..c2a0df4a 100644
--- a/test/passes/resolve-genders/gcd.fir
+++ b/test/passes/resolve-genders/gcd.fir
@@ -6,8 +6,8 @@ circuit top :
       input x : UInt
       input y : UInt
       output z : UInt
-      z <= subw(x, y)
-      ;CHECK: z@<g:f> <= subw(x@<g:m>, y@<g:m>)
+      z <= tail(sub(x, y),1)
+      ;CHECK: z@<g:f> <= tail(sub(x@<g:m>, y@<g:m>)@<g:m>, 1)@<g:m>   
    module gcd :
       input a : UInt<16>
       input b : UInt<16>
@@ -16,8 +16,10 @@ circuit top :
       input reset : UInt<1>
       output z : UInt<16>
       output v : UInt<1>
-      reg x : UInt,clk,reset,UInt(0)
-      reg y : UInt,clk,reset,UInt(42)
+      reg x : UInt,clk with :
+         reset => (reset,UInt(0))
+      reg y : UInt,clk with :
+         reset => (reset,UInt(42))
 ; CHECK: reg x : UInt
       when gt(x, y) :
       ;CHECK: when gt(x@<g:m>, y@<g:m>)@<g:m> :
diff --git a/test/passes/resolve-genders/subbundle.fir b/test/passes/resolve-genders/subbundle.fir
index 0d0dd574..e91fa52e 100644
--- a/test/passes/resolve-genders/subbundle.fir
+++ b/test/passes/resolve-genders/subbundle.fir
@@ -6,7 +6,8 @@ circuit top :
       input clk : Clock
       input reset : UInt<1>
       wire w : { flip x : UInt<10>}
-      reg r : { flip x : UInt<10>},clk,reset,w
+      reg r : { flip x : UInt<10>},clk with :
+         reset => (reset,w)
       w <= r     ; CHECK r_x := w_x
       w.x <= r.x ; CHECK w_x := r_x
 ; CHECK: Finished Lower Types
diff --git a/test/passes/resolve-kinds/gcd.fir b/test/passes/resolve-kinds/gcd.fir
index bb978972..cdc8c337 100644
--- a/test/passes/resolve-kinds/gcd.fir
+++ b/test/passes/resolve-kinds/gcd.fir
@@ -6,8 +6,8 @@ circuit top :
       input x : UInt
       input y : UInt
       output z : UInt
-      z <= subw(x, y)
-      ;CHECK: z@<k:port> <= subw(x@<k:port>, y@<k:port>)
+      z <= tail(sub(x, y),1)
+      ;CHECK: z@<k:port> <= tail(sub(x@<k:port>, y@<k:port>)@<k:exp>, 1)@<k:exp>   
    module gcd :
       input clk : Clock
       input reset : UInt<1>
@@ -16,8 +16,10 @@ circuit top :
       input e : UInt<1>
       output z : UInt<16>
       output v : UInt<1>
-      reg x : UInt,clk,reset,UInt(0)
-      reg y : UInt,clk,reset,UInt(42)
+      reg x : UInt,clk with :
+         reset => (reset,UInt(0))
+      reg y : UInt,clk with :
+         reset => (reset,UInt(42))
       when gt(x, y) :
          inst s of subtracter
          s.x <= x
diff --git a/test/passes/split-exp/gcd.fir b/test/passes/split-exp/gcd.fir
index e651f41a..4b42d007 100644
--- a/test/passes/split-exp/gcd.fir
+++ b/test/passes/split-exp/gcd.fir
@@ -6,7 +6,7 @@ circuit top :
       input x : UInt
       input y : UInt
       output q : UInt
-      q <= subw(x, y)
+      q <= tail(sub(x, y),1)
    module gcd :
       input clk : Clock
       input reset : UInt<1>
@@ -14,8 +14,10 @@ circuit top :
       input b : UInt<16>
       input e : UInt<1>
       output z : UInt<16>
-      reg x : UInt,clk,reset,UInt(0)
-      reg y : UInt,clk,reset,UInt(42)
+      reg x : UInt,clk with :
+         reset => (reset,UInt(0))
+      reg y : UInt,clk with :
+         reset => (reset,UInt(42))
       when gt(x, y) :
          inst s of subtracter
          s.x <= x
diff --git a/test/passes/split-exp/split-in-when.fir b/test/passes/split-exp/split-in-when.fir
index e4d0da36..06d1463d 100644
--- a/test/passes/split-exp/split-in-when.fir
+++ b/test/passes/split-exp/split-in-when.fir
@@ -9,16 +9,21 @@ circuit Top :
       input b : UInt<10>
       input c : UInt<10>
       
-      reg out : UInt<10>,clk,p,a
+      reg out : UInt<10>,clk with :
+         reset => (p,a)
 
-      when bit(subw(a,c),3) : out <= mux(eqv(bits(UInt(32),4,0),UInt(13)),addw(a,addw(b,c)),subw(c,b))
+      when bits(tail(sub(a,c),1),3,3) : out <= mux(eq(bits(UInt(32),4,0),UInt(13)),tail(add(a,tail(add(b,c),1)),1),tail(sub(c,b),1))
 
-;CHECK: node GEN_0 = subw(a, c)
-;CHECK: node GEN_1 = bit(GEN_0, 3)
-;CHECK: node GEN_2 = eqv(UInt("h0"), UInt("hd"))
-;CHECK: node GEN_3 = addw(b, c)
-;CHECK: node GEN_4 = addw(a, GEN_3)
-;CHECK: node GEN_5 = subw(c, b)
-;CHECK: out <= mux(GEN_1, mux(GEN_2, GEN_4, GEN_5), out)   
+;CHECK: node GEN_0 = sub(a, c)
+;CHECK: node GEN_1 = tail(GEN_0, 1)
+;CHECK: node GEN_2 = bits(GEN_1, 3, 3)
+;CHECK: node GEN_3 = eq(UInt("h0"), UInt("hd"))
+;CHECK: node GEN_4 = add(b, c)
+;CHECK: node GEN_5 = tail(GEN_4, 1)
+;CHECK: node GEN_6 = add(a, GEN_5)
+;CHECK: node GEN_7 = tail(GEN_6, 1)
+;CHECK: node GEN_8 = sub(c, b)
+;CHECK: node GEN_9 = tail(GEN_8, 1)
+;CHECK: out <= mux(GEN_2, mux(GEN_3, GEN_7, GEN_9), out)   
 
 ;CHECK: Finished Split Expressions
diff --git a/test/passes/to-verilog/gcd.fir b/test/passes/to-verilog/gcd.fir
index cadd9ec8..5a50ddd1 100644
--- a/test/passes/to-verilog/gcd.fir
+++ b/test/passes/to-verilog/gcd.fir
@@ -6,7 +6,7 @@ circuit top :
       input x : UInt
       input y : UInt
       output q : UInt
-      q <= subw(x, y)
+      q <= tail(sub(x, y),1)
    module gcd :
       input clk : Clock
       input reset : UInt<1>
@@ -14,8 +14,10 @@ circuit top :
       input b : UInt<16>
       input e : UInt<1>
       output z : UInt<16>
-      reg x : UInt,clk,reset,UInt(0)
-      reg y : UInt,clk,reset,UInt(42)
+      reg x : UInt,clk with :
+         reset => (reset,UInt(0))
+      reg y : UInt,clk with :
+         reset => (reset,UInt(42))
       when gt(x, y) :
          inst s of subtracter
          s.x <= x
diff --git a/test/passes/to-verilog/shr.fir b/test/passes/to-verilog/shr.fir
index d8e889da..6921e74e 100644
--- a/test/passes/to-verilog/shr.fir
+++ b/test/passes/to-verilog/shr.fir
@@ -16,9 +16,12 @@ circuit HellaCache :
 
     inst dtlb of TLB_60
     poison init : {addr : UInt<40>}
-    reg s1_req : {addr : UInt<40>}, clock, reset, init
-    reg s2_req : {addr : UInt<40>}, clock, reset, init
-    reg s1_clk_en : UInt<1>, clock, reset, UInt(0)
+    reg s1_req : {addr : UInt<40>}, clock with :
+       reset => ( reset, init)
+    reg s2_req : {addr : UInt<40>}, clock with :
+       reset => ( reset, init)
+    reg s1_clk_en : UInt<1>, clock with :
+       reset => ( reset, UInt(0))
 
     node T_928 = bits(s1_req.addr, 11, 0)
     node s1_addr = cat(dtlb.resp.ppn, T_928)