blob: cdc8c337bf407cc064913aad48092f21ac8c4cd2 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
|
; RUN: firrtl -i %s -o %s.v -X verilog -p ck 2>&1 | tee %s.out | FileCheck %s
; CHECK: Resolve Kinds
circuit top :
module subtracter :
input x : UInt
input y : UInt
output z : UInt
z <= tail(sub(x, y),1)
;CHECK: z@<k:port> <= tail(sub(x@<k:port>, y@<k:port>)@<k:exp>, 1)@<k:exp>
module gcd :
input clk : Clock
input reset : UInt<1>
input a : UInt<16>
input b : UInt<16>
input e : UInt<1>
output z : UInt<16>
output v : UInt<1>
reg x : UInt,clk with :
reset => (reset,UInt(0))
reg y : UInt,clk with :
reset => (reset,UInt(42))
when gt(x, y) :
inst s of subtracter
s.x <= x
;CHECK: s@<k:inst>.x@<k:inst> <= x@<k:reg>
s.y <= y
x <= s.z
else :
inst s2 of subtracter
s2.x <= x
s2.y <= y
y <= s2.z
when e :
x <= a
y <= b
v <= eq(v, UInt(0))
z <= x
module top :
input a : UInt<16>
input b : UInt<16>
input clk : Clock
input reset : UInt<1>
output z : UInt
inst i of gcd
i.a <= a
i.b <= b
i.clk <= clk
i.reset <= reset
i.e <= UInt(1)
z <= i.z
;CHECK: z@<k:port> <= i@<k:inst>.z@<k:inst>
; CHECK: Finished Resolve Kinds
|
