WIP, hit semantic bug in WSubAccess

4 files changed, 47 insertions, 28 deletions

diff --git a/test/features/InitializeVec.fir b/test/features/InitializeVec.fir
index ef6400a0..1cc44daf 100644
--- a/test/features/InitializeVec.fir
+++ b/test/features/InitializeVec.fir
@@ -1,5 +1,5 @@
 ; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
-; XFAIL: *
+
 ;CHECK: Done!
 circuit Tst : 
   module Tst : 
@@ -16,7 +16,6 @@ circuit Tst :
     outs[3].valid <= UInt<1>(0)
     outs[3].bits <= UInt<1>(0)
     in.ready <= UInt<1>(1)
-    infer accessor out = outs[in.bits]
-    when out.ready : 
-      out.bits <= UInt<7>(99)
-      out.valid <= UInt<1>(1)
+    when outs[in.bits].ready : 
+      outs[in.bits].bits <= UInt<7>(99)
+      outs[in.bits].valid <= UInt<1>(1)
diff --git a/test/features/SeqMem.fir b/test/features/SeqMem.fir
index 354bd8de..d97435af 100644
--- a/test/features/SeqMem.fir
+++ b/test/features/SeqMem.fir
@@ -10,15 +10,37 @@ circuit Top :
 
     i0 <= UInt(10)
 
-    cmem m-com : UInt<128>[32], clk
-    infer accessor r-com = m-com[i]
-    infer accessor w-com = m-com[i]
-    j <= r-com
-    w-com <= j
+    mem m-com : 
+       data-type => UInt<128>
+       depth => 32
+       reader => r
+       writer => w
+       read-latency => 0
+       write-latency => 1
+    m-com.r.addr <= i
+    m-com.r.en <= UInt(1)
+    m-com.r.clk <= clk
+    m-com.w.addr <= i
+    m-com.w.mask <= UInt(1)
+    m-com.w.en <= UInt(1)
+    m-com.w.clk <= clk
+    j <= m-com.r.data
+    m-com.w.data <= j
 
 
-    smem m-seq : UInt<128>[32], clk
-    infer accessor r-seq = m-seq[i]
-    infer accessor w-seq = m-seq[i]
-    j <= r-seq
-    w-seq <= j
+    mem m-seq : 
+       data-type => UInt<128>
+       depth => 32
+       reader => r
+       writer => w
+       read-latency => 1
+       write-latency => 1
+    m-seq.r.addr <= i
+    m-seq.r.en <= UInt(1)
+    m-seq.r.clk <= clk
+    m-seq.w.addr <= i
+    m-seq.w.mask <= UInt(1)
+    m-seq.w.en <= UInt(1)
+    m-seq.w.clk <= clk
+    j <= m-seq.r.data
+    m-seq.w.data <= j
diff --git a/test/features/Stop.fir b/test/features/Stop.fir
index 16e25416..d0957324 100644
--- a/test/features/Stop.fir
+++ b/test/features/Stop.fir
@@ -1,6 +1,6 @@
 ; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
 
-;CHECK: Lower To Ground
+;CHECK: Expand Whens
 
 circuit Top : 
   module Top : 
@@ -8,14 +8,13 @@ circuit Top :
     input q : UInt<1>
     input clk : Clock
     when p :
-       stop(clk,0)
+       stop(clk,UInt(1),0)
     when q :
-       stop(clk,1)
-    stop(clk,3)
-
-;CHECK: when p : stop(clk, 0)
-;CHECK: when q : stop(clk, 1)
-;CHECK: stop(clk, 3)   
+       stop(clk,UInt(1),1)
+    stop(clk,UInt(1),3)
 
+;CHECK: stop(clk, and(p, UInt("h1")), 0)
+;CHECK: stop(clk, and(q, UInt("h1")), 1)
+;CHECK: stop(clk, UInt("h1"), 3)   
 ;CHECK: Done!
 
diff --git a/test/features/TwoClocks.fir b/test/features/TwoClocks.fir
index f68a2769..6562d3e1 100644
--- a/test/features/TwoClocks.fir
+++ b/test/features/TwoClocks.fir
@@ -5,15 +5,14 @@ circuit Top :
     input clk2 : Clock
     input reset1 : UInt<1>
     input reset2 : UInt<1>
-    reg src : UInt<10>, clk1, reset1
-    reg sink : UInt<10>, clk2, reset2
+    reg src : UInt<10>, clk1, reset1, UInt(0)
+    reg sink : UInt<10>, clk2, reset2, UInt(0)
 
-    onreset src <= UInt(0)
     src <= addw(src,UInt(1))
 
-    reg sync_A : UInt<10>, clk2, reset2
+    reg sync_A : UInt<10>, clk2, reset2, UInt(0)
     sync_A <= src
-    reg sync_B : UInt<10>, clk2, reset2
+    reg sync_B : UInt<10>, clk2, reset2, UInt(0)
     sync_B <= sync_A
 
     sink <= sync_B