diff options
| author | azidar | 2015-12-12 14:37:41 -0800 |
|---|---|---|
| committer | azidar | 2016-01-16 14:28:17 -0800 |
| commit | 28e4c6a09011cafdd1e3533118f7c3499e0d3dc6 (patch) | |
| tree | 42e8e2ed50a254f7fea61bc0a56d963258463bb5 /test | |
| parent | d9f33f58c94382dfbd22e87e2f85600b9807328f (diff) | |
WIP. Fixed a bunch of tests. Starting on implementing chirrtl, but hit roadblock in assigning clocked ports
Diffstat (limited to 'test')
33 files changed, 250 insertions, 334 deletions
diff --git a/test/features/BulkConnect.fir b/test/features/BulkConnect.fir index a57ce199..1b68bbdc 100644 --- a/test/features/BulkConnect.fir +++ b/test/features/BulkConnect.fir @@ -2,7 +2,7 @@ ;CHECK: Expand Connects circuit Top : module Top : - wire a : { w : UInt<42>} + wire a : { w : UInt} a.w <= UInt(1) wire b : { w : UInt<42>, x : UInt<20>} b.w <= UInt(1) diff --git a/test/features/InitAccessor.fir b/test/features/InitAccessor.fir index 5a81a62e..6261ec01 100644 --- a/test/features/InitAccessor.fir +++ b/test/features/InitAccessor.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.v -X verilog -p cT 2>&1 | tee %s.out | FileCheck %s ;CHECK: Done! circuit Top : diff --git a/test/passes/expand-whens/bundle-init.fir b/test/passes/expand-whens/bundle-init.fir index f34dbe1a..c4b9f314 100644 --- a/test/passes/expand-whens/bundle-init.fir +++ b/test/passes/expand-whens/bundle-init.fir @@ -4,10 +4,10 @@ circuit top : module top : input clk : Clock input reset : UInt<1> - reg r : { x : UInt, y : UInt},clk,reset + wire w : { x : UInt, y : UInt} + reg r : { x : UInt, y : UInt},clk,reset,w wire a : UInt wire b : UInt - wire w : { x : UInt, y : UInt} a <= UInt(1) b <= UInt(2) @@ -15,13 +15,12 @@ circuit top : w.y <= a r.x <= a r.y <= b - onreset r <= w -; CHECK: r$x <= mux(reset, w$x, a) -; CHECK: r$y <= mux(reset, w$y, b) +; CHECK: w.x <= b +; CHECK: w.y <= a +; CHECK: r.x <= a +; CHECK: r.y <= b ; CHECK: a <= UInt("h1") ; CHECK: b <= UInt("h2") -; CHECK: w$x <= b -; CHECK: w$y <= a ; CHECK: Finished Expand Whens diff --git a/test/passes/expand-whens/nested-whens.fir b/test/passes/expand-whens/nested-whens.fir index 0a45dac1..9a9d56d4 100644 --- a/test/passes/expand-whens/nested-whens.fir +++ b/test/passes/expand-whens/nested-whens.fir @@ -6,13 +6,13 @@ circuit top : input reset : UInt<1> wire p : UInt wire q : UInt - reg r : UInt, clk, reset wire a : UInt wire b : UInt wire x : UInt wire y : UInt wire z : UInt wire w : UInt + reg r : UInt, clk, reset, w p <= UInt(1) q <= UInt(1) a <= UInt(1) @@ -22,13 +22,11 @@ circuit top : z <= UInt(1) w <= UInt(1) - onreset r <= w when p : - onreset r <= x r <= a when q : - onreset r <= y r <= b r <= z -; CHECK: r <= mux(reset, mux(q, y, mux(p, x, w)), z) +; CHECK: r <= z ; CHECK: Finished Expand Whens +; CHECK: Done! diff --git a/test/passes/expand-whens/non-ref.fir b/test/passes/expand-whens/non-ref.fir index 730151e1..dd3ae665 100644 --- a/test/passes/expand-whens/non-ref.fir +++ b/test/passes/expand-whens/non-ref.fir @@ -9,4 +9,4 @@ circuit top : ; CHECK-NOT: wire x : UInt<1> ; CHECK: Finished Expand Whens - +; CHECK: Done! diff --git a/test/passes/expand-whens/one-when.fir b/test/passes/expand-whens/one-when.fir index 53616b0e..6eb341d7 100644 --- a/test/passes/expand-whens/one-when.fir +++ b/test/passes/expand-whens/one-when.fir @@ -1,20 +1,25 @@ ; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s +; XFAIL: * ; CHECK: Expand Whens circuit top : module top : input clk : Clock input reset : UInt<1> - cmem m : UInt<1>[2], clk + mem m : + data-type => UInt<1> + depth => 2 + read-latency => 0 + write-latency => 1 wire i : UInt<1> wire p : UInt<1> wire j : UInt<1> j <= UInt(1) - reg r : UInt<1>, clk, reset + reg r : UInt<1>, clk, reset,i p <= j when p : - onreset r <= i + infer accessor a = m[i] i <= a infer accessor b = m[i] @@ -29,7 +34,6 @@ circuit top : p <= i when e : p <= p - onreset r <= p r <= p diff --git a/test/passes/expand-whens/partial-init.fir b/test/passes/expand-whens/partial-init.fir index f2b9c2e1..490ac995 100644 --- a/test/passes/expand-whens/partial-init.fir +++ b/test/passes/expand-whens/partial-init.fir @@ -5,7 +5,19 @@ circuit top : module top : input clk : Clock input reset : UInt<1> - reg r : UInt<1>[10],clk,reset + poison x : UInt<1> + wire init : UInt<1>[10] + init[0] <= x + init[1] <= x + init[2] <= x + init[3] <= UInt(3) + init[4] <= x + init[5] <= x + init[6] <= x + init[7] <= x + init[8] <= x + init[9] <= x + reg r : UInt<1>[10],clk,reset,init r[0] <= UInt(1) r[1] <= UInt(1) r[2] <= UInt(1) @@ -16,6 +28,6 @@ circuit top : r[7] <= UInt(1) r[8] <= UInt(1) r[9] <= UInt(1) - onreset r[3] <= UInt(0) ; CHECK: Finished Expand Whens +; CHECK: Done! diff --git a/test/passes/expand-whens/reg-dwc.fir b/test/passes/expand-whens/reg-dwc.fir index 30132723..024b527c 100644 --- a/test/passes/expand-whens/reg-dwc.fir +++ b/test/passes/expand-whens/reg-dwc.fir @@ -5,7 +5,7 @@ circuit top : input reset : UInt<1> wire p : UInt p <= UInt(1) - reg r : UInt,clk,reset + reg r : UInt,clk,reset,r when p : r <= UInt(2) @@ -16,8 +16,9 @@ circuit top : ; CHECK: wire p : UInt ; CHECK: reg r : UInt ; CHECK: p <= UInt("h1") -; CHECK: when p : r <= UInt("h2") +; CHECK: r <= mux(p, UInt("h2"), r) ; CHECK: Finished Expand Whens +; CHECK: Done! diff --git a/test/passes/expand-whens/reg-dwoc.fir b/test/passes/expand-whens/reg-dwoc.fir deleted file mode 100644 index 002f34a5..00000000 --- a/test/passes/expand-whens/reg-dwoc.fir +++ /dev/null @@ -1,23 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p cd 2>&1 | tee %s.out | FileCheck %s -circuit top : - module top : - input clk : Clock - input reset : UInt<1> - wire p : UInt - p <= UInt(1) - reg r : UInt,clk,reset - when p : - onreset r <= UInt(1) - r <= UInt(2) - -; CHECK: Expand Whens - -; CHECK: circuit top : -; CHECK: module top : -; CHECK: wire p : UInt -; CHECK: reg r : UInt, clk, reset -; CHECK: p <= UInt("h1") -; CHECK: when p : r <= mux(reset, UInt("h1"), UInt("h2")) - -; CHECK: Finished Expand Whens - diff --git a/test/passes/expand-whens/reg-wdc.fir b/test/passes/expand-whens/reg-wdc.fir index 33cac75e..4ddea427 100644 --- a/test/passes/expand-whens/reg-wdc.fir +++ b/test/passes/expand-whens/reg-wdc.fir @@ -6,7 +6,7 @@ circuit top : wire p : UInt p <= UInt(1) when p : - reg r : UInt,clk,reset + reg r : UInt,clk,reset,r r <= UInt(2) ; CHECK: Expand Whens @@ -14,9 +14,10 @@ circuit top : ; CHECK: circuit top : ; CHECK: module top : ; CHECK: wire p : UInt -; CHECK: reg r : UInt, clk, reset +; CHECK: reg r : UInt<2>, clk, reset, r ; CHECK: p <= UInt("h1") -; CHECK-NOT: when p : r <= UInt("h2") +; CHECK-NOT: r <= mux(p, UInt("h2"), r) +; CHECK: r <= UInt("h2") ; CHECK: Finished Expand Whens diff --git a/test/passes/expand-whens/reg-wdoc.fir b/test/passes/expand-whens/reg-wdoc.fir deleted file mode 100644 index 1d535aca..00000000 --- a/test/passes/expand-whens/reg-wdoc.fir +++ /dev/null @@ -1,23 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -circuit top : - module top : - input clk : Clock - input reset : UInt<1> - wire p : UInt - p <= UInt(1) - when p : - reg r : UInt,clk,reset - onreset r <= UInt(1) - r <= UInt(2) - -; CHECK: Expand Whens - -; CHECK: circuit top : -; CHECK: module top : -; CHECK: wire p : UInt -; CHECK: reg r : UInt, clk, reset -; CHECK: p <= UInt("h1") -; CHECK-NOT: when p : r <= mux(reset, UInt("h1"), UInt("h2")) - -; CHECK: Finished Expand Whens - diff --git a/test/passes/expand-whens/scoped-reg.fir b/test/passes/expand-whens/scoped-reg.fir deleted file mode 100644 index edce1e1e..00000000 --- a/test/passes/expand-whens/scoped-reg.fir +++ /dev/null @@ -1,21 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -circuit top : - module top : - input clk : Clock - input reset : UInt<1> - wire p : UInt - p <= UInt(1) - when p : - reg r : UInt, clk, reset - onreset r <= UInt(1) - r <= UInt(2) - -; CHECK: Expand Whens - -; CHECK: circuit top : -; CHECK: module top : -; CHECK: wire p : UInt -; CHECK: reg r : UInt, clk, reset -; CHECK-NOT: when p : r <= mux(reset, UInt("h00000001"), UInt("h00000002")) - -; CHECK: Finished Expand Whens diff --git a/test/passes/expand-whens/two-when.fir b/test/passes/expand-whens/two-when.fir index 05179cf5..38e02c5e 100644 --- a/test/passes/expand-whens/two-when.fir +++ b/test/passes/expand-whens/two-when.fir @@ -1,4 +1,5 @@ ; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s +; XFAIL: * ; CHECK: Expand Whens circuit top : diff --git a/test/passes/infer-widths/gcd.fir b/test/passes/infer-widths/gcd.fir index 4de2a539..7745a933 100644 --- a/test/passes/infer-widths/gcd.fir +++ b/test/passes/infer-widths/gcd.fir @@ -14,10 +14,8 @@ circuit top : input clk : Clock input reset : UInt<1> output z : UInt<16> - reg x : UInt,clk,reset - reg y : UInt,clk,reset - onreset x <= UInt(0) - onreset y <= UInt(42) + reg x : UInt,clk,reset,UInt(0) + reg y : UInt,clk,reset,UInt(42) when gt(x, y) : inst s of subtracter s.x <= x diff --git a/test/passes/infer-widths/shr.fir b/test/passes/infer-widths/shr.fir index e5a9e15a..67b6896e 100644 --- a/test/passes/infer-widths/shr.fir +++ b/test/passes/infer-widths/shr.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p cd 2>&1 | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s ;CHECK: Infer Widths ; CHECK: Finished Infer Widths @@ -20,14 +20,11 @@ circuit MemSerdes : node T_218961 = cat(wide.req_cmd.bits.tag, wide.req_cmd.bits.rw) node T_218962 = cat(wide.req_cmd.bits.addr, T_218961) - reg out_buf : UInt, clock, reset - reg in_buf : UInt, clock, reset - reg state : UInt<3>, clock, reset - onreset state <= UInt<3>("h00") - reg send_cnt : UInt<3>, clock, reset - onreset send_cnt <= UInt<3>("h00") - reg data_send_cnt : UInt<2>, clock, reset - onreset data_send_cnt <= UInt<2>("h00") + reg out_buf : UInt, clock, reset, out_buf + reg in_buf : UInt, clock, reset, in_buf + reg state : UInt<3>, clock, reset,UInt<3>("h00") + reg send_cnt : UInt<3>, clock, reset, UInt<3>("h00") + reg data_send_cnt : UInt<2>, clock, reset, UInt<2>("h00") node T_218984 = eq(send_cnt, UInt<2>("h02")) node adone = and(narrow.req.ready, T_218984) node T_218987 = eq(send_cnt, UInt<3>("h07")) @@ -96,12 +93,9 @@ circuit MemSerdes : node T_219021 = mux(T_219020, UInt<3>("h00"), UInt<3>("h03")) state <= T_219021 send_cnt <= UInt<1>("h00") - reg recv_cnt : UInt<4>, clock, reset - onreset recv_cnt <= UInt<4>("h00") - reg data_recv_cnt : UInt<2>, clock, reset - onreset data_recv_cnt <= UInt<2>("h00") - reg resp_val : UInt<1>, clock, reset - onreset resp_val <= UInt<1>("h00") + reg recv_cnt : UInt<4>, clock, reset, UInt<4>("h00") + reg data_recv_cnt : UInt<2>, clock, reset, UInt<2>("h00") + reg resp_val : UInt<1>, clock, reset, UInt<1>("h00") resp_val <= UInt<1>("h00") when narrow.resp.valid : node T_219031 = addw(recv_cnt, UInt<1>("h01")) diff --git a/test/passes/infer-widths/simple.fir b/test/passes/infer-widths/simple.fir index e0d23c37..dc3007f9 100644 --- a/test/passes/infer-widths/simple.fir +++ b/test/passes/infer-widths/simple.fir @@ -7,7 +7,7 @@ circuit top : input reset : UInt<1> wire e : UInt<30> e <= UInt(1) - reg y : UInt,clk,reset + reg y : UInt,clk,reset,y y <= e wire a : UInt<20> @@ -23,4 +23,5 @@ circuit top : ; CHECK: Finished Infer Widths +; CHECK: Done! diff --git a/test/passes/lower-to-ground/accessor.fir b/test/passes/lower-to-ground/accessor.fir deleted file mode 100644 index c712fdc2..00000000 --- a/test/passes/lower-to-ground/accessor.fir +++ /dev/null @@ -1,32 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p cd 2>&1 | tee %s.out | FileCheck %s - -; CHECK: Lower To Ground -circuit top : - module top : - input clk : Clock - wire i : UInt<2> - wire j : UInt<32> - - wire a : UInt<32>[4] - ; CHECK: wire a{{[_$]+}}0 : UInt<32> - ; CHECK: wire a{{[_$]+}}1 : UInt<32> - ; CHECK: wire a{{[_$]+}}2 : UInt<32> - ; CHECK: wire a{{[_$]+}}3 : UInt<32> - - infer accessor b = a[i] - ; CHECK: indexer b = (a{{[_$]+}}0 a{{[_$]+}}1 a{{[_$]+}}2 a{{[_$]+}}3)[i] : UInt<32> - j <= b - - infer accessor c = a[i] - ; CHECK: indexer (a{{[_$]+}}0 a{{[_$]+}}1 a{{[_$]+}}2 a{{[_$]+}}3)[i] = c : UInt<32> - c <= j - - cmem p : UInt<32>[4],clk - infer accessor t = p[i] - ; CHECK: read accessor t = p[i] - j <= t - infer accessor r = p[i] - ; CHECK: write accessor r = p[i] - r <= j - -; CHECK: Finished Lower To Ground diff --git a/test/passes/lower-to-ground/bundle-vecs.fir b/test/passes/lower-to-ground/bundle-vecs.fir index b0de26f4..719033cb 100644 --- a/test/passes/lower-to-ground/bundle-vecs.fir +++ b/test/passes/lower-to-ground/bundle-vecs.fir @@ -1,9 +1,9 @@ ; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; CHECK: Lower To Ground +; CHECK: Lower Types circuit top : module top : - wire i : UInt + input i : UInt<1> wire j : { x : UInt<32>, flip y : UInt<32> } wire a : { x : UInt<32>, flip y : UInt<32> }[2] @@ -11,17 +11,34 @@ circuit top : ; CHECK: wire a{{[_$]+}}0{{[_$]+}}y : UInt<32> ; CHECK: wire a{{[_$]+}}1{{[_$]+}}x : UInt<32> ; CHECK: wire a{{[_$]+}}1{{[_$]+}}y : UInt<32> + a[0].x <= UInt(0) + a[0].y <= UInt(0) + a[1].x <= UInt(0) + a[1].y <= UInt(0) - infer accessor b = a[i] - ; CHECK: indexer b{{[_$]+}}x = (a{{[_$]+}}0{{[_$]+}}x a{{[_$]+}}1{{[_$]+}}x)[i] : UInt<32> - ; CHECK: indexer (a{{[_$]+}}0{{[_$]+}}y a{{[_$]+}}1{{[_$]+}}y)[i] = b{{[_$]+}}y : UInt<32> - j <= b - - infer accessor c = a[i] - ; CHECK: indexer (a{{[_$]+}}0{{[_$]+}}x a{{[_$]+}}1{{[_$]+}}x)[i] = c{{[_$]+}}x : UInt<32> - ; CHECK: indexer c{{[_$]+}}y = (a{{[_$]+}}0{{[_$]+}}y a{{[_$]+}}1{{[_$]+}}y)[i] : UInt<32> - c <= j + j <= a[i] + a[i] <= j +;CHECK: wire GEN : UInt<32> +;CHECK: wire GEN_1 : UInt<32> +;CHECK: wire GEN_2 : UInt<32> +;CHECK: wire GEN_3 : UInt<32> +;CHECK: j_x <= GEN +;CHECK: j_y <= GEN_3 +;CHECK: node a_0_x = eqv(UInt("h0"), i) +;CHECK: a_0_x <= mux(a_0_x, GEN_2, UInt("h0")) +;CHECK: node a_0_y = eqv(UInt("h0"), i) +;CHECK: a_0_y <= mux(a_0_y, GEN_1, UInt("h0")) +;CHECK: node a_1_x = eqv(UInt("h1"), i) +;CHECK: a_1_x <= mux(a_1_x, GEN_2, UInt("h0")) +;CHECK: node a_1_y = eqv(UInt("h1"), i) +;CHECK: a_1_y <= mux(a_1_y, GEN_1, UInt("h0")) +;CHECK: node GEN_4 = eqv(UInt("h1"), i) +;CHECK: GEN <= mux(GEN_4, a_1_x, a_0_x) +;CHECK: GEN_1 <= j_y +;CHECK: GEN_2 <= j_x +;CHECK: node GEN_5 = eqv(UInt("h1"), i) +;CHECK: GEN_3 <= mux(GEN_5, a_1_y, a_0_y) -; CHECK: Finished Lower To Ground +; CHECK: Finished Lower Types diff --git a/test/passes/lower-to-ground/bundle.fir b/test/passes/lower-to-ground/bundle.fir index ccf942ee..b2ea2d63 100644 --- a/test/passes/lower-to-ground/bundle.fir +++ b/test/passes/lower-to-ground/bundle.fir @@ -4,6 +4,8 @@ circuit top : module m : input a : { x : UInt<5>, flip y: SInt<5>} output b : { x : UInt<5>, flip y: SInt<5>} + a.y <= UInt(0) + b.x <= UInt(0) module top : input c : { x : UInt<5>[5], flip y : { x : UInt<5>[3], flip y : SInt<5> } } wire a : { x : UInt<5>, flip y : SInt<5>} @@ -13,8 +15,16 @@ circuit top : i.a <= a b <= i.b wire d : UInt<5>[5] + d[0] <= UInt(0) + d[1] <= UInt(0) + d[2] <= UInt(0) + d[3] <= UInt(0) + d[4] <= UInt(0) + c.y.x[0] <= UInt(0) + c.y.x[1] <= UInt(0) + c.y.x[2] <= UInt(0) -;CHECK: Lower To Ground +;CHECK: Lower Types ;CHECK: circuit top : ;CHECK: module m : ;CHECK: input a{{[_$]+}}x : UInt<5> @@ -35,16 +45,16 @@ circuit top : ;CHECK: wire a{{[_$]+}}y : SInt<5> ;CHECK: wire b{{[_$]+}}x : UInt<5> ;CHECK: wire b{{[_$]+}}y : SInt<5> -;CHECK: a{{[_$]+}}x <= b{{[_$]+}}x -;CHECK: b{{[_$]+}}y <= a{{[_$]+}}y ;CHECK: inst i of m -;CHECK: i.a{{[_$]+}}x <= a{{[_$]+}}x -;CHECK: a{{[_$]+}}y <= i.a{{[_$]+}}y -;CHECK: b{{[_$]+}}x <= i.b{{[_$]+}}x -;CHECK: i.b{{[_$]+}}y <= b{{[_$]+}}y ;CHECK: wire d{{[_$]+}}0 : UInt<5> ;CHECK: wire d{{[_$]+}}1 : UInt<5> ;CHECK: wire d{{[_$]+}}2 : UInt<5> ;CHECK: wire d{{[_$]+}}3 : UInt<5> ;CHECK: wire d{{[_$]+}}4 : UInt<5> -;CHECK: Finished Lower To Ground +;CHECK: a{{[_$]+}}x <= b{{[_$]+}}x +;CHECK: a{{[_$]+}}y <= i.a{{[_$]+}}y +;CHECK: b{{[_$]+}}x <= i.b{{[_$]+}}x +;CHECK: b{{[_$]+}}y <= a{{[_$]+}}y +;CHECK: i.a{{[_$]+}}x <= a{{[_$]+}}x +;CHECK: i.b{{[_$]+}}y <= b{{[_$]+}}y +;CHECK: Finished Lower Types diff --git a/test/passes/lower-to-ground/instance.fir b/test/passes/lower-to-ground/instance.fir index ecc2d40b..e0175f34 100644 --- a/test/passes/lower-to-ground/instance.fir +++ b/test/passes/lower-to-ground/instance.fir @@ -8,9 +8,14 @@ circuit top : module sink : input data : UInt<16> output ready : UInt<1> + ready <= UInt(1) module top: wire connect : { data : UInt<16>, flip ready: UInt<1> } + connect.ready <= UInt(1) + connect.data <= UInt(1) wire connect2 : { flip data : UInt<16>, ready: UInt<1> } + connect2.ready <= UInt(1) + connect2.data <= UInt(1) inst src of source inst snk of sink connect <= src @@ -25,11 +30,12 @@ circuit top : ; CHECK: Finished Resolve Genders -; CHECK: Lower To Ground +; CHECK: Lower Types ; CHECK: connect{{[_$]+}}data@<g:f> <= src@<g:m>.data@<g:m> +; CHECK: connect2{{[_$]+}}ready@<g:f> <= snk@<g:m>.ready@<g:m> ; CHECK: src@<g:m>.ready@<g:f> <= connect{{[_$]+}}ready@<g:m> ; CHECK: snk@<g:m>.data@<g:f> <= connect2{{[_$]+}}data@<g:m> -; CHECK: connect2{{[_$]+}}ready@<g:f> <= snk@<g:m>.ready@<g:m> -; CHECK: Finished Lower To Ground +; CHECK: Finished Lower Types +; CHECK: Done! diff --git a/test/passes/lower-to-ground/nested-vec.fir b/test/passes/lower-to-ground/nested-vec.fir index 0c58f267..0d4f5bf0 100644 --- a/test/passes/lower-to-ground/nested-vec.fir +++ b/test/passes/lower-to-ground/nested-vec.fir @@ -1,10 +1,10 @@ ; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; CHECK: Lower To Ground +; CHECK: Lower Types circuit top : module top : input clk : Clock - wire i : UInt + input i : UInt<1> wire j : { x : UInt<32>, flip y : UInt<32> } wire k : { x : UInt<32>, y : UInt<32> } @@ -13,23 +13,56 @@ circuit top : ; CHECK: wire a{{[_$]+}}0{{[_$]+}}y : UInt<32> ; CHECK: wire a{{[_$]+}}1{{[_$]+}}x : UInt<32> ; CHECK: wire a{{[_$]+}}1{{[_$]+}}y : UInt<32> + a[0].x <= UInt(0) + a[0].y <= UInt(0) + a[1].x <= UInt(0) + a[1].y <= UInt(0) + j.x <= UInt(0) + j.y <= UInt(0) + k.x <= UInt(0) + k.y <= UInt(0) - infer accessor b = a[i] - ; CHECK: indexer b{{[_$]+}}x = (a{{[_$]+}}0{{[_$]+}}x a{{[_$]+}}1{{[_$]+}}x)[i] : UInt<32> - ; CHECK: indexer (a{{[_$]+}}0{{[_$]+}}y a{{[_$]+}}1{{[_$]+}}y)[i] = b{{[_$]+}}y : UInt<32> + wire b : { x : UInt<32>, flip y : UInt<32> } + b <= a[i] j <= b - cmem m : { x : UInt<32>, y : UInt<32> }[2],clk - ; CHECK: cmem m{{[_$]+}}x : UInt<32>[2] - ; CHECK: cmem m{{[_$]+}}y : UInt<32>[2] + mem m : + data-type => { x : UInt<32>, y : UInt<32> } + depth => 2 + read-latency => 0 + write-latency => 1 + writer => c - infer accessor c = m[i] ; MALE - ; CHECK: accessor c{{[_$]+}}x = m{{[_$]+}}x[i] - ; CHECK: accessor c{{[_$]+}}y = m{{[_$]+}}y[i] + m.c.addr <= i + m.c.clk <= clk + m.c.en <= UInt(1) + m.c.mask.x <= UInt(1) + m.c.mask.y <= UInt(1) + m.c.data <= k - c <= k - ; CHECK: c{{[_$]+}}x <= k{{[_$]+}}x - ; CHECK: c{{[_$]+}}y <= k{{[_$]+}}y +;CHECK: mem m_x : +;CHECK: data-type: UInt<32> +;CHECK: depth: 2 +;CHECK: write-latency: 1 +;CHECK: read-latency: 0 +;CHECK: writer: c +;CHECK: mem m_y : +;CHECK: data-type: UInt<32> +;CHECK: depth: 2 +;CHECK: write-latency: 1 +;CHECK: read-latency: 0 +;CHECK: writer: c +;CHECK: m_x.c.data <= k_x +;CHECK: m_y.c.data <= k_y +;CHECK: m_x.c.mask <= UInt("h1") +;CHECK: m_y.c.mask <= UInt("h1") +;CHECK: m_x.c.addr <= i +;CHECK: m_y.c.addr <= i +;CHECK: m_x.c.en <= UInt("h1") +;CHECK: m_y.c.en <= UInt("h1") +;CHECK: m_x.c.clk <= clk +;CHECK: m_y.c.clk <= clk -; CHECK: Finished Lower To Ground +; CHECK: Finished Lower Types +; CHECK: Done! diff --git a/test/passes/lower-to-ground/register.fir b/test/passes/lower-to-ground/register.fir index 99f63153..66d1cfb3 100644 --- a/test/passes/lower-to-ground/register.fir +++ b/test/passes/lower-to-ground/register.fir @@ -1,23 +1,21 @@ ; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; CHECK: Lower To Ground +; CHECK: Lower Types circuit top : module top : input a : UInt<16> input b : UInt<16> input clk : Clock input reset : UInt<1> - output z : UInt - reg r1 : { x : UInt, y : SInt },clk,reset wire q : { x : UInt, y : SInt } - onreset r1 <= q + q.x <= UInt(0) + q.y <= SInt(0) + reg r1 : { x : UInt, y : SInt },clk,reset,q - ; CHECK: reg r1{{[_$]+}}x : UInt - ; CHECK: reg r1{{[_$]+}}y : SInt ; CHECK: wire q{{[_$]+}}x : UInt ; CHECK: wire q{{[_$]+}}y : SInt - ; CHECK: onreset r1{{[_$]+}}x <= q{{[_$]+}}x - ; CHECK: onreset r1{{[_$]+}}y <= q{{[_$]+}}y + ; CHECK: reg r1{{[_$]+}}x : UInt<1>, clk, reset, q_x + ; CHECK: reg r1{{[_$]+}}y : SInt<1>, clk, reset, q_y -; CHECK: Finished Lower To Ground +; CHECK: Finished Lower Types diff --git a/test/passes/resolve-genders/accessor.fir b/test/passes/resolve-genders/accessor.fir deleted file mode 100644 index 64797ece..00000000 --- a/test/passes/resolve-genders/accessor.fir +++ /dev/null @@ -1,34 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p cg 2>&1 | tee %s.out | FileCheck %s - -;CHECK: Resolve Genders -circuit top : - module top : - wire m : UInt<32>[2][2][2] - m[0][0][0] <= UInt(1) - m[1][0][0] <= UInt(1) - m[0][1][0] <= UInt(1) - m[1][1][0] <= UInt(1) - m[0][0][1] <= UInt(1) - m[1][0][1] <= UInt(1) - m[0][1][1] <= UInt(1) - m[1][1][1] <= UInt(1) - wire i : UInt - i <= UInt(1) - infer accessor a = m[i] ;CHECK: accessor a = m@<g:m>[i@<g:m>]@<g:m> - infer accessor b = a[i] ;CHECK: accessor b = a@<g:m>[i@<g:m>]@<g:m> - infer accessor c = b[i] ;CHECK: accessor c = b@<g:m>[i@<g:m>]@<g:m> - wire j : UInt - j <= c - - infer accessor x = m[i] ;CHECK: accessor x = m@<g:f>[i@<g:m>]@<g:f> - x[0][0] <= UInt(1) - x[1][0] <= UInt(1) - x[0][1] <= UInt(1) - x[1][1] <= UInt(1) - infer accessor y = x[i] ;CHECK: accessor y = x@<g:f>[i@<g:m>]@<g:f> - y[0] <= UInt(1) - y[1] <= UInt(1) - infer accessor z = y[i] ;CHECK: accessor z = y@<g:f>[i@<g:m>]@<g:f> - z <= j - -; CHECK: Finished Resolve Genders diff --git a/test/passes/resolve-genders/gcd.fir b/test/passes/resolve-genders/gcd.fir index 85b6474b..4d7772d9 100644 --- a/test/passes/resolve-genders/gcd.fir +++ b/test/passes/resolve-genders/gcd.fir @@ -16,15 +16,12 @@ circuit top : input reset : UInt<1> output z : UInt<16> output v : UInt<1> - reg x : UInt,clk,reset - reg y : UInt,clk,reset + reg x : UInt,clk,reset,UInt(0) + reg y : UInt,clk,reset,UInt(42) ; CHECK: reg x : UInt - onreset x <= UInt(0) - onreset y <= UInt(42) when gt(x, y) : - ;CHECK: when gt(x@<g:m>, y@<g:m>) : + ;CHECK: when gt(x@<g:m>, y@<g:m>)@<g:m> : inst s of subtracter - ;CHECK: inst s of subtracter@<g:m> s.x <= x s.y <= y x <= s.z diff --git a/test/passes/resolve-genders/ports.fir b/test/passes/resolve-genders/ports.fir index 57c8721d..246fb9ac 100644 --- a/test/passes/resolve-genders/ports.fir +++ b/test/passes/resolve-genders/ports.fir @@ -11,11 +11,11 @@ circuit top : output ready : UInt<1> module top: wire connect : { data : UInt<16>, flip ready: UInt<1> } - inst src of source ;CHECK: inst src of source@<g:m> - inst snk of sink ;CHECK: inst snk of sink@<g:m> - connect.data <= src.data ;CHECK: connect@<g:f>.data@<g:f> := src@<g:m>.data@<g:m> - src.ready <= connect.ready ;CHECK: src@<g:m>.ready@<g:f> := connect@<g:f>.ready@<g:m> - snk.data <= connect.data ;CHECK: snk@<g:m>.data@<g:f> := connect@<g:m>.data@<g:m> - connect.ready <= snk.ready ;CHECK: connect@<g:m>.ready@<g:f> := snk@<g:m>.ready@<g:m> + inst src of source + inst snk of sink + connect.data <= src.data ;CHECK: connect@<g:f>.data@<g:f> <= src@<g:m>.data@<g:m> + src.ready <= connect.ready ;CHECK: src@<g:m>.ready@<g:f> <= connect@<g:f>.ready@<g:m> + snk.data <= connect.data ;CHECK: snk@<g:m>.data@<g:f> <= connect@<g:m>.data@<g:m> + connect.ready <= snk.ready ;CHECK: connect@<g:m>.ready@<g:f> <= snk@<g:m>.ready@<g:m> ; CHECK: Finished Resolve Genders diff --git a/test/passes/resolve-genders/rdwraccessor.fir b/test/passes/resolve-genders/rdwraccessor.fir deleted file mode 100644 index 35f88071..00000000 --- a/test/passes/resolve-genders/rdwraccessor.fir +++ /dev/null @@ -1,31 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p cg 2>&1 | tee %s.out | FileCheck %s - -;CHECK: Resolve Genders -circuit top : - module top : - wire m : UInt<32>[2][2][2] - m[0][0][0] <= UInt(1) - m[1][0][0] <= UInt(1) - m[0][1][0] <= UInt(1) - m[1][1][0] <= UInt(1) - m[0][0][1] <= UInt(1) - m[1][0][1] <= UInt(1) - m[0][1][1] <= UInt(1) - m[1][1][1] <= UInt(1) - wire i : UInt - i <= UInt(1) - rdwr accessor a = m[i] ;CHECK: accessor a = m@<g:b>[i@<g:m>]@<g:b> - rdwr accessor b = a[i] ;CHECK: accessor b = a@<g:b>[i@<g:m>]@<g:b> - rdwr accessor c = b[i] ;CHECK: accessor c = b@<g:b>[i@<g:m>]@<g:b> - wire j : UInt - j <= c - c <= j - - rdwr accessor x = m[i] ;CHECK: accessor x = m@<g:b>[i@<g:m>]@<g:b> - rdwr accessor y = x[i] ;CHECK: accessor y = x@<g:b>[i@<g:m>]@<g:b> - rdwr accessor z = y[i] ;CHECK: accessor z = y@<g:b>[i@<g:m>]@<g:b> - z <= j - j <= z - -; CHECK: Finished Resolve Genders -; CHECK: Done! diff --git a/test/passes/resolve-genders/subbundle.fir b/test/passes/resolve-genders/subbundle.fir index f734d08b..0d0dd574 100644 --- a/test/passes/resolve-genders/subbundle.fir +++ b/test/passes/resolve-genders/subbundle.fir @@ -1,13 +1,13 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.v -X verilog -p cT 2>&1 | tee %s.out | FileCheck %s -;CHECK: Lower To Ground +;CHECK: Lower Types circuit top : module top : input clk : Clock input reset : UInt<1> wire w : { flip x : UInt<10>} - reg r : { flip x : UInt<10>},clk,reset - w <= r ; CHECK r$x := w$x - w.x <= r.x ; CHECK w$x := r$x -; CHECK: Finished Lower To Ground + reg r : { flip x : UInt<10>},clk,reset,w + w <= r ; CHECK r_x := w_x + w.x <= r.x ; CHECK w_x := r_x +; CHECK: Finished Lower Types diff --git a/test/passes/resolve-kinds/gcd.fir b/test/passes/resolve-kinds/gcd.fir index 3583c81a..bb978972 100644 --- a/test/passes/resolve-kinds/gcd.fir +++ b/test/passes/resolve-kinds/gcd.fir @@ -16,14 +16,12 @@ circuit top : input e : UInt<1> output z : UInt<16> output v : UInt<1> - reg x : UInt,clk,reset - reg y : UInt,clk,reset - onreset x <= UInt(0) - onreset y <= UInt(42) + reg x : UInt,clk,reset,UInt(0) + reg y : UInt,clk,reset,UInt(42) when gt(x, y) : inst s of subtracter s.x <= x - ;CHECK: s@<k:inst>.x <= x@<k:reg> + ;CHECK: s@<k:inst>.x@<k:inst> <= x@<k:reg> s.y <= y x <= s.z else : @@ -43,14 +41,13 @@ circuit top : input reset : UInt<1> output z : UInt inst i of gcd - ;CHECK: inst i of gcd@<k:module> i.a <= a i.b <= b i.clk <= clk i.reset <= reset i.e <= UInt(1) z <= i.z - ;CHECK: z@<k:port> <= i@<k:inst>.z + ;CHECK: z@<k:port> <= i@<k:inst>.z@<k:inst> ; CHECK: Finished Resolve Kinds diff --git a/test/passes/split-exp/gcd.fir b/test/passes/split-exp/gcd.fir index 1f032c04..e651f41a 100644 --- a/test/passes/split-exp/gcd.fir +++ b/test/passes/split-exp/gcd.fir @@ -14,10 +14,8 @@ circuit top : input b : UInt<16> input e : UInt<1> output z : UInt<16> - reg x : UInt,clk,reset - reg y : UInt,clk,reset - onreset x <= UInt(0) - onreset y <= UInt(42) + reg x : UInt,clk,reset,UInt(0) + reg y : UInt,clk,reset,UInt(42) when gt(x, y) : inst s of subtracter s.x <= x diff --git a/test/passes/split-exp/primop.fir b/test/passes/split-exp/primop.fir index caccf57b..cdbd4e77 100644 --- a/test/passes/split-exp/primop.fir +++ b/test/passes/split-exp/primop.fir @@ -12,7 +12,8 @@ circuit Top : wire x : UInt<1> x <= not(UInt(1)) - infer accessor a = m[x] + wire a : UInt<1> + a <= m[x] out <= a diff --git a/test/passes/split-exp/split-in-when.fir b/test/passes/split-exp/split-in-when.fir index b72a1d95..a6d0a2c5 100644 --- a/test/passes/split-exp/split-in-when.fir +++ b/test/passes/split-exp/split-in-when.fir @@ -9,15 +9,16 @@ circuit Top : input b : UInt<10> input c : UInt<10> - reg out : UInt<10>,clk,p + reg out : UInt<10>,clk,p,a when bit(subw(a,c),3) : out <= mux(eqv(bits(UInt(32),4,0),UInt(13)),addw(a,addw(b,c)),subw(c,b)) -;CHECK: node F = subw(a, c) -;CHECK: node out_1 = eqv(UInt("h0"), UInt("hd")) -;CHECK: node out_3 = addw(b, c) -;CHECK: node out_2 = addw(a, out_3) -;CHECK: node out_4 = subw(c, b) -;CHECK: when bit(F, 3) : out <= mux(out_1, out_2, out_4) +;CHECK: node out_1 = subw(a, c) +;CHECK: node out_2 = bit(out_1, 3) +;CHECK: node out_3 = eqv(UInt("h0"), UInt("hd")) +;CHECK: node out_4 = addw(b, c) +;CHECK: node out_5 = addw(a, out_4) +;CHECK: node out_6 = subw(c, b) +;CHECK: node out_7 = mux(out_3, out_5, out_6) ;CHECK: Finished Split Expressions diff --git a/test/passes/to-verilog/rd-mem.fir b/test/passes/to-verilog/rd-mem.fir index 0bb86851..7146f026 100644 --- a/test/passes/to-verilog/rd-mem.fir +++ b/test/passes/to-verilog/rd-mem.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.v -X verilog &> %s.out ; cat %s.v | FileCheck %s +; RUN: firrtl -i %s -o %s.v -X verilog -p c &> %s.out ; cat %s.v | FileCheck %s circuit top : module top : @@ -7,36 +7,47 @@ circuit top : input ren : UInt<1> input clk : Clock - smem m : UInt<32>[4],clk - read accessor c = m[index] - rdata <= UInt(0) - when ren : - rdata <= c + mem m : + data-type => UInt<32> + depth => 4 + read-latency => 1 + write-latency => 1 + reader => c + m.c.addr <= index + m.c.en <= ren + m.c.clk <= clk + rdata <= m.c.data -: CHECK: module top( -: CHECK: output [31:0] rdata, -: CHECK: input [1:0] index, -: CHECK: input [0:0] ren, -: CHECK: input [0:0] clk -: CHECK: ); -: CHECK: wire [31:0] c; -: CHECK: reg [31:0] m [0:3]; -: CHECK: reg [1:0] index_1; -: CHECK: `ifndef SYNTHESIS -: CHECK: integer initvar; -: CHECK: initial begin -: CHECK: #0.002; -: CHECK: for (initvar = 0; initvar < 4; initvar = initvar+1) -: CHECK: m[initvar] = {1{$random}}; -: CHECK: index_1 = {1{$random}}; -: CHECK: end -: CHECK: `endif -: CHECK: assign c = m[index_1]; -: CHECK: assign rdata = c; -: CHECK: always @(posedge clk) begin -: CHECK: if(ren) begin -: CHECK: index_1 <= index; -: CHECK: end -: CHECK: end -: CHECK: endmodule -: CHECK: +; CHECK: module top( +; CHECK: output [31:0] rdata, +; CHECK: input [1:0] index, +; CHECK: input ren, +; CHECK: input clk, +; CHECK: ); +; CHECK: reg [31:0] m [0:3]; +; CHECK: wire [31:0] m_c_data; +; CHECK: wire [1:0] m_c_addr; +; CHECK: wire m_c_en; +; CHECK: wire m_c_clk; +; CHECK: reg [1:0] GEN; +; CHECK: reg GEN_1; +; CHECK: assign rdata = m_c_data +; CHECK: assign m_c_addr = index +; CHECK: assign m_c_en = ren +; CHECK: assign m_c_clk = clk +; CHECK: `ifndef SYNTHESIS +; CHECK: integer initvar; +; CHECK: initial begin +; CHECK: #0.002; +; CHECK: for (initvar = 0; initvar < 4; initvar = initvar+1) +; CHECK: m[initvar] = {1{$random}}; +; CHECK: end +; CHECK: `endif +; CHECK: always @(posedge m_c_clk) begin +; CHECK: GEN <= m_c_addr +; CHECK: GEN_1 <= m_c_en +; CHECK: if(GEN_1) begin +; CHECK: m_c_data <= m[GEN] +; CHECK: end +; CHECK: end +; CHECK: endmodule diff --git a/test/passes/to-verilog/shr.fir b/test/passes/to-verilog/shr.fir index 1b8db9e0..d8e889da 100644 --- a/test/passes/to-verilog/shr.fir +++ b/test/passes/to-verilog/shr.fir @@ -1,8 +1,9 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p cTd 2>&1 | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: Infer Widths -;CEHCK: node s1_addr = cat(dtlb<t:{ resp$ppn : UInt<20>}>.resp$ppn<t:UInt<20>>, bits(s1_req$addr<t:UInt<40>>, 11, 0)<t:UInt<12>>)<t:UInt<32>> -;CHECK: Finished Infer Widths +;CHECK: Lower Types +;CHECK: node T_928 = bits(s1_req_addr, 11, 0) +;CHECK: node s1_addr = cat(dtlb.resp_ppn, T_928) +;CHECK: Finished Lower Types circuit HellaCache : module TLB_60 : @@ -14,9 +15,10 @@ circuit HellaCache : input reset : UInt<1> inst dtlb of TLB_60 - reg s1_req : {addr : UInt<40>}, clock, reset - reg s2_req : {addr : UInt<40>}, clock, reset - reg s1_clk_en : UInt<1>, clock, reset + poison init : {addr : UInt<40>} + reg s1_req : {addr : UInt<40>}, clock, reset, init + reg s2_req : {addr : UInt<40>}, clock, reset, init + reg s1_clk_en : UInt<1>, clock, reset, UInt(0) node T_928 = bits(s1_req.addr, 11, 0) node s1_addr = cat(dtlb.resp.ppn, T_928) |