diff options
Diffstat (limited to 'test/passes/lower-to-ground/register.fir')
| -rw-r--r-- | test/passes/lower-to-ground/register.fir | 16 |
1 files changed, 7 insertions, 9 deletions
diff --git a/test/passes/lower-to-ground/register.fir b/test/passes/lower-to-ground/register.fir index 99f63153..66d1cfb3 100644 --- a/test/passes/lower-to-ground/register.fir +++ b/test/passes/lower-to-ground/register.fir @@ -1,23 +1,21 @@ ; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; CHECK: Lower To Ground +; CHECK: Lower Types circuit top : module top : input a : UInt<16> input b : UInt<16> input clk : Clock input reset : UInt<1> - output z : UInt - reg r1 : { x : UInt, y : SInt },clk,reset wire q : { x : UInt, y : SInt } - onreset r1 <= q + q.x <= UInt(0) + q.y <= SInt(0) + reg r1 : { x : UInt, y : SInt },clk,reset,q - ; CHECK: reg r1{{[_$]+}}x : UInt - ; CHECK: reg r1{{[_$]+}}y : SInt ; CHECK: wire q{{[_$]+}}x : UInt ; CHECK: wire q{{[_$]+}}y : SInt - ; CHECK: onreset r1{{[_$]+}}x <= q{{[_$]+}}x - ; CHECK: onreset r1{{[_$]+}}y <= q{{[_$]+}}y + ; CHECK: reg r1{{[_$]+}}x : UInt<1>, clk, reset, q_x + ; CHECK: reg r1{{[_$]+}}y : SInt<1>, clk, reset, q_y -; CHECK: Finished Lower To Ground +; CHECK: Finished Lower Types |