WIP getting through tests

2 files changed, 17 insertions, 17 deletions

diff --git a/test/passes/infer-types/bundle.fir b/test/passes/infer-types/bundle.fir
index 400aecde..12cc58b1 100644
--- a/test/passes/infer-types/bundle.fir
+++ b/test/passes/infer-types/bundle.fir
@@ -1,14 +1,13 @@
 ; RUN: firrtl -i %s -o %s.v -X verilog -p ct 2>&1 | tee %s.out | FileCheck %s
 
-;CHECK: Infer Types
 circuit top :
    module top :
       wire z : { x : UInt, flip y: SInt}
       z.x <= UInt(1)
       z.y <= SInt(1)
-      node x = z.x            ;CHECK: node x = z@<t:{ x : UInt, flip y : SInt}>.x@<t:UInt>
-      node y = z.y            ;CHECK: node y = z@<t:{ x : UInt, flip y : SInt}>.y@<t:SInt>
-      wire a : UInt<3>[10]    ;CHECK: wire a : UInt<3>[10]@<t:UInt>@<t:UInt<3>[10]@<t:UInt>>
+      node x = z.x            
+      node y = z.y            
+      wire a : UInt<3>[10]    
       a[0] <= UInt(1)
       a[1] <= UInt(1)
       a[2] <= UInt(1)
@@ -19,11 +18,15 @@ circuit top :
       a[7] <= UInt(1)
       a[8] <= UInt(1)
       a[9] <= UInt(1)
-      node b = a[2]           ;CHECK: node b = a@<t:UInt<3>[10]@<t:UInt>>[2]@<t:UInt>
-      read accessor c = a[UInt(3)] ;CHECK: read accessor c = a@<t:UInt<3>[10]@<t:UInt>>[UInt("h3")@<t:UInt>]
-; CHECK: Finished Infer Types
+      node b = a[2]           
+      node c = a[UInt(3)]     
+
+;CHECK: Infer Types
+;CHECK: node x = z@<t:{ x : UInt, flip y : SInt}>.x@<t:UInt>
+;CHECK: node y = z@<t:{ x : UInt, flip y : SInt}>.y@<t:SInt>
+;CHECK: wire a : UInt<3>[10]@<t:UInt>@<t:UInt[10]@<t:UInt>>
+;CHECK: node b = a@<t:UInt[10]@<t:UInt>>[2]@<t:UInt>
+;CHECK: node c = a@<t:UInt[10]@<t:UInt>>[UInt("h3")@<t:UInt>]
+;CHECK: Finished Infer Types
 
-; CHECK: Resolve Genders 
-; CHECK: read accessor c = a@<t:UInt<3>[10]@<t:UInt>>[UInt("h3")@<t:UInt>]
-; CHECK: Finished Resolve Genders 
 
diff --git a/test/passes/infer-types/gcd.fir b/test/passes/infer-types/gcd.fir
index 68ec4174..938cb345 100644
--- a/test/passes/infer-types/gcd.fir
+++ b/test/passes/infer-types/gcd.fir
@@ -15,16 +15,13 @@ circuit top :
       input clk : Clock
       input reset : UInt<1>
       output z : UInt<16>
-      output v : UInt<1>
-      reg x : UInt,clk,reset
-      reg y : UInt,clk,reset
-; CHECK: reg x : UInt, clk@<t:Clock>, reset@<t:UInt>@<t:UInt>
-      onreset x <= UInt(0)
-      onreset y <= UInt(42)
+      reg x : UInt,clk,reset,UInt(0)
+      reg y : UInt,clk,reset,UInt(42)
+      ; CHECK: reg x : UInt, clk@<t:Clock>, reset@<t:UInt>, UInt("h0")@<t:UInt>@<t:UInt>
       when gt(x, y) :
       ;CHECK: when gt(x@<t:UInt>, y@<t:UInt>)@<t:UInt> :
          inst s of subtracter
-         ;CHECK: inst s of subtracter@<t:{flip x : UInt, flip y : UInt,  z : UInt}>
+         ;CHECK: inst s of subtracter : {flip x : UInt, flip y : UInt,  z : UInt}
          s.x <= x
          s.y <= y
          x <= s.z