diff options
| -rw-r--r-- | TODO | 10 | ||||
| -rw-r--r-- | src/main/stanza/ir-utils.stanza | 8 | ||||
| -rw-r--r-- | src/main/stanza/passes.stanza | 11 | ||||
| -rw-r--r-- | test/passes/infer-types/bundle.fir | 23 | ||||
| -rw-r--r-- | test/passes/infer-types/gcd.fir | 11 |
5 files changed, 34 insertions, 29 deletions
@@ -1,4 +1,12 @@ - +Add check passes +Fix all test cases +Add chirrtl support +Test with real RTL +Add optimization passes +Figure out naming +Convert to scala +Tech Report +ROM node Support ASIC backend diff --git a/src/main/stanza/ir-utils.stanza b/src/main/stanza/ir-utils.stanza index 7201b8ed..9c997f39 100644 --- a/src/main/stanza/ir-utils.stanza +++ b/src/main/stanza/ir-utils.stanza @@ -339,12 +339,12 @@ defmethod print (o:OutputStream, t:Type) : print(o, "Clock") (t:UIntType) : match(width(t)) : - (w:UnknownWidth) : print-all(o, ["UInt"]) - (w) : print-all(o, ["UInt<" width(t) ">"]) + (w:IntWidth) : print-all(o, ["UInt<" width(t) ">"]) + (w) : print-all(o, ["UInt"]) (t:SIntType) : match(width(t)) : - (w:UnknownWidth) : print-all(o, ["SInt"]) - (w) : print-all(o, ["SInt<" width(t) ">"]) + (w:IntWidth) : print-all(o, ["SInt<" width(t) ">"]) + (w) : print-all(o, ["SInt"]) (t:BundleType) : print(o, "{") print-all(o, join(fields(t), ", ")) diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza index 01ec034c..14e3e75d 100644 --- a/src/main/stanza/passes.stanza +++ b/src/main/stanza/passes.stanza @@ -298,7 +298,7 @@ defmethod print-debug (o:OutputStream, e:Expression|Stmt|Type|Port|Field|Module| match(t) : (t:UIntType) : UIntType(UnknownWidth()) (t:SIntType) : SIntType(UnknownWidth()) - (t) : t + (t) : map(wipe-width,t) if any-debug?(e) : print(o,"@") if PRINT-KINDS and hasKind(e) : print-all(o,["<k:" kind(e as ?) ">"]) @@ -727,9 +727,7 @@ defn infer-types (c:Circuit) -> Circuit : (e:DoPrim) : set-primop-type(e) (e:UIntValue|SIntValue) : e defn infer-types-s (s:Stmt) -> Stmt : - map{infer-types-e,_} $ map(infer-types-s,s) - defn build-types (s:Stmt) -> Stmt : - match(s) : + match(map(infer-types-e,s)) : (s:DefWire|DefPoison|DefRegister|DefNode) : val t = remove-unknowns(get-type(s)) types[name(s)] = t @@ -742,13 +740,12 @@ defn infer-types (c:Circuit) -> Circuit : (s:WDefInstance) : types[name(s)] = module-types[module(s)] WDefInstance(info(s),name(s),module(s),module-types[module(s)]) - (s) : map(build-types,s) + (s) : map(infer-types-s,s) for p in ports(m) do : types[name(p)] = type(p) match(m) : (m:InModule) : - val s* = build-types(body(m)) - InModule(info(m),name(m),ports(m),infer-types-s(s*)) + InModule(info(m),name(m),ports(m),infer-types-s(body(m))) (m:ExModule) : m ; MAIN diff --git a/test/passes/infer-types/bundle.fir b/test/passes/infer-types/bundle.fir index 400aecde..12cc58b1 100644 --- a/test/passes/infer-types/bundle.fir +++ b/test/passes/infer-types/bundle.fir @@ -1,14 +1,13 @@ ; RUN: firrtl -i %s -o %s.v -X verilog -p ct 2>&1 | tee %s.out | FileCheck %s -;CHECK: Infer Types circuit top : module top : wire z : { x : UInt, flip y: SInt} z.x <= UInt(1) z.y <= SInt(1) - node x = z.x ;CHECK: node x = z@<t:{ x : UInt, flip y : SInt}>.x@<t:UInt> - node y = z.y ;CHECK: node y = z@<t:{ x : UInt, flip y : SInt}>.y@<t:SInt> - wire a : UInt<3>[10] ;CHECK: wire a : UInt<3>[10]@<t:UInt>@<t:UInt<3>[10]@<t:UInt>> + node x = z.x + node y = z.y + wire a : UInt<3>[10] a[0] <= UInt(1) a[1] <= UInt(1) a[2] <= UInt(1) @@ -19,11 +18,15 @@ circuit top : a[7] <= UInt(1) a[8] <= UInt(1) a[9] <= UInt(1) - node b = a[2] ;CHECK: node b = a@<t:UInt<3>[10]@<t:UInt>>[2]@<t:UInt> - read accessor c = a[UInt(3)] ;CHECK: read accessor c = a@<t:UInt<3>[10]@<t:UInt>>[UInt("h3")@<t:UInt>] -; CHECK: Finished Infer Types + node b = a[2] + node c = a[UInt(3)] + +;CHECK: Infer Types +;CHECK: node x = z@<t:{ x : UInt, flip y : SInt}>.x@<t:UInt> +;CHECK: node y = z@<t:{ x : UInt, flip y : SInt}>.y@<t:SInt> +;CHECK: wire a : UInt<3>[10]@<t:UInt>@<t:UInt[10]@<t:UInt>> +;CHECK: node b = a@<t:UInt[10]@<t:UInt>>[2]@<t:UInt> +;CHECK: node c = a@<t:UInt[10]@<t:UInt>>[UInt("h3")@<t:UInt>] +;CHECK: Finished Infer Types -; CHECK: Resolve Genders -; CHECK: read accessor c = a@<t:UInt<3>[10]@<t:UInt>>[UInt("h3")@<t:UInt>] -; CHECK: Finished Resolve Genders diff --git a/test/passes/infer-types/gcd.fir b/test/passes/infer-types/gcd.fir index 68ec4174..938cb345 100644 --- a/test/passes/infer-types/gcd.fir +++ b/test/passes/infer-types/gcd.fir @@ -15,16 +15,13 @@ circuit top : input clk : Clock input reset : UInt<1> output z : UInt<16> - output v : UInt<1> - reg x : UInt,clk,reset - reg y : UInt,clk,reset -; CHECK: reg x : UInt, clk@<t:Clock>, reset@<t:UInt>@<t:UInt> - onreset x <= UInt(0) - onreset y <= UInt(42) + reg x : UInt,clk,reset,UInt(0) + reg y : UInt,clk,reset,UInt(42) + ; CHECK: reg x : UInt, clk@<t:Clock>, reset@<t:UInt>, UInt("h0")@<t:UInt>@<t:UInt> when gt(x, y) : ;CHECK: when gt(x@<t:UInt>, y@<t:UInt>)@<t:UInt> : inst s of subtracter - ;CHECK: inst s of subtracter@<t:{flip x : UInt, flip y : UInt, z : UInt}> + ;CHECK: inst s of subtracter : {flip x : UInt, flip y : UInt, z : UInt} s.x <= x s.y <= y x <= s.z |