WIP

1 files changed, 5 insertions, 4 deletions

diff --git a/test/passes/to-verilog/gcd.fir b/test/passes/to-verilog/gcd.fir
index 6d1bc819..c79cc92e 100644
--- a/test/passes/to-verilog/gcd.fir
+++ b/test/passes/to-verilog/gcd.fir
@@ -14,10 +14,8 @@ circuit top :
       input b : UInt<16>
       input e : UInt<1>
       output z : UInt<16>
-      reg x : UInt,clk,reset
-      reg y : UInt,clk,reset
-      onreset x := UInt(0)
-      onreset y := UInt(42)
+      reg x : UInt,clk,reset,UInt(0)
+      reg y : UInt,clk,reset,UInt(42)
       when gt(x, y) :
          inst s of subtracter
          s.x := x
@@ -45,4 +43,7 @@ circuit top :
       i.b := b
       i.e := UInt(1)
       z := i.z
+
+
+
 ;CHECK: Done!