diff options
| author | azidar | 2015-09-30 10:23:03 -0700 |
|---|---|---|
| committer | azidar | 2015-09-30 10:23:03 -0700 |
| commit | 1f004616b045d3d8df18a87c252333361739c66d (patch) | |
| tree | 52e554edd692cfbe2de8b4ccd4c47b4e1db9a84e /test | |
| parent | 168f001d672259f308301afa1165c15ab868171c (diff) | |
Fixed test so it passes, as it should
Diffstat (limited to 'test')
| -rw-r--r-- | test/passes/inline-indexers/init-vecs.fir | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/test/passes/inline-indexers/init-vecs.fir b/test/passes/inline-indexers/init-vecs.fir index 7d64a117..149215c3 100644 --- a/test/passes/inline-indexers/init-vecs.fir +++ b/test/passes/inline-indexers/init-vecs.fir @@ -1,7 +1,6 @@ ; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; XFAIL: * -; CHECK: Expand Indexed Connects +; CHECK: Inline Indexers circuit top : module top : wire outs : UInt<32>[2][1] |