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authorazidar2015-08-25 14:13:00 -0700
committerazidar2015-08-25 14:13:13 -0700
commiteb1ab67b6cc3fd4a549da563bf643bd519d7562e (patch)
treea21f0ca828398a33a68f38209429cc6beed86edc /test
parent6cd96b6315c32bbf6c4ace28197ff1d4be86a129 (diff)
Added width check pass with tests. #22.
Diffstat (limited to 'test')
-rw-r--r--test/errors/high-form/NegWidth.fir2
-rw-r--r--test/errors/width/NegWidth.fir9
-rw-r--r--test/errors/width/SmallWidth.fir13
-rw-r--r--test/errors/width/UninferredWidth.fir12
4 files changed, 35 insertions, 1 deletions
diff --git a/test/errors/high-form/NegWidth.fir b/test/errors/high-form/NegWidth.fir
index 9b055228..1eb54a34 100644
--- a/test/errors/high-form/NegWidth.fir
+++ b/test/errors/high-form/NegWidth.fir
@@ -1,5 +1,5 @@
; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
-; CHECK: Width cannot be negative.
+; CHECK: Width cannot be negative or zero.
circuit Top :
module Top :
diff --git a/test/errors/width/NegWidth.fir b/test/errors/width/NegWidth.fir
new file mode 100644
index 00000000..5d5bbf43
--- /dev/null
+++ b/test/errors/width/NegWidth.fir
@@ -0,0 +1,9 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p ciwT 2>&1 | tee %s.out | FileCheck %s
+; CHECK: Width cannot be negative or zero.
+
+circuit Top :
+ module Top :
+ output y : UInt
+
+ wire x : UInt<2>
+ y := shr(x,4)
diff --git a/test/errors/width/SmallWidth.fir b/test/errors/width/SmallWidth.fir
new file mode 100644
index 00000000..9e26699e
--- /dev/null
+++ b/test/errors/width/SmallWidth.fir
@@ -0,0 +1,13 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p ciwT 2>&1 | tee %s.out | FileCheck %s
+; CHECK: Width too small for constant "h121".
+; CHECK: Width too small for constant "h13333".
+
+circuit Top :
+ module Top :
+ output z : UInt
+
+ z := add(UInt<4>("h121"),UInt<3>("h13333"))
+
+
+
+
diff --git a/test/errors/width/UninferredWidth.fir b/test/errors/width/UninferredWidth.fir
new file mode 100644
index 00000000..d4cff841
--- /dev/null
+++ b/test/errors/width/UninferredWidth.fir
@@ -0,0 +1,12 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p ciwTd 2>&1 | tee %s.out | FileCheck %s
+; CHECK: Uninferred width.
+
+circuit Top :
+ module Top :
+ input z : UInt
+
+
+
+
+
+