| Age | Commit message (Expand) | Author |
|---|
| 2016-01-28 | Fixed bug where subaccess indexes were being classified as female, | azidar |
| 2016-01-28 | Changed rmode to wmode | azidar |
| 2016-01-28 | Use IsInvalid instead of Poisons in chirrtl -> firrtl transform | azidar |
| 2016-01-28 | Added tests for previous commit | azidar |
| 2016-01-28 | Added addw to working ir as an optimized verilog emission | azidar |
| 2016-01-28 | Fixed bug and updated test for changing mod to rem | azidar |
| 2016-01-28 | Updated all tests to pass | azidar |
| 2016-01-28 | Changed register syntax for optional reset and init values | azidar |
| 2016-01-27 | Reworked readwriter types | azidar |
| 2016-01-27 | Fixed additional tests and inferring rdwr ports in chirrtl | jackkoenig |
| 2016-01-25 | Fixed bug where poisons were not being declared | azidar |
| 2016-01-25 | Added verilog rename pass | azidar |
| 2016-01-25 | Added isinvalid and validif | azidar |
| 2016-01-25 | Fixed support for muxes and nodes with passive aggregate types | azidar |
| 2016-01-25 | Fixed one more test | azidar |
| 2016-01-25 | Changed tests to pass with change to postfix of generated name | azidar |
| 2016-01-24 | Fixed tests that broke from changing verilog backend and removing mask from w... | azidar |
| 2016-01-24 | Added muxing on passive aggregate types | azidar |
| 2016-01-24 | Added DefMemory to CInfer Types | azidar |
| 2016-01-23 | Fixed bug where the write mask wasn't being generated correctly | azidar |
| 2016-01-23 | Added inference to mports | azidar |
| 2016-01-23 | Added prefix checker, now compliant with firrtl spec | azidar |
| 2016-01-23 | Changed chirrtl to not require known mask values | azidar |
| 2016-01-17 | Fixed error where memory of size 1 would create an index of size 0. This can ... | azidar |
| 2016-01-17 | Added check for uint on access index type | azidar |
| 2016-01-17 | BIT-AND, BIT-OR, and BIT-XOR now can accept SInts. Fixed tests | azidar |
| 2016-01-16 | Added a bunch of tests and added firrtl-stanza and firrtl-scala to .gitignore | azidar |
| 2016-01-16 | Fixed all tests so they either pass are marked as expected failures | azidar |
| 2016-01-16 | Updated passes so they test new-mem | azidar |
| 2016-01-16 | Fixed a test | azidar |
| 2016-01-16 | Fixed Vector performance tests | azidar |
| 2016-01-16 | Finished first cut at new firrtl - time for testing! Chirrtl requires masks t... | azidar |
| 2016-01-16 | Fixed a bunch of tests, and minor bugs | azidar |
| 2016-01-16 | Added src and test files | azidar |
| 2016-01-16 | WIP. Fixed a bunch of tests. Starting on implementing chirrtl, but hit roadbl... | azidar |
| 2016-01-16 | WIP getting through tests | azidar |
| 2016-01-16 | Finished supporting nested accesses. Required some nuianced thinking. Pass al... | azidar |
| 2016-01-16 | WIP, hit semantic bug in WSubAccess | azidar |
| 2016-01-16 | New memory works with verilog. Slowly changing tests and fixing bugs. | azidar |
| 2016-01-16 | WIP. Compiles and almost done with verilog backend. Need to think about emitt... | azidar |
| 2016-01-16 | WIP | azidar |
| 2016-01-16 | WIP need to correctly output readwrite ports | azidar |
| 2016-01-16 | Added performance tests | azidar |
| 2016-01-16 | Fixed inline-indexers bug where genders weren't properly calculated in | azidar |
| 2016-01-16 | Finished adding clocks to Stop and Print | azidar |
| 2015-11-02 | Deleted extranous passes.stanza comments, updated standard passes. Added supp... | jackkoenig |
| 2015-10-19 | Merge pull request #47 from jackkoenig/master | Adam Izraelevitz |
| 2015-10-14 | Modified getType to return Type rather than Option[Type] which makes more sen... | Jack |
| 2015-10-14 | Moved Logger to new private object DebugUtils, changed UInt/SInt value printi... | Jack |
| 2015-10-12 | Added support for no width to mean unknown, and print nothing instead of <?> ... | Jack |
