| Age | Commit message (Expand) | Author |
|---|
| 2016-01-28 | Fixed bug where subaccess indexes were being classified as female, | azidar |
| 2016-01-28 | Changed rmode to wmode | azidar |
| 2016-01-28 | Use IsInvalid instead of Poisons in chirrtl -> firrtl transform | azidar |
| 2016-01-28 | Added tests for previous commit | azidar |
| 2016-01-28 | Fixed bug where you cannot extract from a single bit wire in verilog. #55. | azidar |
| 2016-01-28 | Fixed bug where needed to cast bit-operation inputs prior to verilog emission | azidar |
| 2016-01-28 | Added addw to working ir as an optimized verilog emission | azidar |
| 2016-01-28 | Add map of symbol->symbol for wdefinstance | azidar |
| 2016-01-28 | Fixed matching on types for and, or, and xor | azidar |
| 2016-01-28 | Fixed bug and updated test for changing mod to rem | azidar |
| 2016-01-28 | Changed mod to rem | azidar |
| 2016-01-28 | Updated todo list | azidar |
| 2016-01-28 | Updated all tests to pass | azidar |
| 2016-01-28 | Updated with new primops. Removed addw,subw,quo,rem,bit. Added head,tail,asCl... | azidar |
| 2016-01-28 | Fixed readwriter syntax, and all printed mstats to use => instead of a colon | azidar |
| 2016-01-28 | Changed register syntax for optional reset and init values | azidar |
| 2016-01-27 | Reworked readwriter types | azidar |
| 2016-01-27 | Fixed additional tests and inferring rdwr ports in chirrtl | jackkoenig |
| 2016-01-27 | Merge branch 'scala-new-mem' | jackkoenig |
| 2016-01-25 | Fixed bug where poisons were not being declared | azidar |
| 2016-01-25 | Added verilog rename pass | azidar |
| 2016-01-25 | Added isinvalid and validif | azidar |
| 2016-01-25 | Removed println in expand when | azidar |
| 2016-01-25 | Fixed width inference bug for muxes | azidar |
| 2016-01-25 | Removed random println | azidar |
| 2016-01-25 | Fixed support for muxes and nodes with passive aggregate types | azidar |
| 2016-01-25 | Fixed one more test | azidar |
| 2016-01-25 | Changed tests to pass with change to postfix of generated name | azidar |
| 2016-01-25 | Changed first generated name to use _0 postfix | azidar |
| 2016-01-24 | Fixed tests that broke from changing verilog backend and removing mask from w... | azidar |
| 2016-01-24 | Made CInfer robust to high firrtl errors | azidar |
| 2016-01-24 | Added muxing on passive aggregate types | azidar |
| 2016-01-24 | Merge branch 'new-mem' of github.com:ucb-bar/firrtl into new-mem | azidar |
| 2016-01-24 | Removed hashing as it made refchip slower to compile | azidar |
| 2016-01-24 | Added DefMemory to CInfer Types | azidar |
| 2016-01-23 | Fix Verilog syntax errors for print/stop | Andrew Waterman |
| 2016-01-23 | Update rocket regression | Andrew Waterman |
| 2016-01-23 | Removed buggy optimization of dshr and dshl | azidar |
| 2016-01-23 | Moved inst declarations after other declarations | azidar |
| 2016-01-23 | Fixed commas for instances in verilog | azidar |
| 2016-01-23 | Added more semicolons | azidar |
| 2016-01-23 | Added semicolon after assigns in verilog | azidar |
| 2016-01-23 | off by one error when emitting ports in verilog | azidar |
| 2016-01-23 | Fixed combinational read verilog backend | azidar |
| 2016-01-23 | Removed more prints ;) | azidar |
| 2016-01-23 | Removed print statements | azidar |
| 2016-01-23 | Fixed bug where the write mask wasn't being generated correctly | azidar |
| 2016-01-23 | Removed debugging printlns | azidar |
| 2016-01-23 | Added inference to mports | azidar |
| 2016-01-23 | Added prefix checker, now compliant with firrtl spec | azidar |
