Fixed bug where the write mask wasn't being generated correctly

4 files changed, 33 insertions, 10 deletions

diff --git a/src/main/stanza/chirrtl.stanza b/src/main/stanza/chirrtl.stanza
index ed4b2550..4854a61d 100644
--- a/src/main/stanza/chirrtl.stanza
+++ b/src/main/stanza/chirrtl.stanza
@@ -265,7 +265,7 @@ defn remove-chirrtl (c:Circuit) :
                   for r in vec do :
                      add(stmts,Connect(info(s),SubField(SubField(Ref(name(s),ut),name(r),ut),en,taddr),zero))
                defn set-write (vec:List<MPort>,data:Symbol,mask:Symbol) -> False :
-                  val tmask = type(create-mask(`blah,type(s)))
+                  val tmask = create-mask(type(s))
                   for r in vec do :
                      add(stmts,Connect(info(s),SubField(SubField(Ref(name(s),ut),name(r),ut),data,tdata),Ref(ndata,tdata)))
                      for x in create-exps(SubField(SubField(Ref(name(s),ut),name(r),ut),mask,tmask)) do :
@@ -338,8 +338,11 @@ defn remove-chirrtl (c:Circuit) :
                (e:Ref) :
                   if key?(repl,name(e)) : 
                      val vt = repl[name(e)]
-                     val f = create-mask(`blah,mport-types[name(e)])
-                     SubField(exp(vt),mask(vt),type(f))
+                     println(exp(vt))
+                     println(type(exp(vt)))
+                     val t = create-mask(type(e))
+                     println(t)
+                     SubField(exp(vt),mask(vt),t)
                   else : e
                (e) : e
          match(s) :
diff --git a/src/main/stanza/ir-utils.stanza b/src/main/stanza/ir-utils.stanza
index 7af75b57..fa4b296f 100644
--- a/src/main/stanza/ir-utils.stanza
+++ b/src/main/stanza/ir-utils.stanza
@@ -194,7 +194,7 @@ public defn get-valid-points (t1:Type,t2:Type,flip1:Flip,flip2:Flip) -> List<[In
                      flip2 * flip(f2)) 
                   for x in ls do :
                      add(points,[x[0] + ilen, x[1] + jlen])
-               println(points)
+               ;println(points)
                jlen = jlen + get-size(type(fields(t2)[j]))
             ilen = ilen + get-size(type(fields(t1)[i]))
             jlen = 0
@@ -212,12 +212,12 @@ public defn get-valid-points (t1:Type,t2:Type,flip1:Flip,flip2:Flip) -> List<[In
          to-list(points)
 
 ;============= Useful functions ==============
-public defn create-mask (n:Symbol,dt:Type) -> Field :
-   Field{n,DEFAULT,_} $ match(dt) :
-      (t:VectorType) : VectorType(BoolType(),size(t))
+public defn create-mask (dt:Type) -> Type :
+   match(dt) :
+      (t:VectorType) : VectorType(create-mask(type(t)),size(t))
       (t:BundleType) : 
          val fields* = for f in fields(t) map :
-            Field(name(f),flip(f),BoolType())
+            Field(name(f),flip(f),create-mask(type(f)))
          BundleType(fields*)
       (t:UIntType|SIntType) : BoolType()
 
diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index ee650bde..005cc88d 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -130,8 +130,8 @@ defn get-type (s:Stmt) -> Type :
          val rev-data = Field(`data,REVERSE,data-type(s))
          val rdata = Field(`rdata,REVERSE,data-type(s))
          val wdata = Field(`wdata,DEFAULT,data-type(s))
-         val mask = create-mask(`mask,data-type(s))
-         val wmask = create-mask(`wmask,data-type(s))
+         val mask = Field(`mask,DEFAULT,create-mask(data-type(s)))
+         val wmask = Field(`wmask,DEFAULT,create-mask(data-type(s)))
          val ren = Field(`ren,DEFAULT,UIntType(IntWidth(1)))
          val wen = Field(`wen,DEFAULT,UIntType(IntWidth(1)))
          val raddr = Field(`raddr,DEFAULT,UIntType(IntWidth(ceil-log2(depth))))
diff --git a/test/chirrtl/mask-bug.fir b/test/chirrtl/mask-bug.fir
new file mode 100644
index 00000000..b580c075
--- /dev/null
+++ b/test/chirrtl/mask-bug.fir
@@ -0,0 +1,20 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
+; CHECK: Done!
+circuit top :
+   module top :
+      input clk : Clock
+      wire p : UInt
+      wire q : UInt
+      cmem m : {a:UInt<4>,b:{c: UInt<4>,d:UInt<4>}}[10]
+      p <= UInt(1)
+      q <= UInt(1)
+      wire x : {a:UInt<4>,b:{c: UInt<4>,d:UInt<4>}}
+      x.a <= UInt(1)
+      x.b.c <= UInt(1)
+      x.b.d <= UInt(1)
+      when p :
+         write mport a = m[UInt(3)],clk
+         when q :
+            a <- x
+
+