Changed mod to rem

9 files changed, 10 insertions, 9 deletions

diff --git a/spec/spec.tex b/spec/spec.tex
index dc15e1b8..b8b1fd55 100644
--- a/spec/spec.tex
+++ b/spec/spec.tex
@@ -1808,6 +1808,7 @@ The concrete syntax of FIRRTL is defined in section \ref{syntax_tree}. Productio
 %- Proposed changes to spec
 %   - switch back to precise dynamic left shift
 %   - have a wmode instead of rmode for readwrite ports
+%   - rename mod to rem
 
 \end{document}
 
diff --git a/src/main/stanza/errors.stanza b/src/main/stanza/errors.stanza
index 80ae9c08..f9504bea 100644
--- a/src/main/stanza/errors.stanza
+++ b/src/main/stanza/errors.stanza
@@ -191,7 +191,7 @@ public defn check-high-form (c:Circuit) -> Circuit :
          SUB-OP             : correct-num(2,0)
          MUL-OP             : correct-num(2,0)
          DIV-OP             : correct-num(2,0)
-         MOD-OP             : correct-num(2,0)
+         REM-OP             : correct-num(2,0)
          LESS-OP            : correct-num(2,0)
          LESS-EQ-OP         : correct-num(2,0)
          GREATER-OP         : correct-num(2,0)
diff --git a/src/main/stanza/firrtl-ir.stanza b/src/main/stanza/firrtl-ir.stanza
index 998c5aa7..e6c242bf 100644
--- a/src/main/stanza/firrtl-ir.stanza
+++ b/src/main/stanza/firrtl-ir.stanza
@@ -32,7 +32,7 @@ public val ADD-OP = new PrimOp
 public val SUB-OP = new PrimOp
 public val MUL-OP = new PrimOp
 public val DIV-OP = new PrimOp
-public val MOD-OP = new PrimOp
+public val REM-OP = new PrimOp
 public val LESS-OP = new PrimOp
 public val LESS-EQ-OP = new PrimOp
 public val GREATER-OP = new PrimOp
diff --git a/src/main/stanza/flo.stanza b/src/main/stanza/flo.stanza
index 3b1dbf76..015da39a 100644
--- a/src/main/stanza/flo.stanza
+++ b/src/main/stanza/flo.stanza
@@ -31,7 +31,7 @@ defn flo-op-name (op:PrimOp, args:List<Expression>) -> String :
       SUB-WRAP-OP :        "sub"
       MUL-OP :             "mul" ;; todo: signed version
       DIV-OP :             "div" ;; todo: signed version
-      MOD-OP :             "mod" ;; todo: signed version
+      REM-OP :             "mod" ;; todo: signed version
       QUO-OP :             "div" ;; todo: signed version
       REM-OP :             "mod" ;; todo: signed version
       LESS-OP :            "lt"  ;; todo: signed version
diff --git a/src/main/stanza/ir-parser.stanza b/src/main/stanza/ir-parser.stanza
index 1685996c..139216c3 100644
--- a/src/main/stanza/ir-parser.stanza
+++ b/src/main/stanza/ir-parser.stanza
@@ -63,7 +63,7 @@ OPERATORS[`add] = ADD-OP
 OPERATORS[`sub] = SUB-OP
 OPERATORS[`mul] = MUL-OP
 OPERATORS[`div] = DIV-OP
-OPERATORS[`mod] = MOD-OP
+OPERATORS[`rem] = REM-OP
 OPERATORS[`lt] = LESS-OP
 OPERATORS[`leq] = LESS-EQ-OP
 OPERATORS[`gt] = GREATER-OP
diff --git a/src/main/stanza/ir-utils.stanza b/src/main/stanza/ir-utils.stanza
index 1c960974..9fd8b39a 100644
--- a/src/main/stanza/ir-utils.stanza
+++ b/src/main/stanza/ir-utils.stanza
@@ -360,7 +360,7 @@ defmethod print (o:OutputStream, op:PrimOp) :
       SUB-OP : "sub"
       MUL-OP : "mul"
       DIV-OP : "div"
-      MOD-OP : "mod"
+      REM-OP : "rem"
       LESS-OP : "lt"
       LESS-EQ-OP : "leq"
       GREATER-OP : "gt"
diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index 7475e793..3f18ef21 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -2486,7 +2486,7 @@ defn op-stream (doprim:DoPrim) -> Streamable :
       SUB-OP : [cast-if(a0()) " - " cast-if(a1())]
       MUL-OP : [cast-if(a0()) " * " cast-if(a1()) ]
       DIV-OP : [cast-if(a0()) " / " cast-if(a1()) ]
-      MOD-OP : [cast-if(a0()) " % " cast-if(a1()) ]
+      REM-OP : [cast-if(a0()) " % " cast-if(a1()) ]
       LESS-OP : [cast-if(a0()) " < " cast-if(a1())]
       LESS-EQ-OP : [cast-if(a0()) " <= " cast-if(a1())]
       GREATER-OP : [cast-if(a0()) " > " cast-if(a1())]
diff --git a/src/main/stanza/primop.stanza b/src/main/stanza/primop.stanza
index b6e81be1..7aba40c7 100644
--- a/src/main/stanza/primop.stanza
+++ b/src/main/stanza/primop.stanza
@@ -53,7 +53,7 @@ public defn set-primop-type (e:DoPrim) -> DoPrim :
             (t1:SIntType, t2:UIntType) : SIntType(w1())
             (t1:SIntType, t2:SIntType) : SIntType(PLUS(w1(),ONE))
             (t1, t2) : UnknownType()
-      MOD-OP : DoPrim{o,a,c,_} $
+      REM-OP : DoPrim{o,a,c,_} $
          match(t1(),t2()) :
             (t1:UIntType, t2:UIntType) : UIntType(MIN(w1(),w2()))
             (t1:UIntType, t2:SIntType) : UIntType(MIN(w1(),w2()))
@@ -202,7 +202,7 @@ public defn set-primop-type (e:DoPrim) -> DoPrim :
 ;            (t0:UIntType,t1:SIntType) : PlusWidth(width!(args(e)[0]),IntWidth(1))
 ;            (t0:SIntType,t1:SIntType) : PlusWidth(width!(args(e)[0]),IntWidth(1))
 ;            (t0,t1) : width!(args(e)[0])
-;      MOD-OP : 
+;      REM-OP : 
 ;         match(type(args(e)[0]),type(args(e)[1])) :
 ;            (t0:SIntType,t1:UIntType) : PlusWidth(width!(args(e)[1]),IntWidth(1))
 ;            (t0,t1) : width!(args(e)[1])
diff --git a/src/main/stanza/verilog.stanza b/src/main/stanza/verilog.stanza
index 21931dd9..9040a8bd 100644
--- a/src/main/stanza/verilog.stanza
+++ b/src/main/stanza/verilog.stanza
@@ -96,7 +96,7 @@ defn emit (e:Expression) -> String :
             SUB-OP : [emit-signed-if-any(args(e)[0],args(e)) " - " emit-signed-if-any(args(e)[1],args(e))]
             MUL-OP : [emit-signed-if-any(args(e)[0],args(e)) " * " emit-signed-if-any(args(e)[1],args(e)) ]
             DIV-OP : [emit-signed-if-any(args(e)[0],args(e)) " / " emit-signed-if-any(args(e)[1],args(e)) ]
-            MOD-OP : [emit-signed-if-any(args(e)[0],args(e)) " % " emit-signed-if-any(args(e)[1],args(e)) ]
+            REM-OP : [emit-signed-if-any(args(e)[0],args(e)) " % " emit-signed-if-any(args(e)[1],args(e)) ]
             QUO-OP : [emit-signed-if-any(args(e)[0],args(e)) " / " emit-signed-if-any(args(e)[1],args(e)) ]
             REM-OP : [emit-signed-if-any(args(e)[0],args(e)) " % " emit-signed-if-any(args(e)[1],args(e)) ]
             ADD-WRAP-OP : [emit-signed-if-any(args(e)[0],args(e)), " + " emit-signed-if-any(args(e)[1],args(e))]