Changed register syntax for optional reset and init values

4 files changed, 22 insertions, 5 deletions

diff --git a/spec/spec.tex b/spec/spec.tex
index 12f2c91e..7c528467 100644
--- a/spec/spec.tex
+++ b/spec/spec.tex
@@ -1792,7 +1792,6 @@ The concrete syntax of FIRRTL is defined in section \ref{syntax_tree}. Productio
 %\section{TODO}
 %
 %- FIRRTL implementation
-%   - Rework readwrite port types       ; limits optimizations but probably ok
 %   - Make register reset/init optional ; good
 %   - removed addw, added head and tail ; great!
 %   - Add UBits                         ; andrew doesn't care, favors overloading UInt
@@ -1800,6 +1799,7 @@ The concrete syntax of FIRRTL is defined in section \ref{syntax_tree}. Productio
 %   - Add partial connect algorithm     ; 
 %   - Add oriented types to type checker
 %   - Add memory read-under-write flag  ; probably overengineering, but could be a wash
+%   - *FINISHED* Rework readwrite port types       ; limits optimizations but probably ok
 %   - *FINISHED* Add Mux expression                ; that's lovely, need glitch-free mux for clock types
 %   - *FINISHED* add rename pass for verilog
 %   - *FINISHED* Add is invalid                    ; good
diff --git a/src/main/stanza/ir-parser.stanza b/src/main/stanza/ir-parser.stanza
index e1083d50..5261d587 100644
--- a/src/main/stanza/ir-parser.stanza
+++ b/src/main/stanza/ir-parser.stanza
@@ -258,9 +258,8 @@ defsyntax firrtl :
    defrule statements :
       stmt = (skip) : Empty()
       stmt = (wire ?name:#id! #:! ?t:#type!) : DefWire(first-info(form),name, t)
-      stmt = (reg ?name:#id! #:! ?t:#type! ?clk:#exp! ?reset:#exp! ?init:#exp!) : DefRegister(first-info(form),name, t,clk,reset,init)
-      ;stmt = (mem ?name:#id! #:! ?data-type:#type! ?depth:#int ?writers:#id! ... ?wl:#int ?readers:#id! ... ?rl:#int ?readwriters:#id! ...) : 
-      ;   DefMemory(first-info(form),name,data-type,depth,wl,rl,readers,writers,readwriters)
+      stmt = (reg ?name:#id! #:! ?t:#type! ?clk:#exp! with #:! ( reset => (?reset:#exp! ?init:#exp!))) : DefRegister(first-info(form),name,t,clk,reset,init)
+      stmt = (reg ?name:#id! #:! ?t:#type! ?clk:#exp!) : DefRegister(first-info(form),name,t,clk,zero,Ref(name,UnknownType()))
       stmt = (cmem ?name:#id! #:! ?t:#vectype! ) : CDefMemory(first-info(form),name,type(t),size(t),false)
       stmt = (smem ?name:#id! #:! ?t:#vectype! ) : CDefMemory(first-info(form),name,type(t),size(t),true)
 
diff --git a/src/main/stanza/ir-utils.stanza b/src/main/stanza/ir-utils.stanza
index cf9e03e2..66e095fc 100644
--- a/src/main/stanza/ir-utils.stanza
+++ b/src/main/stanza/ir-utils.stanza
@@ -420,7 +420,8 @@ defmethod print (o:OutputStream, c:Stmt) :
       (c:DefWire) :
          print-all(o,["wire " name(c) " : " type(c)])
       (c:DefRegister) : 
-         print-all(o,["reg " name(c) " : " type(c) ", " clock(c) ", " reset(c) ", " init(c)])
+         print-all(o,["reg " name(c) " : " type(c) ", " clock(c) " with :"])
+         print-all(io,["\nreset => (" reset(c) ", " init(c) ")"])
       (c:DefMemory) :
          print-all(o,["mem " name(c) " : "])
          print-debug(o,c)
diff --git a/test/features/OptionalRegisterReset.fir b/test/features/OptionalRegisterReset.fir
new file mode 100644
index 00000000..54a90b67
--- /dev/null
+++ b/test/features/OptionalRegisterReset.fir
@@ -0,0 +1,17 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
+circuit Top : 
+  module Top : 
+    input clk : Clock
+    input reset : UInt<1>
+    input a : UInt<32>
+    input p : UInt<1>
+    output b : UInt<32>
+    reg r1:UInt<32> clk with : 
+      reset => (reset, a)
+    when p :
+      b <= r1
+    else :
+      b <= r1
+
+
+;CHECK: Done!