Fixed bug where poisons were not being declared

2 files changed, 19 insertions, 17 deletions

diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index 3fba76de..cf6db44d 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -2653,7 +2653,7 @@ defn emit-verilog (m:InModule) -> Module :
             declare(`reg,name(wref),type(exp(s)))
             initialize(wref)
          (s:DefPoison) :
-            val n = firrtl-gensym(`GEN,namehash)
+            val n = name(s)
             val e = wref(n,type(s))
             declare(`reg,n,type(e))
             initialize(e)
diff --git a/test/passes/jacktest/Tbl.fir b/test/passes/jacktest/Tbl.fir
index f760af68..5feb71bb 100644
--- a/test/passes/jacktest/Tbl.fir
+++ b/test/passes/jacktest/Tbl.fir
@@ -1,19 +1,21 @@
 ; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
 ;CHECK: Done!
-circuit Tbl : 
-  module Tbl : 
-    input i : UInt<16>
-    input d : UInt<16>
+
+circuit Tbl :
+  module Tbl :
     input clk : Clock
-    output o : UInt<16>
-    input we : UInt<1>
-    
-    cmem m : UInt<10>[256]
-    o <= UInt<1>(0)
-    when we : 
-      write mport T_13 = m[i],clk
-      node T_14 = bits(d, 9, 0)
-      T_13 <= T_14
-    else : 
-      read mport T_15 = m[i],clk
-      o <= T_15
+    input reset : UInt<1>
+    output io : {flip wi : UInt<3>, flip ri : UInt<3>, flip we : UInt<1>, flip d : UInt<3>, o : UInt<3>}
+
+    io.o <= UInt<1>("h00")
+    cmem m : UInt<3>[8]
+    infer mport T_12 = m[io.ri], clk
+    io.o <= T_12
+    when io.we :
+      infer mport T_13 = m[io.wi], clk
+      T_13 <= io.d
+      node T_14 = eq(io.ri, io.wi)
+      when T_14 :
+        io.o <= io.d
+        skip
+      skip