| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2016-09-25 | Change file name ReplacesSubAccesses ReplaceAccess | chick | |
| 2016-09-25 | convert all occurencess of BigInt == Int to BigInt == BigInt | chick | |
| 2016-09-25 | Fix Anonymous function convertible to a method value | chick | |
| if methods has parens, then referencing without parens is a method value, you don't need following underscore | |||
| 2016-09-25 | Minor fixes, typo in word | chick | |
| missing declarations in scala doc | |||
| 2016-09-25 | Use empty-parens as appropriate for f: => Unit calls | chick | |
| 2016-09-23 | use .count instead of filter and size | chick | |
| 2016-09-23 | Use parens on Unit methods | chick | |
| 2016-09-23 | use .isEmpty, .nonEmpty, isDefined | chick | |
| 2016-09-23 | use .indices | chick | |
| 2016-09-23 | use .head instead of (0) | chick | |
| 2016-09-22 | Fixed width inference for add, sub (#312) | Adam Izraelevitz | |
| Fixes #308 Fixes #193 | |||
| 2016-09-21 | Fix clock connections in InferReadWrite (#310) | Donggyu | |
| 2016-09-21 | swap functions in MemPortUtils and MemTransformUtils properly for further ↵ | Donggyu Kim | |
| refactoring | |||
| 2016-09-21 | refactor AnnotateValidMemConfigs | Donggyu Kim | |
| 2016-09-21 | refactor ReplaceMemMacros | Donggyu Kim | |
| 2016-09-21 | refactor UpdateDuplicateMemMacros | Donggyu Kim | |
| 2016-09-21 | clean up ReplSeqMem | Donggyu Kim | |
| 2016-09-21 | refactor AnnotateMemMacros | Donggyu Kim | |
| 2016-09-21 | refactor InferReadWrite | Donggyu Kim | |
| 2016-09-21 | generalize Analysis.getConnects for code resuse | Donggyu Kim | |
| 2016-09-16 | fill empty module body with "begin end" (#305) | Yunsup Lee | |
| * fill empty module body with "begin end" apparently vivado treats an empty module as a black box and triggers an error * Changed empty module to use always @(*) begin end | |||
| 2016-09-15 | Fix non-determinism bug in ExpandWhens (#303) | Jack Koenig | |
| Despite the fact that LinkedHashMaps preserve insertion order in traversal, it appears that .keys and .keySet return Sets that do not provide the same guarantee | |||
| 2016-09-14 | fix spaces in WIR.scala | Donggyu Kim | |
| 2016-09-14 | style fixes for Compiler.scala, LoweringCompiler.scala | Donggyu Kim | |
| 2016-09-14 | Fix for more general case of getConnectOrigin with reg feedback (#301) | Angie Wang | |
| 2016-09-14 | Added Rob.fir for regression testing (#258) | Donggyu | |
| 2016-09-14 | fix enable signal inferecne for smems' read ports (#289) | Donggyu | |
| 2016-09-14 | Fixed infinite loop for finding connect origin in ReplSeqMem (#300) | Angie Wang | |
| * Addressed the fact that a node can be connected to itself (updating reg) | |||
| 2016-09-13 | Fix a lurking width-inference bug; improve adjacent style (#298) | Andrew Waterman | |
| ceil(log(x) / log(2)) does not, in general, round to ceil(log2(x)). I noticed this because of #297. | |||
| 2016-09-13 | use BoolType for UIntType(IntWidth(1)) | Donggyu Kim | |
| 2016-09-13 | remove VIndent | Donggyu Kim | |
| 2016-09-13 | use case object for WVoid, WInvalid | Donggyu Kim | |
| 2016-09-13 | cache IntWidths to avoid redudant object creations | Donggyu Kim | |
| 2016-09-13 | use case object for Kind | Donggyu Kim | |
| 2016-09-13 | clean up PadWidth | Donggyu Kim | |
| 2016-09-13 | clean up LowerTypes | Donggyu Kim | |
| no vars for mname, info | |||
| 2016-09-13 | clean up Passes.scala | Donggyu Kim | |
| 2016-09-13 | type aliases | Donggyu Kim | |
| 2016-09-13 | remove Utils.{width_BANG, long_BANG} | Donggyu Kim | |
| 2016-09-13 | remove Utils.get_type | Donggyu Kim | |
| 2016-09-13 | use MemPortUtils.memType for DefMemory | Donggyu Kim | |
| 2016-09-13 | remove Utils.{mapr, get_name} and fix spaces | Donggyu Kim | |
| 2016-09-13 | MemPortUtils: return correct memory types | Donggyu Kim | |
| 2016-09-13 | clean up MemUtils | Donggyu Kim | |
| 2016-09-12 | Add LegalizeSpec for testing Verilog Legalization pass | Jack | |
| 2016-09-12 | Add legalization of pad operation on literals. | Jack | |
| Performing a pad on SInt literals results in linting warnings in Verilator. This commit replaces pad operations on literal values with a literal of the correct width. | |||
| 2016-09-12 | Cast bit select of SInt in PadWidths to SInt | Jack | |
| Fixes #172 | |||
| 2016-09-12 | Legalize bit select. Run Legalize after PadWidths. | Jack | |
| Bit selecting a literal resulted in invalid Verilog. Legalize now deals with this by replacing any bits select of UInt or SInt literals with a new literal composed of the selected bits. Legalize also is now run after PadWidths because that pass introduces this issue. Fixes #170 | |||
| 2016-09-12 | Change Legalize Connect to respect SInt | Jack | |
| Legalize will wrap the rhs of a connect statement with a bit select primop if the lhs is of smaller width than the rhs. This bit select is now wrapped in a asSInt cast if the original rhs was an SInt so that is has the correct type. Fixes #173 | |||
| 2016-09-12 | Change Legalize Shift Right to respect SInt | jackkoenig | |
| Fix bug where Legalize was generating a bit select for SInts without then casting to SInt Fixes #169 | |||
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index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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