Add LegalizeSpec for testing Verilog Legalization pass

2 files changed, 79 insertions, 0 deletions

diff --git a/src/test/resources/passes/Legalize/Legalize.fir b/src/test/resources/passes/Legalize/Legalize.fir
new file mode 100644
index 00000000..6e27a0bf
--- /dev/null
+++ b/src/test/resources/passes/Legalize/Legalize.fir
@@ -0,0 +1,41 @@
+
+circuit Legalize :
+  module Legalize :
+    input clk : Clock
+    input reset : UInt<1>
+
+    ; Count till done
+    node done = UInt(6)
+    reg count : UInt<16>, clk with :
+      reset => (reset, UInt(0))
+    when neq(count, done) :
+      count <= add(count, UInt(1))
+    when not(reset) :
+      when eq(count, done) :
+        stop(clk, UInt(1), 0)
+
+    ; Begin Test
+    ; Check assignment to smaller width
+    node x = UInt<32>("hdeadbeef")
+    wire y : UInt<16>
+    y <- x
+    when neq(y, UInt("hbeef")) :
+      printf(clk, UInt(1), "Assertion failed!\n y != beef\n")
+      stop(clk, UInt(1), 1)
+
+    ; Check bit select of literal
+    node b = bits(UInt("hd0"), 7, 5)
+    node b2 = bits(UInt("h9"), 3, 3)
+    when neq(b, UInt(6)) :
+      printf(clk, UInt(1), "Assertion failed!\n b != 6\n")
+      stop(clk, UInt(1), 1)
+    when neq(b2, UInt(1)) :
+      printf(clk, UInt(1), "Assertion failed!\n b2 != 1\n")
+      stop(clk, UInt(1), 1)
+
+    ; Check padding of literal
+    node bar = pad(SInt(-1), 16)
+    node bar_15 = bits(bar, 15, 15)
+    when neq(bar_15, UInt(1)) :
+      printf(clk, UInt(1), "Assertion failed!\n bar_15 != 0\n")
+      stop(clk, UInt(1), 1)
diff --git a/src/test/scala/firrtlTests/LegalizeSpec.scala b/src/test/scala/firrtlTests/LegalizeSpec.scala
new file mode 100644
index 00000000..781f93d7
--- /dev/null
+++ b/src/test/scala/firrtlTests/LegalizeSpec.scala
@@ -0,0 +1,38 @@
+/*
+Copyright (c) 2014 - 2016 The Regents of the University of
+California (Regents). All Rights Reserved.  Redistribution and use in
+source and binary forms, with or without modification, are permitted
+provided that the following conditions are met:
+   * Redistributions of source code must retain the above
+     copyright notice, this list of conditions and the following
+     two paragraphs of disclaimer.
+   * Redistributions in binary form must reproduce the above
+     copyright notice, this list of conditions and the following
+     two paragraphs of disclaimer in the documentation and/or other materials
+     provided with the distribution.
+   * Neither the name of the Regents nor the names of its contributors
+     may be used to endorse or promote products derived from this
+     software without specific prior written permission.
+IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT,
+SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS,
+ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF
+REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT
+LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF
+ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION
+TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR
+MODIFICATIONS.
+*/
+
+package firrtlTests
+
+import firrtl._
+
+class LegalizeSpec extends FirrtlFlatSpec {
+  behavior of "Legalize"
+
+  it should "compile and run" in {
+    runFirrtlTest("Legalize", "/passes/Legalize")
+  }
+}