diff options
| author | Jack | 2016-05-17 14:39:20 -0700 |
|---|---|---|
| committer | jackkoenig | 2016-09-12 21:30:38 -0700 |
| commit | 654f1130b604d74c0a194b2598d70111583b442e (patch) | |
| tree | 9306fd5f3835ebbda36786658fa14d39446d50da /src | |
| parent | 9edf656e11084958d9e90807a4740a57b83babfe (diff) | |
Cast bit select of SInt in PadWidths to SInt
Fixes #172
Diffstat (limited to 'src')
| -rw-r--r-- | src/main/scala/firrtl/passes/PadWidths.scala | 15 |
1 files changed, 11 insertions, 4 deletions
diff --git a/src/main/scala/firrtl/passes/PadWidths.scala b/src/main/scala/firrtl/passes/PadWidths.scala index 4cdcae59..1a134d11 100644 --- a/src/main/scala/firrtl/passes/PadWidths.scala +++ b/src/main/scala/firrtl/passes/PadWidths.scala @@ -18,11 +18,18 @@ object PadWidths extends Pass { case t: SIntType => SIntType(IntWidth(i)) // default case should never be reached } - if (i > width(e)) + if (i > width(e)) { DoPrim(Pad, Seq(e), Seq(i), tx) - else if (i < width(e)) - DoPrim(Bits, Seq(e), Seq(i - 1, 0), tx) - else e + } else if (i < width(e)) { + val e2 = DoPrim(Bits, Seq(e), Seq(i - 1, 0), UIntType(IntWidth(i))) + // Bit Select always returns UInt, cast if selecting from SInt + e.tpe match { + case UIntType(_) => e2 + case SIntType(_) => DoPrim(AsSInt, Seq(e2), Seq.empty, SIntType(IntWidth(i))) + } + } else { + e + } } // Recursive, updates expression so children exp's have correct widths private def onExp(e: Expression): Expression = { |
