diff options
| author | Donggyu Kim | 2016-09-08 22:16:48 -0700 |
|---|---|---|
| committer | Donggyu Kim | 2016-09-13 17:31:03 -0700 |
| commit | b6a12c77223f50be57a682fb4be198ed8ffc3511 (patch) | |
| tree | 5ec96ef20958141c3bc494a221c966b02ff30ede /src | |
| parent | a8d7e31e5cbe6c387930f8d4ef48fda19e59f465 (diff) | |
use case object for WVoid, WInvalid
Diffstat (limited to 'src')
| -rw-r--r-- | src/main/scala/firrtl/Utils.scala | 2 | ||||
| -rw-r--r-- | src/main/scala/firrtl/WIR.scala | 8 | ||||
| -rw-r--r-- | src/main/scala/firrtl/passes/CheckInitialization.scala | 2 | ||||
| -rw-r--r-- | src/main/scala/firrtl/passes/ExpandWhens.scala | 14 |
4 files changed, 13 insertions, 13 deletions
diff --git a/src/main/scala/firrtl/Utils.scala b/src/main/scala/firrtl/Utils.scala index be4700e3..bc1ca704 100644 --- a/src/main/scala/firrtl/Utils.scala +++ b/src/main/scala/firrtl/Utils.scala @@ -337,7 +337,7 @@ object Utils extends LazyLogging { case e: SIntLiteral => MALE case e: Mux => MALE case e: ValidIf => MALE - case e: WInvalid => MALE + case WInvalid => MALE case e => println(e); error("Shouldn't be here") } def get_gender(s: Statement): Gender = s match { diff --git a/src/main/scala/firrtl/WIR.scala b/src/main/scala/firrtl/WIR.scala index 9c63360c..06b5be48 100644 --- a/src/main/scala/firrtl/WIR.scala +++ b/src/main/scala/firrtl/WIR.scala @@ -73,14 +73,14 @@ case class WSubAccess(exp: Expression, index: Expression, tpe: Type, gender: Gen def mapType(f: Type => Type): Expression = this.copy(tpe = f(tpe)) def mapWidth(f: Width => Width): Expression = this } -case class WVoid() extends Expression { +case object WVoid extends Expression { def tpe = UnknownType def serialize: String = "VOID" def mapExpr(f: Expression => Expression): Expression = this def mapType(f: Type => Type): Expression = this def mapWidth(f: Width => Width): Expression = this } -case class WInvalid() extends Expression { +case object WInvalid extends Expression { def tpe = UnknownType def serialize: String = "INVALID" def mapExpr(f: Expression => Expression): Expression = this @@ -126,8 +126,8 @@ class WrappedExpression (val e1: Expression) { case (e1: WSubField, e2: WSubField) => (e1.name equals e2.name) && weq(e1.exp,e2.exp) case (e1: WSubIndex, e2: WSubIndex) => (e1.value == e2.value) && weq(e1.exp,e2.exp) case (e1: WSubAccess, e2: WSubAccess) => weq(e1.index,e2.index) && weq(e1.exp,e2.exp) - case (e1: WVoid, e2: WVoid) => true - case (e1: WInvalid, e2: WInvalid) => true + case (WVoid, WVoid) => true + case (WInvalid, WInvalid) => true case (e1: DoPrim, e2: DoPrim) => e1.op == e2.op && ((e1.consts zip e2.consts) forall {case (x, y) => x == y}) && ((e1.args zip e2.args) forall {case (x, y) => weq(x, y)}) diff --git a/src/main/scala/firrtl/passes/CheckInitialization.scala b/src/main/scala/firrtl/passes/CheckInitialization.scala index f90ee277..7d7f2f32 100644 --- a/src/main/scala/firrtl/passes/CheckInitialization.scala +++ b/src/main/scala/firrtl/passes/CheckInitialization.scala @@ -69,7 +69,7 @@ object CheckInitialization extends Pass { var void = false val voidDeps = collection.mutable.ArrayBuffer[Expression]() def hasVoid(e: Expression): Expression = e match { - case e: WVoid => + case WVoid => void = true e case (_: WRef | _: WSubField) => diff --git a/src/main/scala/firrtl/passes/ExpandWhens.scala b/src/main/scala/firrtl/passes/ExpandWhens.scala index 6bd4bffd..deea3c0e 100644 --- a/src/main/scala/firrtl/passes/ExpandWhens.scala +++ b/src/main/scala/firrtl/passes/ExpandWhens.scala @@ -63,7 +63,7 @@ object ExpandWhens extends Pass { } private def expandNetlist(netlist: Netlist) = netlist map { - case (k, WInvalid()) => IsInvalid(NoInfo, k.e1) + case (k, WInvalid) => IsInvalid(NoInfo, k.e1) case (k, v) => Connect(NoInfo, k.e1, v) } // Searches nested scopes of defaults for lvalue @@ -97,7 +97,7 @@ object ExpandWhens extends Pass { p: Expression) (s: Statement): Statement = s match { case w: DefWire => - netlist ++= (getFemaleRefs(w.name, w.tpe, BIGENDER) map (ref => we(ref) -> WVoid())) + netlist ++= (getFemaleRefs(w.name, w.tpe, BIGENDER) map (ref => we(ref) -> WVoid)) w case r: DefRegister => netlist ++= (getFemaleRefs(r.name, r.tpe, BIGENDER) map (ref => we(ref) -> ref)) @@ -106,7 +106,7 @@ object ExpandWhens extends Pass { netlist(c.loc) = c.expr EmptyStmt case c: IsInvalid => - netlist(c.expr) = WInvalid() + netlist(c.expr) = WInvalid EmptyStmt case s: Conditionally => val conseqNetlist = new Netlist @@ -127,9 +127,9 @@ object ExpandWhens extends Pass { val trueValue = conseqNetlist getOrElse (lvalue, defaultValue) val falseValue = altNetlist getOrElse (lvalue, defaultValue) (trueValue, falseValue) match { - case (WInvalid(), WInvalid()) => WInvalid() - case (WInvalid(), fv) => ValidIf(NOT(s.pred), fv, fv.tpe) - case (tv, WInvalid()) => ValidIf(s.pred, tv, tv.tpe) + case (WInvalid, WInvalid) => WInvalid + case (WInvalid, fv) => ValidIf(NOT(s.pred), fv, fv.tpe) + case (tv, WInvalid) => ValidIf(s.pred, tv, tv.tpe) case (tv, fv) => Mux(s.pred, tv, fv, mux_type_and_widths(tv, fv)) } case None => @@ -165,7 +165,7 @@ object ExpandWhens extends Pass { val netlist = new Netlist // Add ports to netlist netlist ++= (m.ports flatMap { case Port(_, name, dir, tpe) => - getFemaleRefs(name, tpe, to_gender(dir)) map (ref => we(ref) -> WVoid()) + getFemaleRefs(name, tpe, to_gender(dir)) map (ref => we(ref) -> WVoid) }) (netlist, simlist, expandWhens(netlist, Seq(netlist), one)(m.body)) } |
