remove Utils.get_type

4 files changed, 7 insertions, 34 deletions

diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala
index 8b1360ab..e8423dfe 100644
--- a/src/main/scala/firrtl/Emitter.scala
+++ b/src/main/scala/firrtl/Emitter.scala
@@ -260,7 +260,7 @@ class VerilogEmitter extends Emitter {
           simlist += s
           s
         case (s: DefNode) =>
-          val e = WRef(s.name, get_type(s), NodeKind(), MALE)
+          val e = WRef(s.name, s.value.tpe, NodeKind(), MALE)
           netlist(e) = s.value
           s
         case (s) => s
diff --git a/src/main/scala/firrtl/Utils.scala b/src/main/scala/firrtl/Utils.scala
index 0d3c5d34..28f1de05 100644
--- a/src/main/scala/firrtl/Utils.scala
+++ b/src/main/scala/firrtl/Utils.scala
@@ -372,33 +372,6 @@ object Utils extends LazyLogging {
     case EmptyStmt => UNKNOWNGENDER
   }
   def get_gender(p: Port): Gender = if (p.direction == Input) MALE else FEMALE
-  def get_type(s: Statement): Type = s match {
-    case s: DefWire => s.tpe
-    case s: DefRegister => s.tpe
-    case s: DefNode => s.value.tpe
-    case s: DefMemory =>
-      val depth = s.depth
-      val addr = Field("addr", Default, UIntType(IntWidth(scala.math.max(ceil_log2(depth), 1))))
-      val en = Field("en", Default, BoolType)
-      val clk = Field("clk", Default, ClockType)
-      val def_data = Field("data", Default, s.dataType)
-      val rev_data = Field("data", Flip, s.dataType)
-      val mask = Field("mask", Default, passes.createMask(s.dataType))
-      val wmode = Field("wmode", Default, UIntType(IntWidth(1)))
-      val rdata = Field("rdata", Flip, s.dataType)
-      val wdata = Field("wdata", Default, s.dataType)
-      val wmask = Field("wmask", Default, passes.createMask(s.dataType))
-      val read_type = BundleType(Seq(rev_data, addr, en, clk))
-      val write_type = BundleType(Seq(def_data, mask, addr, en, clk))
-      val readwrite_type = BundleType(Seq(wmode, rdata, wdata, wmask, addr, en, clk))
-      BundleType(
-        (s.readers map (Field(_, Flip, read_type))) ++
-        (s.writers map (Field(_, Flip, write_type))) ++
-        (s.readwriters map (Field(_, Flip, readwrite_type)))
-      )
-    case s: WDefInstance => s.tpe
-    case _ => UnknownType
-  }
   def get_info(s: Statement): Info = s match {
     case s: HasInfo => s.info
     case _ => NoInfo
diff --git a/src/main/scala/firrtl/passes/InferTypes.scala b/src/main/scala/firrtl/passes/InferTypes.scala
index a652ed01..79200a58 100644
--- a/src/main/scala/firrtl/passes/InferTypes.scala
+++ b/src/main/scala/firrtl/passes/InferTypes.scala
@@ -66,16 +66,16 @@ object InferTypes extends Pass {
         types(s.name) = t
         s copy (tpe = t)
       case s: DefWire =>
-        val t = remove_unknowns(get_type(s))
+        val t = remove_unknowns(s.tpe)
         types(s.name) = t
         s copy (tpe = t)
       case s: DefNode =>
-        val sx = s map infer_types_e(types)
-        val t = remove_unknowns(get_type(sx))
+        val sx = (s map infer_types_e(types)).asInstanceOf[DefNode]
+        val t = remove_unknowns(sx.value.tpe)
         types(s.name) = t
         sx map infer_types_e(types)
       case s: DefRegister =>
-        val t = remove_unknowns(get_type(s))
+        val t = remove_unknowns(s.tpe)
         types(s.name) = t
         s copy (tpe = t) map infer_types_e(types)
       case s: DefMemory =>
@@ -128,7 +128,7 @@ object CInferTypes extends Pass {
         types(s.name) = s.tpe
         s
       case (s: DefNode) =>
-        types(s.name) = get_type(s)
+        types(s.name) = s.value.tpe
         s
       case (s: DefMemory) =>
         types(s.name) = MemPortUtils.memType(s)
diff --git a/src/main/scala/firrtl/passes/Uniquify.scala b/src/main/scala/firrtl/passes/Uniquify.scala
index 8ea5eb40..758791b2 100644
--- a/src/main/scala/firrtl/passes/Uniquify.scala
+++ b/src/main/scala/firrtl/passes/Uniquify.scala
@@ -242,7 +242,7 @@ object Uniquify extends Pass {
           ) flatMap (recStmtToType)
           Seq(Field(s.name, Default, BundleType(newFields)))
       }
-      case s: DefNode => Seq(Field(s.name, Default, get_type(s)))
+      case s: DefNode => Seq(Field(s.name, Default, s.value.tpe))
       case s: Conditionally => recStmtToType(s.conseq) ++ recStmtToType(s.alt)
       case s: Block => (s.stmts map (recStmtToType)).flatten
       case s => Seq()