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authorDonggyu Kim2016-09-07 21:01:12 -0700
committerDonggyu Kim2016-09-13 13:34:02 -0700
commita38930a841cf4f328c81bd65844eee5e0fa24b54 (patch)
tree97904328f89117edeebba8d064db64bed93274c8 /src
parentdcca7509127e22f1cdcaa916be7538e85ab8da2d (diff)
use MemPortUtils.memType for DefMemory
Diffstat (limited to 'src')
-rw-r--r--src/main/scala/firrtl/Emitter.scala2
-rw-r--r--src/main/scala/firrtl/passes/InferTypes.scala4
-rw-r--r--src/main/scala/firrtl/passes/Uniquify.scala5
3 files changed, 6 insertions, 5 deletions
diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala
index 1610655b..8b1360ab 100644
--- a/src/main/scala/firrtl/Emitter.scala
+++ b/src/main/scala/firrtl/Emitter.scala
@@ -471,7 +471,7 @@ class VerilogEmitter extends Emitter {
instantiate(s.name, s.module, es)
s
case (s: DefMemory) =>
- val mem = WRef(s.name, get_type(s),
+ val mem = WRef(s.name, MemPortUtils.memType(s),
MemKind(s.readers ++ s.writers ++ s.readwriters), UNKNOWNGENDER)
def mem_exp (p: String, f: String) = {
val t1 = field_type(mem.tpe, p)
diff --git a/src/main/scala/firrtl/passes/InferTypes.scala b/src/main/scala/firrtl/passes/InferTypes.scala
index b36298e8..a652ed01 100644
--- a/src/main/scala/firrtl/passes/InferTypes.scala
+++ b/src/main/scala/firrtl/passes/InferTypes.scala
@@ -79,7 +79,7 @@ object InferTypes extends Pass {
types(s.name) = t
s copy (tpe = t) map infer_types_e(types)
case s: DefMemory =>
- val t = remove_unknowns(get_type(s))
+ val t = remove_unknowns(MemPortUtils.memType(s))
types(s.name) = t
s copy (dataType = remove_unknowns(s.dataType))
case s => s map infer_types_s(types) map infer_types_e(types)
@@ -131,7 +131,7 @@ object CInferTypes extends Pass {
types(s.name) = get_type(s)
s
case (s: DefMemory) =>
- types(s.name) = get_type(s)
+ types(s.name) = MemPortUtils.memType(s)
s
case (s: CDefMPort) =>
val t = types getOrElse(s.mem, UnknownType)
diff --git a/src/main/scala/firrtl/passes/Uniquify.scala b/src/main/scala/firrtl/passes/Uniquify.scala
index d034719a..8ea5eb40 100644
--- a/src/main/scala/firrtl/passes/Uniquify.scala
+++ b/src/main/scala/firrtl/passes/Uniquify.scala
@@ -34,6 +34,7 @@ import firrtl._
import firrtl.ir._
import firrtl.Utils._
import firrtl.Mappers._
+import MemPortUtils.memType
/** Resolve name collisions that would occur in [[LowerTypes]]
*
@@ -228,7 +229,7 @@ object Uniquify extends Pass {
case s: WDefInstance => Seq(Field(s.name, Default, s.tpe))
case s: DefMemory => s.dataType match {
case (_: UIntType | _: SIntType) =>
- Seq(Field(s.name, Default, get_type(s)))
+ Seq(Field(s.name, Default, memType(s)))
case tpe: BundleType =>
val newFields = tpe.fields map ( f =>
DefMemory(s.info, f.name, f.tpe, s.depth, s.writeLatency,
@@ -305,7 +306,7 @@ object Uniquify extends Pass {
val dataType = uniquifyNamesType(s.dataType, node.elts)
val mem = s.copy(name = node.name, dataType = dataType)
// Create new mapping to handle references to memory data fields
- val uniqueMemMap = createNameMapping(get_type(s), get_type(mem))
+ val uniqueMemMap = createNameMapping(memType(s), memType(mem))
nameMap(s.name) = NameMapNode(node.name, node.elts ++ uniqueMemMap)
mem
} else {