diff options
| author | Donggyu Kim | 2016-09-08 14:28:03 -0700 |
|---|---|---|
| committer | Donggyu Kim | 2016-09-13 13:33:32 -0700 |
| commit | 62d97c3aae263b1cd333fdc884422d0099dc5cf1 (patch) | |
| tree | 6ace86185ad1fe8756370c7eccde2b987d892a27 /src | |
| parent | b8ee3179ed8070211c95ecbcceda0f7dbf635a13 (diff) | |
MemPortUtils: return correct memory types
Diffstat (limited to 'src')
| -rw-r--r-- | src/main/scala/firrtl/passes/MemUtils.scala | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/src/main/scala/firrtl/passes/MemUtils.scala b/src/main/scala/firrtl/passes/MemUtils.scala index 09be2b38..798b02da 100644 --- a/src/main/scala/firrtl/passes/MemUtils.scala +++ b/src/main/scala/firrtl/passes/MemUtils.scala @@ -146,7 +146,7 @@ object MemPortUtils { def flattenType(t: Type) = UIntType(IntWidth(bitWidth(t))) def defaultPortSeq(mem: DefMemory) = Seq( - Field("addr", Default, UIntType(IntWidth(ceil_log2(mem.depth)))), + Field("addr", Default, UIntType(IntWidth(ceil_log2(mem.depth) max 1))), Field("en", Default, BoolType), Field("clk", Default, ClockType) ) @@ -197,14 +197,14 @@ object MemPortUtils { ) def memToBundle(s: DefMemory) = BundleType( - s.readers.map(Field(_, Default, rPortToBundle(s))) ++ - s.writers.map(Field(_, Default, wPortToBundle(s))) ++ - s.readwriters.map(Field(_, Default, rwPortToBundle(s)))) + s.readers.map(Field(_, Flip, rPortToBundle(s))) ++ + s.writers.map(Field(_, Flip, wPortToBundle(s))) ++ + s.readwriters.map(Field(_, Flip, rwPortToBundle(s)))) def memToFlattenBundle(s: DefMemory) = BundleType( - s.readers.map(Field(_, Default, rPortToFlattenBundle(s))) ++ - s.writers.map(Field(_, Default, wPortToFlattenBundle(s))) ++ - s.readwriters.map(Field(_, Default, rwPortToFlattenBundle(s)))) + s.readers.map(Field(_, Flip, rPortToFlattenBundle(s))) ++ + s.writers.map(Field(_, Flip, wPortToFlattenBundle(s))) ++ + s.readwriters.map(Field(_, Flip, rwPortToFlattenBundle(s)))) // Todo: merge it with memToBundle def memType(mem: DefMemory) = { |