From 62d97c3aae263b1cd333fdc884422d0099dc5cf1 Mon Sep 17 00:00:00 2001
From: Donggyu Kim
Date: Thu, 8 Sep 2016 14:28:03 -0700
Subject: MemPortUtils: return correct memory types

---
 src/main/scala/firrtl/passes/MemUtils.scala | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

(limited to 'src')

diff --git a/src/main/scala/firrtl/passes/MemUtils.scala b/src/main/scala/firrtl/passes/MemUtils.scala
index 09be2b38..798b02da 100644
--- a/src/main/scala/firrtl/passes/MemUtils.scala
+++ b/src/main/scala/firrtl/passes/MemUtils.scala
@@ -146,7 +146,7 @@ object MemPortUtils {
   def flattenType(t: Type) = UIntType(IntWidth(bitWidth(t)))
 
   def defaultPortSeq(mem: DefMemory) = Seq(
-    Field("addr", Default, UIntType(IntWidth(ceil_log2(mem.depth)))),
+    Field("addr", Default, UIntType(IntWidth(ceil_log2(mem.depth) max 1))),
     Field("en", Default, BoolType),
     Field("clk", Default, ClockType)
   )
@@ -197,14 +197,14 @@ object MemPortUtils {
   )
 
   def memToBundle(s: DefMemory) = BundleType(
-    s.readers.map(Field(_, Default, rPortToBundle(s))) ++
-    s.writers.map(Field(_, Default, wPortToBundle(s))) ++
-    s.readwriters.map(Field(_, Default, rwPortToBundle(s))))
+    s.readers.map(Field(_, Flip, rPortToBundle(s))) ++
+    s.writers.map(Field(_, Flip, wPortToBundle(s))) ++
+    s.readwriters.map(Field(_, Flip, rwPortToBundle(s))))
   
   def memToFlattenBundle(s: DefMemory) = BundleType(
-    s.readers.map(Field(_, Default, rPortToFlattenBundle(s))) ++
-    s.writers.map(Field(_, Default, wPortToFlattenBundle(s))) ++
-    s.readwriters.map(Field(_, Default, rwPortToFlattenBundle(s))))
+    s.readers.map(Field(_, Flip, rPortToFlattenBundle(s))) ++
+    s.writers.map(Field(_, Flip, wPortToFlattenBundle(s))) ++
+    s.readwriters.map(Field(_, Flip, rwPortToFlattenBundle(s))))
 
   // Todo: merge it with memToBundle
   def memType(mem: DefMemory) = {
-- 
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