use .head instead of (0)

10 files changed, 35 insertions, 35 deletions

diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala
index 92cb7a54..902dfecd 100644
--- a/src/main/scala/firrtl/Emitter.scala
+++ b/src/main/scala/firrtl/Emitter.scala
@@ -163,9 +163,9 @@ class VerilogEmitter extends Emitter {
        case (t: UIntType) => e
        case (t: SIntType) => Seq("$signed(",e,")")
      }
-     def a0: Expression = doprim.args(0)
+     def a0: Expression = doprim.args.head
      def a1: Expression = doprim.args(1)
-     def c0: Int = doprim.consts(0).toInt
+     def c0: Int = doprim.consts.head.toInt
      def c1: Int = doprim.consts(1).toInt
 
      def checkArgumentLegality(e: Expression) = e match {
diff --git a/src/main/scala/firrtl/PrimOps.scala b/src/main/scala/firrtl/PrimOps.scala
index cf2cb74e..a736dc3d 100644
--- a/src/main/scala/firrtl/PrimOps.scala
+++ b/src/main/scala/firrtl/PrimOps.scala
@@ -132,12 +132,12 @@ object PrimOps extends LazyLogging {
       case (IntWidth(i), IntWidth(j)) => IntWidth(min(i,j))
       case _ => MinWidth(Seq(w1, w2))
     }
-    def t1 = e.args(0).tpe
+    def t1 = e.args.head.tpe
     def t2 = e.args(1).tpe
     def t3 = e.args(2).tpe
-    def w1 = passes.getWidth(e.args(0).tpe)
+    def w1 = passes.getWidth(e.args.head.tpe)
     def w2 = passes.getWidth(e.args(1).tpe)
-    def c1 = IntWidth(e.consts(0))
+    def c1 = IntWidth(e.consts.head)
     def c2 = IntWidth(e.consts(1))
     e copy (tpe = (e.op match {
       case Add => (t1, t2) match {
diff --git a/src/main/scala/firrtl/WIR.scala b/src/main/scala/firrtl/WIR.scala
index 3db1c250..4ca75858 100644
--- a/src/main/scala/firrtl/WIR.scala
+++ b/src/main/scala/firrtl/WIR.scala
@@ -280,7 +280,7 @@ case class CDefMPort(info: Info,
     direction: MPortDir) extends Statement {
   def serialize: String = {
     val dir = direction.serialize
-    s"$dir mport $name = $mem[${exps(0).serialize}], ${exps(1).serialize}" + info.serialize
+    s"$dir mport $name = $mem[${exps.head.serialize}], ${exps(1).serialize}" + info.serialize
   }
   def mapExpr(f: Expression => Expression): Statement = this.copy(exps = exps map f)
   def mapStmt(f: Statement => Statement): Statement = this
diff --git a/src/main/scala/firrtl/passes/ConstProp.scala b/src/main/scala/firrtl/passes/ConstProp.scala
index 789f2e03..bb8ca549 100644
--- a/src/main/scala/firrtl/passes/ConstProp.scala
+++ b/src/main/scala/firrtl/passes/ConstProp.scala
@@ -49,7 +49,7 @@ object ConstProp extends Pass {
     def fold(c1: Literal, c2: Literal): Expression
     def simplify(e: Expression, lhs: Literal, rhs: Expression): Expression
 
-    def apply(e: DoPrim): Expression = (e.args(0), e.args(1)) match {
+    def apply(e: DoPrim): Expression = (e.args.head, e.args(1)) match {
       case (lhs: Literal, rhs: Literal) => fold(lhs, rhs)
       case (lhs: Literal, rhs) => pad(simplify(e, lhs, rhs), e.tpe)
       case (lhs, rhs: Literal) => pad(simplify(e, rhs, lhs), e.tpe)
@@ -102,23 +102,23 @@ object ConstProp extends Pass {
     }
   }
 
-  private def foldConcat(e: DoPrim) = (e.args(0), e.args(1)) match {
+  private def foldConcat(e: DoPrim) = (e.args.head, e.args(1)) match {
     case (UIntLiteral(xv, IntWidth(xw)), UIntLiteral(yv, IntWidth(yw))) => UIntLiteral(xv << yw.toInt | yv, IntWidth(xw + yw))
     case _ => e
   }
 
-  private def foldShiftLeft(e: DoPrim) = e.consts(0).toInt match {
-    case 0 => e.args(0)
-    case x => e.args(0) match {
+  private def foldShiftLeft(e: DoPrim) = e.consts.head.toInt match {
+    case 0 => e.args.head
+    case x => e.args.head match {
       case UIntLiteral(v, IntWidth(w)) => UIntLiteral(v << x, IntWidth(w + x))
       case SIntLiteral(v, IntWidth(w)) => SIntLiteral(v << x, IntWidth(w + x))
       case _ => e
     }
   }
 
-  private def foldShiftRight(e: DoPrim) = e.consts(0).toInt match {
-    case 0 => e.args(0)
-    case x => e.args(0) match {
+  private def foldShiftRight(e: DoPrim) = e.consts.head.toInt match {
+    case 0 => e.args.head
+    case x => e.args.head match {
       // TODO when amount >= x.width, return a zero-width wire
       case UIntLiteral(v, IntWidth(w)) => UIntLiteral(v >> x, IntWidth((w - x) max 1))
       // take sign bit if shift amount is larger than arg width
@@ -153,7 +153,7 @@ object ConstProp extends Pass {
         def === (that: Range) =
           Seq(this.min, this.max, that.min, that.max)
             .sliding(2,1)
-            .map(x => x(0) == x(1))
+            .map(x => x.head == x(1))
             .reduce(_ && _)
         def > (that: Range) = this.min > that.max
         def >= (that: Range) = this.min >= that.max
@@ -177,7 +177,7 @@ object ConstProp extends Pass {
       // Calculates an expression's range of values
       x match {
         case e: DoPrim => {
-          def r0 = range(e.args(0))
+          def r0 = range(e.args.head)
           def r1 = range(e.args(1))
           e.op match {
             // Always true
@@ -209,29 +209,29 @@ object ConstProp extends Pass {
     case Eq => FoldEqual(e)
     case Neq => FoldNotEqual(e)
     case (Lt | Leq | Gt | Geq) => foldComparison(e)
-    case Not => e.args(0) match {
+    case Not => e.args.head match {
       case UIntLiteral(v, IntWidth(w)) => UIntLiteral(v ^ ((BigInt(1) << w.toInt) - 1), IntWidth(w))
       case _ => e
     }
-    case AsUInt => e.args(0) match {
+    case AsUInt => e.args.head match {
       case SIntLiteral(v, IntWidth(w)) => UIntLiteral(v + (if (v < 0) BigInt(1) << w.toInt else 0), IntWidth(w))
       case u: UIntLiteral => u
       case _ => e
     }
-    case AsSInt => e.args(0) match {
+    case AsSInt => e.args.head match {
       case UIntLiteral(v, IntWidth(w)) => SIntLiteral(v - ((v >> (w.toInt-1)) << w.toInt), IntWidth(w))
       case s: SIntLiteral => s
       case _ => e
     }
-    case Pad => e.args(0) match {
-      case UIntLiteral(v, _) => UIntLiteral(v, IntWidth(e.consts(0)))
-      case SIntLiteral(v, _) => SIntLiteral(v, IntWidth(e.consts(0)))
-      case _ if bitWidth(e.args(0).tpe) == e.consts(0) => e.args(0)
+    case Pad => e.args.head match {
+      case UIntLiteral(v, _) => UIntLiteral(v, IntWidth(e.consts.head))
+      case SIntLiteral(v, _) => SIntLiteral(v, IntWidth(e.consts.head))
+      case _ if bitWidth(e.args.head.tpe) == e.consts.head => e.args.head
       case _ => e
     }
-    case Bits => e.args(0) match {
+    case Bits => e.args.head match {
       case lit: Literal => {
-        val hi = e.consts(0).toInt
+        val hi = e.consts.head.toInt
         val lo = e.consts(1).toInt
         require(hi >= lo)
         UIntLiteral((lit.value >> lo) & ((BigInt(1) << (hi - lo + 1)) - 1), getWidth(e.tpe))
diff --git a/src/main/scala/firrtl/passes/InferReadWrite.scala b/src/main/scala/firrtl/passes/InferReadWrite.scala
index 34359c14..74800cf5 100644
--- a/src/main/scala/firrtl/passes/InferReadWrite.scala
+++ b/src/main/scala/firrtl/passes/InferReadWrite.scala
@@ -80,12 +80,12 @@ object InferReadWritePass extends Pass {
     case (DoPrim(Not, args, _, _), _) => weq(args.head, b)
     // b ?= Eq(a, 0) or b ?= Eq(0, a)
     case (_, DoPrim(Eq, args, _, _)) =>
-      weq(args(0), a) && weq(args(1), zero) ||
-      weq(args(1), a) && weq(args(0), zero)
+      weq(args.head, a) && weq(args(1), zero) ||
+      weq(args(1), a) && weq(args.head, zero)
     // a ?= Eq(b, 0) or b ?= Eq(0, a)
     case (DoPrim(Eq, args, _, _), _) =>
-      weq(args(0), b) && weq(args(1), zero) ||
-      weq(args(1), b) && weq(args(0), zero)
+      weq(args.head, b) && weq(args(1), zero) ||
+      weq(args(1), b) && weq(args.head, zero)
     case _ => false
   }
 
diff --git a/src/main/scala/firrtl/passes/MemUtils.scala b/src/main/scala/firrtl/passes/MemUtils.scala
index 1091db5f..7e2623c4 100644
--- a/src/main/scala/firrtl/passes/MemUtils.scala
+++ b/src/main/scala/firrtl/passes/MemUtils.scala
@@ -35,7 +35,7 @@ import firrtl.PrimOps._
 object seqCat {
   def apply(args: Seq[Expression]): Expression = args.length match {
     case 0 => error("Empty Seq passed to seqcat")
-    case 1 => args(0)
+    case 1 => args.head
     case 2 => DoPrim(PrimOps.Cat, args, Nil, UIntType(UnknownWidth))
     case _ =>
       val (high, low) = args splitAt (args.length / 2)
diff --git a/src/main/scala/firrtl/passes/PadWidths.scala b/src/main/scala/firrtl/passes/PadWidths.scala
index 4c198bab..e0a2e304 100644
--- a/src/main/scala/firrtl/passes/PadWidths.scala
+++ b/src/main/scala/firrtl/passes/PadWidths.scala
@@ -42,10 +42,10 @@ object PadWidths extends Pass {
         e map fixup((e.args map (width(_)) foldLeft 0)(math.max(_, _)))
       case Dshl =>
         // special case as args aren't all same width
-        e copy (op = Dshlw, args = Seq(fixup(width(e.tpe))(e.args(0)), e.args(1)))
+        e copy (op = Dshlw, args = Seq(fixup(width(e.tpe))(e.args.head), e.args(1)))
       case Shl =>
         // special case as arg should be same width as result
-        e copy (op = Shlw, args = Seq(fixup(width(e.tpe))(e.args(0))))
+        e copy (op = Shlw, args = Seq(fixup(width(e.tpe))(e.args.head)))
       case _ => e
     }
     case e => e
diff --git a/src/main/scala/firrtl/passes/Passes.scala b/src/main/scala/firrtl/passes/Passes.scala
index 7f53fac8..8264c6ac 100644
--- a/src/main/scala/firrtl/passes/Passes.scala
+++ b/src/main/scala/firrtl/passes/Passes.scala
@@ -211,7 +211,7 @@ object Legalize extends Pass {
     }
   }
   private def legalizeBits(expr: DoPrim): Expression = {
-    lazy val (hi, low) = (expr.consts(0), expr.consts(1))
+    lazy val (hi, low) = (expr.consts.head, expr.consts(1))
     lazy val mask = (BigInt(1) << (hi - low + 1).toInt) - 1
     lazy val width = IntWidth(hi - low + 1)
     expr.args.head match {
diff --git a/src/main/scala/firrtl/passes/RemoveAccesses.scala b/src/main/scala/firrtl/passes/RemoveAccesses.scala
index 933c3543..16a4d928 100644
--- a/src/main/scala/firrtl/passes/RemoveAccesses.scala
+++ b/src/main/scala/firrtl/passes/RemoveAccesses.scala
@@ -115,7 +115,7 @@ object RemoveAccesses extends Pass {
         def removeFemale(info: Info, loc: Expression): Expression = loc match {
           case (_: WSubAccess| _: WSubField| _: WSubIndex| _: WRef) if (hasAccess(loc)) => 
             val ls = getLocations(loc)
-            if (ls.size == 1 & weq(ls(0).guard,one)) loc
+            if (ls.size == 1 & weq(ls.head.guard,one)) loc
             else {
               val (wire, temp) = create_temp(loc)
               stmts += wire
diff --git a/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala b/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala
index c1b0de1e..2c2e3fd6 100644
--- a/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala
+++ b/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala
@@ -146,7 +146,7 @@ object RemoveCHIRRTL extends Pass {
           }
       }
       Block(
-        (addrs map (x => Connect(s.info, SubField(SubField(Reference(s.mem, ut), s.name, ut), x, ut), s.exps(0)))) ++
+        (addrs map (x => Connect(s.info, SubField(SubField(Reference(s.mem, ut), s.name, ut), x, ut), s.exps.head))) ++
         (clks map (x => Connect(s.info, SubField(SubField(Reference(s.mem, ut), s.name, ut), x, ut), s.exps(1)))) ++
         (ens map (x => Connect(s.info,SubField(SubField(Reference(s.mem,ut), s.name, ut), x, ut), one))))
     }