clean up ReplSeqMem

1 files changed, 39 insertions, 57 deletions

diff --git a/src/main/scala/firrtl/passes/ReplSeqMem.scala b/src/main/scala/firrtl/passes/ReplSeqMem.scala
index ae842a0b..c2c1b303 100644
--- a/src/main/scala/firrtl/passes/ReplSeqMem.scala
+++ b/src/main/scala/firrtl/passes/ReplSeqMem.scala
@@ -2,12 +2,12 @@
 
 package firrtl.passes
 
-import com.typesafe.scalalogging.LazyLogging
 import firrtl._
 import firrtl.ir._
 import Annotations._
-import java.io.Writer
 import AnalysisUtils._
+import Utils.error
+import java.io.{File, CharArrayWriter, PrintWriter}
 
 sealed trait PassOption
 case object InputConfigFileName extends PassOption
@@ -15,11 +15,9 @@ case object OutputConfigFileName extends PassOption
 case object PassCircuitName extends PassOption
 
 object PassConfigUtil {
-
+  type PassOptionMap = Map[PassOption, String]
+ 
   def getPassOptions(t: String, usage: String = "") = {
-    
-    type PassOptionMap = Map[PassOption, String] 
-
     // can't use space to delimit sub arguments (otherwise, Driver.scala will throw error)
     val passArgList = t.split(":").toList
     
@@ -38,25 +36,24 @@ object PassConfigUtil {
     }
     nextPassOption(Map[PassOption, String](), passArgList)
   }
-
 }
 
 class ConfWriter(filename: String) {
-  val outputBuffer = new java.io.CharArrayWriter
+  val outputBuffer = new CharArrayWriter
   def append(m: DefMemory) = {
     // legacy
     val maskGran = getInfo(m.info, "maskGran")
-    val writers = m.writers map (x => if (maskGran == None) "write" else "mwrite")
     val readers = List.fill(m.readers.length)("read")
-    val readwriters = m.readwriters map (x => if (maskGran == None) "rw" else "mrw")
-    val ports = (writers ++ readers ++ readwriters).mkString(",")
-    val maskGranConf = if (maskGran == None) "" else s"mask_gran ${maskGran.get}"
+    val writers = List.fill(m.writers.length)(if (maskGran == None) "write" else "mwrite")
+    val readwriters = List.fill(m.readwriters.length)(if (maskGran == None) "rw" else "mrw")
+    val ports = (writers ++ readers ++ readwriters) mkString ","
+    val maskGranConf = maskGran match { case None => "" case Some(p) => s"mask_gran $p" }
     val width = bitWidth(m.dataType)
     val conf = s"name ${m.name} depth ${m.depth} width ${width} ports ${ports} ${maskGranConf} \n"
     outputBuffer.append(conf)
   }
   def serialize = {
-    val outputFile = new java.io.PrintWriter(filename)
+    val outputFile = new PrintWriter(filename)
     outputFile.write(outputBuffer.toString)
     outputFile.close()
   }
@@ -91,50 +88,35 @@ Optional Arguments:
     error("No circuit name specified for ReplSeqMem!" + usage)
   )
   val target = CircuitName(passCircuit)
-  def duplicate(n: Named) = this.copy(t=t.replace("-c:"+passCircuit, "-c:"+n.name))
-  
+  def duplicate(n: Named) = this copy (t = (t replace (s"-c:$passCircuit", s"-c:${n.name}")))
 }
 
-class ReplSeqMem(transID: TransID) extends Transform with LazyLogging {
-  def execute(circuit:Circuit, map: AnnotationMap) = 
-    map get transID match {
-      case Some(p) => p get CircuitName(circuit.main) match {
-        case Some(ReplSeqMemAnnotation(t, _)) => {
-
-          val inputFileName = PassConfigUtil.getPassOptions(t).getOrElse(InputConfigFileName, "")
-          val inConfigFile = {
-            if (inputFileName.isEmpty) None 
-            else if (new java.io.File(inputFileName).exists) Some(new YamlFileReader(inputFileName))
-            else error("Input configuration file does not exist!")
-          }
-
-          val outConfigFile = new ConfWriter(PassConfigUtil.getPassOptions(t).get(OutputConfigFileName).get)
-          TransformResult(
-            (
-              Seq(
-                Legalize,
-                AnnotateMemMacros,
-                UpdateDuplicateMemMacros,
-                new AnnotateValidMemConfigs(inConfigFile),
-                new ReplaceMemMacros(outConfigFile),
-                RemoveEmpty,
-                CheckInitialization,
-                ResolveKinds,                                       // Must be run for the transform to work!
-                InferTypes,
-                ResolveGenders
-              ) foldLeft circuit
-            ) { 
-              (c, pass) =>
-                val x = Utils.time(pass.name)(pass run c)
-                logger debug x.serialize
-                x
-            } , 
-            None, 
-            Some(map)
-          )
-        }  
-        case _ => error("Unexpected transform annotation")
-      }
-      case _ => TransformResult(circuit, None, Some(map))
+class ReplSeqMem(transID: TransID) extends Transform with SimpleRun {
+  def passSeq(inConfigFile: Option[YamlFileReader], outConfigFile: ConfWriter) =
+    Seq(Legalize,
+        AnnotateMemMacros,
+        UpdateDuplicateMemMacros,
+        new AnnotateValidMemConfigs(inConfigFile),
+        new ReplaceMemMacros(outConfigFile),
+        RemoveEmpty,
+        CheckInitialization,
+        InferTypes,
+        ResolveKinds,         // Must be run for the transform to work!
+        ResolveGenders)
+
+  def execute(c: Circuit, map: AnnotationMap) = map get transID match {
+    case Some(p) => p get CircuitName(c.main) match {
+      case Some(ReplSeqMemAnnotation(t, _)) =>
+        val inputFileName = PassConfigUtil.getPassOptions(t).getOrElse(InputConfigFileName, "")
+        val inConfigFile = {
+          if (inputFileName.isEmpty) None 
+          else if (new File(inputFileName).exists) Some(new YamlFileReader(inputFileName))
+          else error("Input configuration file does not exist!")
+        }
+        val outConfigFile = new ConfWriter(PassConfigUtil.getPassOptions(t)(OutputConfigFileName))
+        run(c, passSeq(inConfigFile, outConfigFile))
+      case _ => error("Unexpected transform annotation")
     }
-}
\ No newline at end of file
+    case _ => TransformResult(c)
+  }
+}