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2016-09-25Change file name ReplacesSubAccesses ReplaceAccesschick
2016-09-25convert all occurencess of BigInt == Int to BigInt == BigIntchick
2016-09-25Fix Anonymous function convertible to a method valuechick
2016-09-25Minor fixes, typo in wordchick
2016-09-25Use empty-parens as appropriate for f: => Unit callschick
2016-09-23use .count instead of filter and sizechick
2016-09-23Use parens on Unit methodschick
2016-09-23use .isEmpty, .nonEmpty, isDefinedchick
2016-09-23use .indiceschick
2016-09-23use .head instead of (0)chick
2016-09-22Fixed width inference for add, sub (#312)Adam Izraelevitz
2016-09-21Fix clock connections in InferReadWrite (#310)Donggyu
2016-09-21swap functions in MemPortUtils and MemTransformUtils properly for further ref...Donggyu Kim
2016-09-21refactor AnnotateValidMemConfigsDonggyu Kim
2016-09-21refactor ReplaceMemMacrosDonggyu Kim
2016-09-21refactor UpdateDuplicateMemMacrosDonggyu Kim
2016-09-21clean up ReplSeqMemDonggyu Kim
2016-09-21refactor AnnotateMemMacrosDonggyu Kim
2016-09-21refactor InferReadWriteDonggyu Kim
2016-09-21generalize Analysis.getConnects for code resuseDonggyu Kim
2016-09-16fill empty module body with "begin end" (#305)Yunsup Lee
2016-09-15Fix non-determinism bug in ExpandWhens (#303)Jack Koenig
2016-09-14fix spaces in WIR.scalaDonggyu Kim
2016-09-14style fixes for Compiler.scala, LoweringCompiler.scalaDonggyu Kim
2016-09-14Fix for more general case of getConnectOrigin with reg feedback (#301)Angie Wang
2016-09-14Added Rob.fir for regression testing (#258)Donggyu
2016-09-14fix enable signal inferecne for smems' read ports (#289)Donggyu
2016-09-14Fixed infinite loop for finding connect origin in ReplSeqMem (#300)Angie Wang
2016-09-13Fix a lurking width-inference bug; improve adjacent style (#298)Andrew Waterman
2016-09-13use BoolType for UIntType(IntWidth(1))Donggyu Kim
2016-09-13remove VIndentDonggyu Kim
2016-09-13use case object for WVoid, WInvalidDonggyu Kim
2016-09-13cache IntWidths to avoid redudant object creationsDonggyu Kim
2016-09-13use case object for KindDonggyu Kim
2016-09-13clean up PadWidthDonggyu Kim
2016-09-13clean up LowerTypesDonggyu Kim
2016-09-13clean up Passes.scalaDonggyu Kim
2016-09-13type aliasesDonggyu Kim
2016-09-13remove Utils.{width_BANG, long_BANG}Donggyu Kim
2016-09-13remove Utils.get_typeDonggyu Kim
2016-09-13use MemPortUtils.memType for DefMemoryDonggyu Kim
2016-09-13remove Utils.{mapr, get_name} and fix spacesDonggyu Kim
2016-09-13MemPortUtils: return correct memory typesDonggyu Kim
2016-09-13clean up MemUtilsDonggyu Kim
2016-09-12Add LegalizeSpec for testing Verilog Legalization passJack
2016-09-12Add legalization of pad operation on literals.Jack
2016-09-12Cast bit select of SInt in PadWidths to SIntJack
2016-09-12Legalize bit select. Run Legalize after PadWidths.Jack
2016-09-12Change Legalize Connect to respect SIntJack
2016-09-12Change Legalize Shift Right to respect SIntjackkoenig
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